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Mitsubishi
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MH16S64AMA-12
Datasheet
52 pgs1.07 Mb0

Mitsubishi MH16S64AMA-12, MH16S64AMA-8, MH16S64AMA-10 Datasheet

Preliminary Spec.
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64AMA is 16777216 - word by 64-bit Synchronous DRAM module. This consists of sixteen industry standard 16Mx4 Synchronous DRAMs in TSOP and one industory standard EEPROM in TSSOP. The mounting of TSOP on a card edge Dual Inline package provides any application where high densities and large quantities of memory are required. This is a socket type - memory modules, suitable for easy interchange or addition of modules.
FEATURES
Frequency
-8
-10 100MHz 8ns(CL=3)
125MHz
CLK Access Time
(Component SDRAM)
6ns(CL=3)
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
85pin
94pin 95pin
1pin
10pin 11pin
-12 83MHz
Utilizes industry standard 16M x 4 Synchronous DRAMs TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 125MHz/100MHz/83MHz
Fully synchronous operation referenced to clock rising edge
Dual bank operation controlled by BA0,1(Bank Address) /CAS latency- 2/3(programmable)
Burst length- 1/2/4/8(programmable) Burst type- sequential / interleave(programmable) Column access - random Auto precharge / All bank precharge controlled by A10 Auto refresh and Self refresh 4096 refresh cycle /64ms LVTTL Interface
8ns(CL=3)
124pin
125pin
Back side
168pin
Front side
40pin
41pin
84pin
APPLICATION
main memory or graphic memory in computer systems
MIT-DS-0127-0.0
MITSUBISHI ELECTRIC
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1
4. Mar.1997
Preliminary Spec.
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1 2 DQ0 44 NC 3 DQ1 45 /S2 4 DQ2 46 DQMB2 5 DQ3 47 DQMB3 6 VDD 48 NC 7 DQ4 49 VDD 8 DQ5 50 NC
9 DQ6 51 NC 10 DQ7 52 11 DQ8 53 12 13 DQ9 55 DQ16 14 DQ10 56 DQ17 15 DQ11 57 DQ18 16 DQ12 58 DQ19 17 DQ13 59 VDD 18 VDD 60 DQ20 19 DQ14 61 NC 20 DQ15 62 NC 21 22 23 VSS 65 DQ21 24 NC 66 DQ22 25 NC 67 DQ23 26 VDD 68 27 28 DQMB0 70 DQ25 29 DQMB1 71 DQ26 30 /S0 72 DQ27 31 NC 73 VDD 32 VSS 74 DQ28 33 A0 75 DQ29 34 A2 76 DQ30 35 A4 77 DQ31 36 A6 78 VSS 37 A8 79 38 39 40 VDD 82 SDA 41 VDD 83 SCL 42 CK0 84 VDD
VSS
VSS
NC NC
/WE0
A10 BA1
43
54 VSS
63 64 VSS
69 DQ24
80 NC 81 NC
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
VSS 85
86 87 88 89 90 91 92
93 NC NC
NC
VSS 110
CK2
94
95
96
97
98
99
100 101 102 103 104 105 106 107 108 109
111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126
VSS 127 DQ32 128 DQ33 129 DQ34 130 DQMB6 DQ35 131 DQMB7
VDD 132 DQ36 133 VDD DQ37 134 NC DQ38 135 NC DQ39 136 DQ40 137
VSS 138 VSS DQ41 139 DQ48 DQ42 140 DQ49 DQ43 141 DQ50 DQ44 142 DQ51 DQ45 143 VDD
VDD 144 DQ52 DQ46 145 NC DQ47 146 NC
NC NC
VSS 149 DQ53
NC 150 DQ54 NC 151 DQ55
VDD 152 VSS
/CAS 153 DQ56 DQMB4 154 DQ57 DQMB5 155 DQ58
NC
/RAS 157 VDD
VSS 158 DQ60
A1 159 DQ61 A3 160 DQ62 A5 161 DQ63 A7 162 VSS
A9 163 BA0 A11
VDD 166 SA1 CK1 167 SA2
NC
147 NC 148 VSS
156 DQ59
164 NC 165 SA0
168 VDD
VSS
CKE0
NC
NC
NC NC
CK3
NC = No Connection
MIT-DS-0127-0.0
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4. Mar.1997
Preliminary Spec.
Block Diagram
/S0
DQMB0 DQMB4
DQM /CS
DQ0 DQ1 DQ2 DQ3
I/O 0
I/O 1 I/O 2 I/O 3
D0
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DQ32 DQ33 DQ34 DQ35
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
D8
DQ4 DQ5 DQ6 DQ7
DQMB1
DQ8 DQ9 DQ10 DQ11
DQ12 DQ13 DQ14 DQ15
/S2
DQMB2 DQMB6
DQ16 DQ17 DQ18 DQ19
DQ20 DQ21 DQ22 DQ23
DQMB3
DQ24 DQ25 DQ26 DQ27
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
DQM /CS
I/O 0
I/O 0
I/O 1
I/O 1 I/O 2
I/O 2 I/O 3
I/O 3
DQM /CS
DQM /CS
I/O 0
I/O 0
I/O 1
I/O 1 I/O 2
I/O 2 I/O 3
I/O 3
DQM /CS
DQM /CS
I/O 0
I/O 0
I/O 1
I/O 1 I/O 2
I/O 2 I/O 3
I/O 3
D1
D2
D3
D4
D0
D5
D0
D6
D0
DQ36 DQ37 DQ38 DQ39
DQMB5
DQ40 DQ41 DQ42 DQ43
DQ44 DQ45 DQ46 DQ47
DQ48 DQ49 DQ50 DQ51
DQ52 DQ53 DQ54 DQ55
DQMB7
DQ56 DQ57 DQ58 DQ59
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
D9
D10
D11
D12
D13
D14
DQM /CS
DQ28 DQ29 DQ30 DQ31
/RAS /CAS
/WE
BA0,BA1,A<11:0> D0 - D15
CK,DQ=10Ω
Vcc Vss
DQM /CS
I/O 0
I/O 0
I/O 1
I/O 1 I/O 2
I/O 2 I/O 3
I/O 3
D7
D0
D0 - D15 D0 - D15 D0 - D15
D0 - D15 D0 - D15
MIT-DS-0127-0.0
DQ60 DQ61 DQ62 DQ63
CKE0 D0 - D7
3.3V
CKE1 D8 - D15
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SCL
DQM /CS
I/O 0
I/O 1 I/O 2 I/O 3
SA0 SA1 SA2
D15
CK0 CK1 CK2 CK3
SERIAL PD
A0 A1 A2
4SDRAMs 4SDRAMs 4SDRAMs 4SDRAMs
SDA
4. Mar.1997
Preliminary Spec.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table I
Byte Function described SPD enrty data SPD DATA(hex)
0 Defines # bytes written into serial memory at module mfgr 128 80 1 Total # bytes of SPD memory device 256 Bytes 08 2 Fundamental memory type SDRAM 04 3 # Row Addresses on this assembly A0-A11 0C 4 # Column Addresses on this assembly A0-A9 0A 5 # Module Banks on this assembly 1BANK 01 6 Data Width of this assembly... x64 40 7 ... Data Width continuation 0 00 8 Voltage interface standard of this assembly LVTTL 01 9 SDRAM Cycletime at Max. Supported CAS Latency (CL). -8 8ns 80
Cycle time for CL=3 -10 10ns A0
-12 12ns C0
10 SDRAM Access from Clock -8 6ns 60
tAC for CL=3 -10 8ns 80
-12 8ns 80 11 DIMM Configuration type (Non-parity,Parity,ECC) Non-PARITY 00 12 Refresh Rate/Type self refresh(15.625uS) 80 13 SDRAM width,Primary DRAM x4 04 14 Error Checking SDRAM data width N/A 00
Minimum Clock Delay,Back to Back Random Column Addresses
15 16 Burst Lengths Supported 1/2/4/8 0F 17 # Banks on Each SDRAM device 4bank 04 18 CAS# Latency CL=2/3 06 19 CS# Latency 0 01 20 Write Latency 0 01 21 SDRAM Module Attributes non-buffered,non-registered 00 22 SDRAM Device Attributes:General Precharge All,Auto precharge 06 23 SDRAM Cycle time(2nd highest CAS latency) -8 13ns D0
Cycle time for CL=2 -10 14ns E0
-12 15ns F0 24 SDRAM Access form Clock(2nd highest CAS latency) -8 7ns 70
tAC for CL=2 -10 8ns 80
-12 9ns 90 25 SDRAM Cycle time(3rd highest CAS latency) -8 N/A 00
Cycle time for CL= -10 N/A 00
-12 N/A 00 26 SDRAM Access form Clock(3rd highest CAS latency) -8 N/A 00
tAC for CL= -10 N/A 00
-12 N/A 00 27 Precharge to Active Minimum -8 24ns 18
-10 30ns 1E
-12 30ns 1E 28 Row Active to Row Active Min. -8 16ns 10
-10 20ns 14
-12 24ns 18
1 01
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Preliminary Spec.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
29 RAS to CAS Delay Min -8 24ns 18
-10 30ns 1E
-12 30ns 1E
30 Active to Precharge Min -8 56ns 38
-10 60ns 3C
-12 70ns 46
31 Density of each bank on module 128MByte 20
32-61 Superset Information (may be used in future) option 00
62 SPD Revision rev 1 01 63 Checksum for bytes 0-62 Check sum for -8 43
Check sum for -10 B7 Check sum for -12 05
64-71 Manufactures Jedec ID code per JEP-108E MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
73-90 Manufactures Part Number MH16S64AMA-8 4D483136533634414D412D382D38202020202020
MH16S64AMA-10 4D483136533634414D412D313031302020202020
MH16S64AMA-12 4D483136533634414D412D313231322020202020 91-92 Revision Code PCB revision rrrr 93-94 Manufacturing date year/week code yyww 95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacture Specific Data option 00
126 Intetl specification frequency 66MHz 66 127 Intel specification CAS# Latency support CL=3: 04H, CL=2/3: 06H 06
128+ Unused storage locations open 00
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Preliminary Spec.
PIN FUNCTION
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CK (CK0 ~ CK3)
CKE0 Input
/S (/S0,/S2)
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising edge of CK
Clock Enable:CKE controls internal clock.When CKE is low,internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE E becomes asynchronous input.Self refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means No Operation.
A0-11 specify the Row/Column Address in conjunction with BA.The Row Address is specified by A0-11.The Column Address is specified by A0-9.A10 is also used to indicate precharge option.When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
SDA
SA0-3
MIT-DS-0127-0.0
Bank Address:BA0,1 is not simply BA.BA specifies the bank to which a command is applied.BA0,1 must be set with ACT,PRE,READ,WRITE commands
Input/Output
Power Supply Power Supply for the memory mounted module.
Input
Output
Input
Data In and Data out are referenced to the rising edge of CK
Din Mask/Output Disable:When DQMB is high in burst write.Din for the current cycle is masked.When DQMB is high in burst read,Dout is disabled at the next but one cycle.
Serial clock for serial PD
Serial data for serial PD
Address input for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
The MH16S64AMA provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge option,respectively. To know the detailed definition of commands please see the command truth table.
CK
/S Chip Select : L=select, H=deselect
/RAS Command
/CAS Command
/WE CKE A10
Command Refresh Option @refresh
command Precharge Option @precharge or read/write command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output data appears after /CAS latency. When A10 =H at this command,the bank is deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
COMMAND TRUTH TABLE
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Precharge All Bank
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L HL L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
CK
n-1CKn
H X L L H L V H X H X L LH H L V L V
L H L H H H X X X H X L H H L X X X H X L L L L L L
/S
/RAS
LX
/CAS
/WE
X X X X X
BA
A10
A0-9 ,A11
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP L H H L L H L X L L H H L L H L L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP L H H L BA TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END) L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL
L L L L
BA TBST ILLEGAL*2 BA,CA,A10
BA,RA BA,A10 PRE/PREA NOP*4
Op-Code, Mode-Add
Op-Code, Mode-Add
BA
Op-Code, Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
Begin Read,Latch CA, Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
Begin Write,Latch CA, Determine Auto-Precharge
Terminate Burst,Latch CA, Begin New Read,Determine Auto-Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine Auto­Precharge*3
Action
MIT-DS-0127-0.0
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4. Mar.1997
Preliminary Spec.
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END) L H H L BA TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2 L L H L BA,A10 PRE/PREA Terminate Burst,Precharge L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L BA TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL L H L L BA,CA,A10 L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
Op-Code, Mode-Add
BA
BA,RA
Op-Code, Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine Auto­Precharge*3 Terminate Burst,Latch CA, Begin Write,Determine Auto­Precharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-0127-0.0
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10
4. Mar.1997
Preliminary Spec.
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP) L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
Op-Code, Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2 L H L X BA,CA,A10 READ/WRITE ILLEGAL*2 L L H H BA,RA ACT ILLEGAL*2 L L H L BA,A10 PRE/PREA ILLEGAL*2 L L L H X REFA ILLEGAL
L L L L
MIT-DS-0127-0.0
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
ELECTRIC
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Preliminary Spec.
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L BA TBST ILLEGAL L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L BA TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL L L H H BA,RA ACT ILLEGAL L L H L BA,A10 PRE/PREA ILLEGAL L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
NOP(Idle after tRC)
MITSUBISHI LSIs
ABBREVIATIONS: H = Hige Level, L = Low Level, X = Don't Care BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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ELECTRIC
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Preliminary Spec.
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
MITSUBISHI LSIs
Current State
SELF - H X X X X X X
REFRESH*1 L H H X X X X
POWER H X X X X X X
DOWN L H X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
CK
n-1CKn
L H L H H H X L H L H H L X L H L H L X X L H L L X X X L L X X X X X
L L X X X X X
H L H X X X X H L L H H H X H L L H H L X H L L H L X X H L L L X X X L X X X X X X
L L X X X X X
/RAS /CAS /WE Add
/S
Action
INVALID Exit Self-Refresh(Idle after tRC) Exit Self-Refresh(Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP(Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State = Power Down Refer to Function Truth Table Begin CK0 Suspend at Next Cycle*3 Exit CK0 Suspend at Next Cycle*3 Maintain CK0 Suspend
ABBREVIATIONS: H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0127-0.0
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Preliminary Spec.
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
WRITEA
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
CKEH
WRITEA READA
CKEL
WRITEA
CKEH
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE READ
READA
READ
READA
PRE
WRITE
WRITEA
WRITE
WRITEA
PRE PRE
REFA
CKEL
CKEH
READA
POWER
DOWN
READ
AUTO
REFRESH
CKEL
CKEH
CKEL
CKEH
READ
SUSPEND
READA
SUSPEND
POWER APPLIED
MIT-DS-0127-0.0
POWER
ON
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
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Automatic Sequence Command Sequence
4. Mar.1997
Preliminary Spec.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500É s.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register(MRS). The mode register stores these date until the next MRS command, which may be issue when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
LATENCY
MODE
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 0 0 0
00
CL 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
/CAS LATENCY
CK
/S /RAS /CAS
LTMODE BT BL
BA0,1 A11-0
BL
0 0 0 0 0 1
R R
2
3 R R R R
BURST
LENGTH
BURST
TYPE
0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
0
1
/WE
BT= 0 BT= 1
1 2 4 8 R R R R
SEQUENTIAL INTERLEAVED
V
1 2 4 8 R R R R
MIT-DS-0127-0.0
R:Reserved for Future Use
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MITSUBISHI ELECTRIC
15
4. Mar.1997
Preliminary Spec.
CK
Command
Address
DQ
Read
Y
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
Write
Y
Q0 Q1 Q2 Q3
D0 D1
D2
D3
Initial Address
A2 A1 A0
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
CL= 3 BL= 4
BL
8
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2
3 4 5 6 3 2 1 0
7 6 5 4
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0127-0.0
0 1 2 3 1 2 3 0
4
2 3 0 1 3 0 0 1
2
1 0
1 2
MITSUBISHI ELECTRIC
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0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 1 0
1 0
4. Mar.1997
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