Mitsubishi MH16M40AJD-6 Datasheet

Preliminary Spec.

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH16M40AJD -6

Proto-2

DESCRIPTION

The MH16M40AJD is a 16M word by 40-bit dynamic
RAM module and consists of 10 industry standard
16M X 4 dynamic RAMs in a TSOP package.
The ICs are mounted on both sides of two small PC
boards (Ceracom) with the flash gold plating and form
a convenient 69-pin WDIP package.

FEATURES

RAS

CAS

access

time

(max.ns)

Address

access

time

(max.ns)

(max.ns)

Type name

MH16M40AJD-6

Utilizes industry standard 16M X 4 DRAMs in TSOP package
Low stand-by power dissipation

13mW (Max) ............................ CMOS lnput level

Low operating power dissipation

MH16M40AJD - 6 ........................ 3242 mW (Max)

Fast-page mode , Read-modify-write,RAS-only refresh
CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, output TTL compatible and low capacitance
4096 refresh cycles every 64ms (A0 - A12) (CbR only)
Includes (0.22uF x 12) decoupling capacitors

5.0V ± 5% Vcc

3.3V Vdd by onboard mounted regulators
TTL input converted to LVTTL by onboard mounted level
shifters.

APPLICATION

Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT

access

time

(max.ns)

60 15 30 110 250015

PIN DESCRIPTION

Pin Name
A0-A12
DQ1-DQ40
RAS 0
CAS 0
W 0

OE 0
Vcc

Vss

Function
Address Inputs
Data Inputs / Outputs
Row Address Strobe Input
Column Address Strobe Input
Write Control Input
Output Enable Input
Power Supply (+5V)
Ground (0V)

OE

access

time

Cycle

time

(min.ns)

Power

dissipa-

tion

(typ.mW)

PIN CONFIGURATION ( TOP VIEW )

DQ1 1
DQ2 2
DQ3 3
DQ4 4
DQ5 5
DQ6 6

Vss 7
DQ7 8
DQ8 9

DQ9 10
DQ10 11
DQ11 12
DQ12 13
DQ13 14

Vcc 15

DQ14 16

/CAS0 17
/RAS0 18

DQ15 19
DQ16 20
DQ17 21

/W0 22

NC 23
DQ18 24
DQ19 25

Vss 26

DQ20 27

A0 28
A1 29
A2 30
A3 31
A4 32
A5 33
A6 34

69 Key Pin
68 Vss
67 DQ40
66 DQ39
65 DQ38
64 DQ37
63 DQ36
62 Vcc
61 DQ35
60 DQ34
59 DQ33
58 DQ32
57 DQ31
56 DQ30
55 DQ29
54 Vss
53 DQ28
52 NC
51 NC
50 DQ27
49 DQ26
48 DQ25
47 /OE0
46 NC
45 DQ24
44 DQ23
43 Vcc
42 DQ22
41 DQ21
40 A12
39 A11
38 A10
37 A9
36 A8
35 A7

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Preliminary Spec.

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH16M40AJD -6

Proto-2

FUNCTION

The MH16M40AJD provide, in addition
to normal read, write, and read-modify-write operations,

a number of other functions, e.g., fast page mode, CAS
before RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.

Table 1 Input conditions for each mode

Operation

Read
Write (Early write)
Write (Delayed write)
Read-modify-write

Hidden refresh
CAS before RAS refresh

Standby

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open

RAS CAS
ACT

ACT
ACT
ACT
ACT
ACT
NAC

ACT
ACT
ACT
ACT
ACT

ACT
DNC

BLOCK DIAGRAM

28,29,30,31,32,33,34,35,36,37,38,39,40

Add
/W0

22

/OE0

47
17

/CAS0

18

/RAS0

SN74CBT3384

Voltage regulator

15

LT1117C

43

Vcc

Vss

ST-3.3

62

C1 to C12

7
26
54
68

0.22 uF

Inputs Input/Output

W

NAC
ACT
ACT
ACT
NAC
NAC
DNC

OE
ACT

DNC
DNC
ACT
ACT
DNC
DNC

M5M467400ATP

M5M467400ATP

M5M467400ATP

M5M467400ATP

M5M467400ATP

M5M467400ATP

M5M467400ATP

CAS

RAS

M5M467400ATP

M5M467400ATP

M5M467400ATP

Row

address address

APD
APD
APD
APD
DNC
DNC
DNC

AddOE WRAS CAS

AddOE WRAS CAS

AddOE WRAS CAS

AddOE WRAS CAS

AddOE WRAS CAS

AddOE WRAS CAS

AddOE WRAS CAS

W

AddOE

AddOE WRAS CAS

AddOE WRAS CAS

Column

APD
APD
APD
APD
DNC
DNC
DNC

Input Output

OPN
VLD
VLD
VLD
OPN
DNC
DNC

SN74CBT3384

VLD
OPN
IVD
VLD
VLD
OPN
OPN

1
2
3
4

5
6
8
9

10
11
12
13

14
16
19
20

21
24

25
27

41
42
44
45

48
49
50
53

55
56
57
58

59
60
61
63

64
65

66
67

DQ1
DQ2

DQ3
DQ4

DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12

DQ13
DQ14
DQ15
DQ16

DQ17
DQ18

DQ19
DQ20

DQ21
DQ22
DQ23

DQ24
DQ25

DQ26
DQ27
DQ28

DQ29
DQ30
DQ31
DQ32

DQ33
DQ34
DQ35
DQ36

DQ37
DQ38

DQ39
DQ40

Refresh Remark

YES

Fast page

YES

mode

YES

identical

YES
YES
YES

NO

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Preliminary Spec.

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol
Vcc
VI
V0
I0
Pd
Topr
Tstg

Supply voltage
Input voltage

Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature

RECOMMENDED OPERATING CONDITIONS

Symbol

Vcc
Vss
VIH
VIL

Note 1 : All voltage values are with respect to Vss

Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs

Parameter Conditions Ratings Unit

Parameter

MH16M40AJD -6

With respect to Vss

Ta=25

C

(Ta=0 ~ 70 , unless otherwise noted) (Note 1)C

Limits

Min Nom Max

5

4.75
0

0

2.0

-0.3

5.25
0

5.5

0.8

Unit

V
V
V
V

MITSUBISHI LSIs

Proto-2

-0.5 ~ 7

-0.5 ~ 6

-0.5 ~ 6
50
15

0 ~ 70

-40 ~ 100

V
V
V

mA

W

C
C

ELECTRICAL CHARACTERISTICS

Symbol

VOH
VOL
IOZ
I I

ICC1 (AV)

ICC2

ICC4(AV)

ICC6(AV)

Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.

High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current

from Vcc operating

Supply current from Vcc , stand-by

Average supply current
from Vcc
Fast-Page-Mode

Average supply current from Vcc
CAS before RAS refresh mode

CAPACITANCE

Symbol Parameter Test conditions

CI (A)

CI (OE)
CI (W)
CI (RAS)
CI (CAS)
CI / O

Input capacitance,
address inputs

Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports

Parameter

(Note 3,4)

(Note 3,4)

(Note 3)

(Ta=0 ~ 70 , Vcc=5V ± 5%, Vss=0V, unless otherwise noted) C

(Ta=0 ~ 70 , Vcc=5V ± 5%, Vss=0V, unless otherwise noted) (Note 2)C

Test conditions

IOH=-2mA
IOL=2mA
Q floating 0V VOUT 3.6V

VII

VII

0V VIN 5.25V, Other inputs pins=0V

RAS, CAS cycling
tRC=tWC=min.
output open

RAS= CAS =VIH, output open
RAS= CAS Vcc -0.2

RAS=VIL, CAS cycling
tPC=min.
output open

CAS before RAS refresh cycling
tRC=min.
output open

VI=Vss
f=1MHZ
Vi=25mVrms

VII

VII

IIV

Limits

Min Max

Typ

2.4
0

-10

-5

900

10

5.4

800

1200

Limits

Min Max

Typ

3.6

0.4
10

20

20
20
20
20
20

Unit

V
V

uA

5

uA

mA

mA

mA

mA

Unit

pF
pF

pF
pF
pF
pF

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Preliminary Spec.

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

MITSUBISHI LSIs

MH16M40AJD -6

Proto-2

IIV

VII

VII

IIV

(Ta=0 ~ 70 , Vcc=5V ± 5%, Vss=0V, unless otherwise noted , see notes 5,12,13)C

(Note 6,7)
(Note 6,8)
(Note 6,9)

(Note 6,10)

(Note 6)
(Note 6)

(Note 11)

Limits

-6

Min Max

15
60
30
35

15
5
0

15
0 15

VII

Unit

ns
ns
ns
ns
ns
ns
ns
ns

SWITCHING CHARACTERISTICS

Symbol

Access time from CAS

tCAC

Access time from RAS

tRAC

Columu address access time

tAA
tCPA

Access time from CAS precharge

tOEA

Access time from OE
Output low impedance time from CAS low

tCLZ

Output disable time after CAS high

tOFF
tOEZ (Note 11)

Output disable time after OE high

Note 5: An initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing CAS before RAS refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to 1TTL loads and 100pF.The reference levels for measuring of output signals are 2.0V(VOH)
and 0.8V(VOL).
7: Assumes that tRCD tRCD(max) and tASC tASC(max).

8: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,

tRAC will increase by amount that tRCD exceeds the value shown.
9: Assumes that tRAD tRAD(max) and tASC tASC(max).

10: Assumes that tCP tCP(max) and tASC tASC(max).
11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT I ± 10 uAI) and is not reference to

VOH(min) or VOL(max).

Parameter

IIV

VII

IIV

VII

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)

(Ta=0 ~ 70 , Vcc=5V ± 5%, Vss=0V, unless otherwise noted See notes 12,13)C

Limits

Symbol

Refresh cycle time

tREF

RAS high pulse width

tRP

Delay time, RAS low to CAS low

tRCD
tCRP

Delay time, CAS high to RAS low

tRPC

Delay time, RAS high to CAS low

tCPN

CAS high pulse width

Column address delay time from RAS low

tRAD
tASR

Row address setup time before RAS low

Column address setup time before CAS low

tASC

Row address hold time after RAS low

tRAH
tCAH

Column address hold time after CAS low

tDZC

Delay time, data to CAS low
Delay time, data to OE low

tDZO

Delay time, CAS high to data

tCDD
tODD

Delay time, OE high to data

tT

Transition time

Note 12: The timing requirements are assumed tT =5ns.
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access

time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
15: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.
16: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.
17: Either tDZC or tDZO must be satisfied.
18: Either tCDD or tODD must be satisfied.
19: tT is measured between VIH(min) and VIL(max).

Parameter

(Note14)

(Note15)

(Note16)

(Note17)
(Note17)
(Note18)
(Note18)
(Note19)

IIV
IIV

VII

IIV

-6

Min Max

64

40

45

20

10

0

10

15

30

0

10

0

10

15

0
0

15
15

50

1

Unit

ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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Preliminary Spec.

Preliminary Spec.

Some of contents are subject to change without notice.

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

Read and Refresh Cycles

Symbol

Read cycle time

tRC

RAS iow pulse width

tRAS

CAS iow pulse width

tCAS
tCSH

CAS hold time after RAS iow

tRSH

RAS hold time after CAS iow

tRCS

Read Setup time after CAS high
Read hold time after CAS iow (Note 20)

tRCH
tRRH (Note 20)

Read hold time after RAS iow

tRAL

Column address to RAS hold time

tOCH

CAS hold time after OE iow

tORH

RAS hold time after OE iow

Note 20: Either tRCH or tRRH must be satisfied for a read cycle.

Parameter

MITSUBISHI LSIs

MH16M40AJD -6

Proto-2

Limits

-6

Min Max

110

10000

60

10000

15
60
15

0
0

10

30
15
15

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Write Cycle (Early Write and Delayed Write)

Symbol

tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH

Write cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS iow
RAS hold time after CAS iow
Write setup time before CAS low
Write hold time after CAS iow
CAS hold time after W iow
RAS hold time after W iow
Write pulse width
Data setup time before CAS iow or W iow
Data hold time after CAS iow or W iow
OE hold time after W iow

Parameter

(Note 22)

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Limits

-6

Min Max

110

10000

60

10000

15
60
15

0

10
15
15
10
0
10
15

31/ Jan./1997MIT - DS - 0069 -1.1

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Preliminary Spec.

Preliminary Spec.

MITSUBISHI LSIs

Some of contents are subject to change without notice.

MH16M40AJD -6

Proto-2

FAST PAGE MODE ( 16,777,216-WORD BY 40-BIT ) DYNAMIC RAM

Read-Write and Read-Modify-Write Cycles

Limits

Symbol

Read write/read modify write cycle time

tRWC

RAS low pulse width

tRAS

CAS low pulse width

tCAS
tCSH

CAS hold time after RAS low
RAS hold time after CAS low

tRSH
tRCS

Read setup time before CAS low

tCWD

Delay time, CAS low to W low

tRWD

Delay time, RAS low to W low

tAWD

Delay time, address to W low

tCWL

CAS hold time after W low

tRWL

RAS hold time after W low

tWP

Write pulse width
Data setup time before W low

tDS

Data hold time after W low

tDH
tOEH

OE hold time after W low

Note 21: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
22: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min)

(for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.

If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.

Parameter

ÅÜ
ÅÖ ÅÖ

ÅÜ

-6

Min Max

(Note21)

(Note22) ns
(Note22)
(Note22)

IIV

IIV

150

95

10000

50

10000
95
50
0
30
75
45
15
15
10

0
10
15

IIV

Unit

IIV

ns
ns
ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns

IIV

Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle) (Note 23)

Limits

Symbol

Fast page mode read/write cycle time

tPC

Fast page mode read write/read modify write cycle time

tPRWC

RAS iow pulse width for read write cycle

tRAS

CAS high pulse width

tCP
tCPRH

RAS hold time after CAS precharge

tCPWD

Delay time, CAS precharge to W iow (Note22)

Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle.
24: tRAS(min) is specified as two cycles of CAS input are performed.
25: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.

Parameter

(Note24)
(Note25)

IIV

-6

Min Max

40
75

100

102400

15

10
35
35

Unit

ns
ns
ns
ns
ns
ns

CAS before RAS Refresh Cycle (Note 26)

Limits

Symbol

CAS setup time before RAS low

tCSR

CAS hold time after RAS low

tCHR
tRSR

Read setup time before RAS low

tRHR

Read hold time after RAS low

Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh
mode.

Parameter

-6

Min Max

10

10

10

10

Unit

ns
ns
ns
ns

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