Mitsubishi MH16D72AKLB-10, MH16D72AKLB-75 Datasheet

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

APPLICATION

Type name

133MHz

MH16D72AKLB-75

- Commands entered on each positive CLK edge

100MHz

Data Rate(DDR) Synchronous DRAM mounted module.

main

[component level]

+ 0.75ns

+ 0.8ns

MH16D72AKLB-10

Some contents are subject to change without notice.

DESCRIPTION

The MH16D72AKLB is 16777216 - word x 72-bit Double

This consists of 9 industry standard 16M x 8 DDR
Synchronous DRAMs in TSOP with SSTL_2 interface which
achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for
memory in computer systems and easy to interchange or
add modules.

FEATURES

MITSUBISHI LSIs

MH16D72AKLB-10,75

93pin

1pin

Max.
Frequency

- Utilizes industry standard 16M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.

- Vdd=Vddq=2.5v±0.2V

CLK
Access Time

- Double data rate architecture; two data transfers per
clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received
with data

- Differential clock inputs (CK0 and /CK0)

- data and data mask referenced to both edges of DQS

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 refresh cycles /64ms

- Auto refresh and Self refresh

- Row address A0-11 / Column address A0-9

- SSTL_2 Interface

- Module 1bank Configration

- Burst Type - sequential/interleave(programmable)

144pin

145pin

184pin

52pin

53pin

92pin

Main memory unit for PC, PCserver

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

1

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

Some contents are subject to change without notice.

PIN CONFIGURATION

PIN
NO.

PIN
NAME

1

VREF

2

DQ0

3

VSS

4

DQ1

5

DQS0

6

DQ2

7

VDD
DQ3

NC

RESET

VSS
DQ8
DQ9

DQS1

15

VDDQ

16
17 58
18
19
20
21
22
23
24
25
26 VSS 67
27
28
29
30
31 DQ19 72
32
33
34
35
36
37 A4 78
38
39
40
41
42

NC
NC

VSS
DQ10
DQ11

CKE0

VDDQ

DQ16
DQ17
DQS2

A9

DQ18

A7

VDDQ

A5

DQ24

VSS
DQ25
DQS3

VDD
DQ26

DQ27

A2

VSS

PIN
NO.

43
44
45
46
47
48
49
50
51
52

53
54
55
56
57

59
60
61
62
63
64
65
66

68
69
70
71

73
74
75
76
77

79
80
81
82
83

KEY

PIN
NAME

A1

CB0
CB1

VDD

DQS8

A0

CB2
VSS

CB3
BA1

DQ32

VDDQ

DQ33
DQS4
DQ34

VSS

BA0
DQ35
DQ40

VDDQ

/WE
DQ41

/CAS

VSS
DQS5
DQ42
DQ43

VDD

NC

DQ48
DQ49

VSS

NC
NC

VDDQ

DQS6
DQ50

DQ51

VSS

VDDID

DQ56

PIN
NO.

84
85
86
87
88
89
90
91
92
93
94
95
96
97
98

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125

PIN
NAME

DQ57

VDD

DQS7

DQ58
DQ59

VSS

NC

SDA

SCL

VSS
DQ4
DQ5

VDDQ

DM0
DQ6
DQ7

VSS

NC
NC

A13

VDDQ

DQ12
DQ13

DM1
VDD

DQ14
DQ15

CKE1

VDDQ

NC

DQ20

A12

VSS

DQ21

A11

DM2
VDD

DQ22

A8

DQ23

VSS

A6

PIN
NO.

126
127
128
129
130
131
132
1338
1349
13510
13611
13712
13813
13914
140
141
142
143
144

145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166

MITSUBISHI LSIs

MH16D72AKLB-10,75

PIN
NAME

DQ28
DQ29

VDDQ

DM3

A3

DQ30

VSS

DQ31

CB4
CB5

VDDQ

CK0

/CK0

VSS
DM8

A10

CB6

VDDQ

CB7

KEY

VSS
DQ36
DQ37

VDD

DM4
DQ38

DQ39

VSS
DQ44

/RAS

DQ45

VDDQ

/S0
/S1

DM5

VSS
DQ46

DQ47

NC

VDDQ

DQ52
DQ53

PIN
NO.
167

168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184

PIN
NAME

NC

VDD

DM6
DQ54
DQ55

VDDQ

NC

DQ60
DQ61

VSS

DM7
DQ62

DQ63

VDDQ

SA0
SA1

SA2

VDDSPD

NC: Not Connected

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

2

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

/S0

BA0-BA1

A0-A11

/RAS

/CAS

CKE0

/WE

/RS0 -> SDRAMs D0-D8

RBA0-RBA1

-> SDRAMs D0-D8

RA0-RA11 -> SDRAMs D0-D8

/RRAS -> SDRAMs D0-D8

/RCAS -> SDRAMs D0-D8

/RCKE0 -> SDRAMs D0-D8

/RWE -> SDRAMs D0-D8

/PCK

PCK

/RESET

CK0

/CK0

Registered Buffer

D0

DM

DQS

/S

D1

DM

DQS

/S

D2

DM

DQS

/S

D3

DM

DQS

/S

D8

DM

DQS

/S

D4

DM

DQS

/S

D5

DM

DQS

/S

D6

DM

DQS

/S

D7

DM

DQS

/S

SA0

SA1

SA2

SERIAL PD

SCL

SDAA0A1A2WP

VDD

D0 to D8

VREF

VSS

D0 to D8

D0 to D8

VDDID

VDDQ

D0 to D8

VDDID: OPEN -> VDD = VDDQ

Some contents are subject to change without notice.

Block Diagram

/RS0

DQS0

DM0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS1

DM1

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

MITSUBISHI LSIs

MH16D72AKLB-10,75

DQS4

DM4

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS5

DM5

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS2

DM2

DQS3

DM3

DQS8

DM8

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQS6

DM6

DQS7

DM7

DQ48
DQ49

DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

VSS -> VDD = VDDQ

PCK0 -> SDRAMs D0-D8,
Registered Buffer

PLL

/PCK0 -> SDRAMs D0-D8,

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

3

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

PIN FUNCTION

Clock: CK0 and /CK0 are differential clock inputs. All address and control input

Data Input/Output: Data bus

SYMBOL

DESCRIPTION

Some contents are subject to change without notice.

TYPE

MITSUBISHI LSIs

MH16D72AKLB-10,75

CK0,/CK0 Input

CKE0

/S0

Input

Input

/RAS, /CAS, /WE Input

A0-11 Input

BA0,1 Input

DQ 0-64
CB 0-7

DQS0-8

DM0-8

Input / Output

Input / Output

Input

signals are sampled on the crossing of the positive edge of CK0 and negative
edge of /CK0. Output (read) data is referenced to the crossings of CK0 and
/CK0 (both directions of crossing).

Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the
internal clock for the following cycle is ceased. CKE0 is also used to select
auto / self refresh. After self refresh mode is started, CKE0 becomes
asynchronous input. Self refresh is maintained as long as CKE0 is low.

Physical Bank Select: When /S0 is high, any command means No Operation.

Combination of /RAS, /CAS, /WE defines basic commands.

A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row
Address is specified by A0-11. The Column Address is specified by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a precharge
command, all banks are precharged.

Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.

Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.

Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.

Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.

VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.

Vddspd

Vref Input

RESET

SDA

SCL

SA0-2

VDDID

Power Supply Power Supply for SPD

SSTL_2 reference voltage.

Input

Input / Output

Input

Input

This signal is asynchronous and is driven low to the register in order to
guarantee the register outputs are low.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM.
A resistor must be connected from the SDA bus line to VDD to act as a pullup.

This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected from the SCL bus time to VDD to act as a pullup.

These signals are tied at the system planar to either VSS or VDD to configure
the serial SPD EEPROM address range.

VDD identification flag

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

4

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

BASIC FUNCTIONS

The MH16D72AKLB provides basic functions, bank (row) activate, burst read / write, bank (row)

burst read (auto-precharge,

READA

)

WRITE command starts burst write to the active bank indicated by BA. Total data length to be

the burst write (auto-precharge,

WRITEA

).

PRE command deactivates the active bank indicated by BA. This command also terminates

(precharge all,

PREA

).

generated internally. After this command, the banks are precharged automatically.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /S0 ,CKE0 and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.

/CK0

CK0

/S0

Chip Select : L=select, H=deselect

/RAS
/CAS

/WE

CKE0

A10

Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command

define basic commands

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the

Write (WRITE) [/RAS =H, /CAS =/WE =L]

written is set by burst length. When A10 =H at this command, the bank is deactivated after

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

burst read /write operation. When A10 =H at this command, all banks are deactivated

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]

REFA command starts auto-refresh cycle. Refresh address including bank address are

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

5

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

COMMAND TRUTH TABLE

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

COMMAND MNEMONIC

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

Row Address Entry &

Bank Activate

Single Bank Precharge PRE H X L L H L V L X

Precharge All Banks PREA H X L L H L H X

Column Address Entry

& Write

Column Address Entry

& Write with

Auto-Precharge

Column Address Entry

& Read

Column Address Entry

& Read with

Auto-Precharge

Auto-Refresh

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit

Burst Terminate

Mode Register Set

ACT H X L L H H V V V

WRITE H X L H L L V L V

WRITEA H X L H L L V H V

READ H X L H L H V L V

READA H X L H L H V H V

REFA H H L L L H X X X

REFSX

TERM

MRS

CKE0

CKE0

n-1

L H H X X X X X X
L H L H H H X X X
H X L H H L X X X
H X L L L L L L V

n

/RAS /CAS /WE BA0,1

/S

A10
/AP

X

A0-9,
11

note

1
2

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.

2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A11 provide the op-code to be written to the selected Mode Register.

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

6

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

Notes

Some contents are subject to change without notice.

FUNCTION TRUTH TABLE

MITSUBISHI LSIs

MH16D72AKLB-10,75

Current State

IDLE H X X X X DESEL NOP

ROW ACTIVE H X X X X DESEL NOP

/S

/RAS /CAS /WE Address Command Action

L H H H X NOP NOP
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10
L L L H X REFA Auto-Refresh

L L L L

L H H H X NOP NOP
L H H L BA TERM NOP

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL

Op-Code,
Mode-Add

READ / WRITE

PRE / PREA

MRS Mode Register Set

WRITE /

WRITEA

ILLEGAL

NOP

Begin Read, Latch CA,
Determine Auto-Precharge

Begin Write, Latch CA,
Determine Auto-Precharge

2
2

4
5

5

2

READ
(Auto-

Precharge

Disabled)

L L H L BA, A10 PRE / PREA Precharge / Precharge All
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM Terminate Burst

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10

L L H H
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

BA, RA

Op-Code,

Mode-Add

MRS ILLEGAL

Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge

WRITE

WRITEA

ACT Bank Active / ILLEGAL

MRS ILLEGAL

ILLEGAL

3

2

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

7

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

FUNCTION TRUTH TABLE (continued)

Notes

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

Current State

WRITE

(Auto-

Precharge

Disabled)

READ with

AUTO

PRECHARGE

/S

/RAS /CAS /WE Address Command Action

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL

Terminate Burst, Latch CA,

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge

L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

Op-Code,
Mode-Add

WRITE /

WRITEA

MRS ILLEGAL

Begin Read, Determine Auto­Precharge

Terminate Burst, Latch CA,
Begin Write, Determine Auto­Precharge

3

3

2

WRITE with

AUTO

PRECHARGE

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL
L L H L BA, A10 PRE / PREA PRECHARGE/ILLEGAL
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L BA TERM ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL
L L H L BA, A10 PRE / PREA PRECHARGE/ILLEGAL
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

Op-Code,
Mode-Add

WRITE /

WRITEA

MRS ILLEGAL

WRITE /

WRITEA

MRS ILLEGAL

ILLEGAL

ILLEGAL

2
2

2
2

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

8

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

FUNCTION TRUTH TABLE (continued)

Notes

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

Current State

PRE -

CHARGING

ROW

ACTIVATING

/S

/RAS /CAS /WE Address Command Action

H X X X X DESEL NOP (Idle after tRP)

L H H H X NOP NOP (Idle after tRP)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA NOP (Idle after tRP)
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Row Active after tRCD)

L H H H X NOP NOP (Row Active after tRCD)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

Op-Code,
Mode-Add

MRS ILLEGAL

MRS ILLEGAL

2
2

2
4

2
2

2
2

WRITE RE­COVERING

MIT-DS-0397-1.3

H X X X X DESEL NOP

L H H H X NOP NOP
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

MRS ILLEGAL

MITSUBISHI ELECTRIC

2
2

2
2

21.Mar.2001

9

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

FUNCTION TRUTH TABLE (continued)

Notes

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

Current State

RE-

FRESHING

MODE

REGISTER

SETTING

/S

/RAS /CAS /WE Address Command Action

H X X X X DESEL NOP (Idle after tRC)

L H H H X NOP NOP (Idle after tRC)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Idle after tRSC)

L H H H X NOP NOP (Idle after tRSC)
L H H L BA TERM ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

Op-Code,
Mode-Add

MRS ILLEGAL

MRS ILLEGAL

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation

NOTES:

1. All entries assume that CKE0 was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

MIT-DS-0397-1.3

21.Mar.2001

MITSUBISHI ELECTRIC

10

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

FUNCTION TRUTH TABLE for CKE

asynchronously

Notes

Some contents are subject to change without notice.

CKE0

Current State

SELF-

REFRESH

POWER

DOWN

ALL BANKS

IDLE

CKE0

n-1

H X X X X X X INVALID

L H H X X X X Exit Self-Refresh (Idle after tRC)
L H L H H H X Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)

H X X X X X X INVALID

L H X X X X X Exit Power Down to Idle

L L X X X X X NOP (Maintain Self-Refresh)
H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL

L X X X X X X Refer to Current State =Power Down

/S /RAS /CAS

n

MITSUBISHI LSIs

MH16D72AKLB-10,75

/WE Add Action

1
1
1
1
1

1
1

2
2

2
2

2
2
2

2

ANY STATE

other than

listed above

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE0 Low to High transition will re-enable CK0 and other inputs
. A minimum setup time must be satisfied before any command other than EXIT.

2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

MIT-DS-0397-1.3

H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Suspend at Next Cycle

L H X X X X X Exit CLK Suspend at Next Cycle
L L X X X X X Maintain CLK Suspend

MITSUBISHI ELECTRIC

3
3

21.Mar.2001

11

1,207.959,552

-BIT (16,777,216-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

Preliminary Spec.

SIMPLIFIED STATE DIAGRAM

REGISTER

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16D72AKLB-10,75

POWER
APPLIED

POWER

ON

PREA

MODE

SET

PRE

CHARGE

ALL

MRS

MRS

Active
Power

Down

CKEH

CKEL

ACTIVE

IDLE

ACT

ROW

REFS

CKEH

REFSX

REFA

CKEL

SELF

REFRESH

AUTO

REFRESH

POWER

DOWN

BURST

STOP

WRITE READ

WRITE READ

WRITEA

WRITE

WRITEA READA

PRE PRE

PRE

READA

READ

READA

READ

READAWRITEA

PRE

CHARGE

TERM

Automatic Sequence
Command Sequence

MIT-DS-0397-1.3

MITSUBISHI ELECTRIC

21.Mar.2001

12