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QCPU(Q Mode)/QnACPU
Programming Manual
(Common Instructions)
Mitsubishi Programmable
Logic Controller
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SAFETY PRECAUTIONS
•
(Always read these cautions before using the product)
Before using this product, please read this manual and the related manuals introduced in this manual,
and pay full attention to safety to handle the product correctly .
Please store this manual in a safe place and make it accessible when required. Always forward a copy of
the manual to the end user.
•
A - 1 A - 1
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REVISIONS
* The manual number is given on the bottom left of the back cover.
Print Date * Manual Number Revision
Dec., 1999 SH (NA)-080039-A First edition
Jun., 2000 SH (NA)-080039-B
Addition
APPENDIX5
Correction
CONTENTS, Section 3.4, 6.6.1, 6.8.6, 6.8.8, 6.8.9, 7.6.8, 9.8, 10.3, 11.2,
APP 1.2, APP 4
Sep., 2000 SH (NA)-080039-C
Addition
Section 9.9, 9.10, 9.11
Correction
CONTENTS, Section 2.5.20, Chapter 4
Section 5.2.5, 6.6.1, 6.8.6, 7.10.1, 8.11.1, 9.3, 11.2, APP 1.2, APP 3,
APP 4
Jun., 2001 SH (NA)-080039-D
Addition model
Q00JCPU, Q00CPU, Q01CPU
Addition
Section 3.9, 11.2.1, 11.2.2, APP 1.3, APP 3.1, APP 3.2, APP 4.1, APP 4.2
Correction
CONTENTS, Section 1.1, 5.3.8, 5.7.1, 6.1.5 ,6.5.2, 6.6.1, 6.8.1, 6.8.2,
6.8.4, 6.8.7, 6.8.8, 6.8.9, 7.1.2, 7.1.4, 7.1.6, 7.1.8, 7.2.1, 7.2.2, 7.2.3,
7.2.4, 7.4.2, 7.5.12, 7.6.6, 7.6.7, 7.6.9, 7.6.10, 7.7.1, 7.7.2, 7.7.3, 7.7.4,
7.9.3, 7.14.1, 9.4, 11.2.2, APP 1.2, APP 1.3, APP 2.1, APP2.1.4, APP 3.2,
APP 4.2
Mar., 2002 SH (NA)-080039-E
Addition model
Q12PHCPU, Q25PHCPU
Addition
Section 11.2.3, APP 3.3, APP 4.3
Correction
CONTENTS, Section 1.1, 1.2, 3.2.2, 3.6, 3.8, 6.6.1, Chapter 9, Section
9.10, APP 1.1
Japanese Manual Version SH-080021-E
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent
licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property
rights which may occur as a result of using the contents noted in this manual.
1999 MITSUBISHI ELECTRIC CORPORATION
A - 2 A - 2
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INTRODUCTION
Thank you for purchasing the Mitsubishi MELSEC-Q Series (Q mode) and MELSEC-QnA Series of
Programmable Logic Controllers.
Before using the product, please read this manual carefully to develop full familiarity with the functions and
performance of the Programmable Logic Controller Q Series (Q mode)/QnA Series you have purchased, so
as to ensure correct use.
A copy of this manual should be forwarded to the end User.
CONTENTS
1. GENERAL DESCRIPTION 1 - 1 to 1 - 4
1.1 Related Programming Manuals .............................................................................................................1 - 1
1.2 Abbreviation and Generic Name............................................................................................................1 - 4
2. INSTRUCTION TABLES 2 - 1 to 2 - 49
2.1 Types of Instructions ..............................................................................................................................2 - 1
2.2 How to Read Instruction Tables.............................................................................................................2 - 2
2.3 Sequence Instructions............................................................................................................................2 - 4
2.3.1 Contact Instruction...........................................................................................................................2 - 4
2.3.2 Connection instructions ...................................................................................................................2 - 5
2.3.3 Output instructions...........................................................................................................................2 - 6
2.3.4 Shift instructions ..............................................................................................................................2 - 6
2.3.5 Master control instructions...............................................................................................................2 - 7
2.3.6 Termination instruction ....................................................................................................................2 - 7
2.3.7 Other instructions.............................................................................................................................2 - 7
2.4 Basic Instructions ...................................................................................................................................2 - 8
2.4.1 Comparison operation instruction ...................................................................................................2 - 8
2.4.2 Arithmetic operation instructions .....................................................................................................2 - 14
2.4.3 Data conversion instructions ...........................................................................................................2 - 19
2.4.4 Data transfer instructions................................................................................................................. 2 - 21
2.4.5 Program branch instruction .............................................................................................................2 - 23
2.4.6 Program execution control instructions........................................................................................... 2 - 23
2.4.7 I/O refresh instructions ....................................................................................................................2 - 23
2.4.8 Other convenient instructions..........................................................................................................2 - 24
2.5 Application Instructions ..........................................................................................................................2 - 25
2.5.1 Logical operation instructions..........................................................................................................2 - 25
2.5.2 Rotation instructions........................................................................................................................2 - 27
2.5.3 Shift instructions ..............................................................................................................................2 - 28
2.5.4 Bit processing instructions...............................................................................................................2 - 28
2.5.5 Data processing instructions ...........................................................................................................2 - 29
2.5.6 Structure creation instructions.........................................................................................................2 - 32
2.5.7 Table operation instructions ............................................................................................................2 - 33
2.5.8 Buffer memory access instructions.................................................................................................2 - 34
2.5.9 Display instructions..........................................................................................................................2 - 34
2.5.10 Debugging and failure diagnosis instructions ............................................................................... 2 - 35
2.5.11 Character string processing instructions.......................................................................................2 - 36
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2.5.12 Special function instructions..........................................................................................................2 - 39
2.5.13 Data control instructions................................................................................................................2 - 41
2.5.14 Switching instructions....................................................................................................................2 - 42
2.5.15 Clock instructions ..........................................................................................................................2 - 43
2.5.16 Peripheral device instructions ....................................................................................................... 2 - 44
2.5.17 Program instructions...................................................................................................................... 2 - 45
2.5.18 Other instructions...........................................................................................................................2 - 45
2.5.19 Instructions for data link.................................................................................................................2 - 46
2.5.20 QCPU instructions.........................................................................................................................2 - 48
2.5.21 Redundant system instructions (For Q4ARCPU) .........................................................................2 - 49
3. CONFIGURATION OF INSTRUCTIONS 3 - 1 to 3 - 24
3.1 Configuration of Instructions .................................................................................................................. 3 - 1
3.2 Designating Data....................................................................................................................................3 - 2
3.2.1 Using bit data...................................................................................................................................3 - 2
3.2.2 Using word (16 bits) data.................................................................................................................3 - 3
3.2.3 Using double word data (32 bits).....................................................................................................3 - 5
3.2.4 Using real number data...................................................................................................................3 - 8
3.2.5 Using character string data .............................................................................................................3 - 9
3.3 Index Modification...................................................................................................................................3 - 10
3.4 Indirect Designation................................................................................................................................3 - 13
3.5 Subset Processing .................................................................................................................................3 - 15
3.6 Cautions on Programming (Operation Errors).......................................................................................3 - 16
3.7 Conditions for Execution of Instructions ................................................................................................3 - 19
3.8 Counting Step Number........................................................................................................................... 3 - 20
3.9 Operation when OUT, SET/RST, or PLS/PLF Instructions Use the Same Device..............................3 - 21
4. HOW TO READ INSTRUCTIONS 4 - 1 to 4 - 3
5. SEQUENCE INSTRUCTIONS 5 - 1 to 5 - 55
5.1 Contact Instructions................................................................................................................................5 - 2
5.1.1 Operation start, series connection, parallel connection (LD, LDI, AND, ANI, OR, ORI)................5 - 2
5.1.2 Pulse operation start, pulse series connection, pulse parallel connection
(LDP, LDF, ANDP, ANDF, ORP, ORF)...........................................................................................5 - 5
5.2 Connection Instructions..........................................................................................................................5 - 7
5.2.1 Ladder block series connections and parallel connections (ANB, ORB)....................................... 5 - 7
5.2.2 Operation results push, read, pop (MPS, MRD, MPP)................................................................... 5 - 9
5.2.3 Operation results inversion (INV) ....................................................................................................5 - 13
5.2.4 Operation result pulse conversion (MEP, MEF) .............................................................................5 - 14
5.2.5 Pulse conversion of edge relay operation results (EGP, EGF) ......................................................5 - 16
5.3 Out Instructions ......................................................................................................................................5 - 18
5.3.1 Out instructions (excluding timers, counters, and annunciators) (OUT)........................................5 - 18
5.3.2 Timers (OUT T, OUTH T) ...............................................................................................................5 - 20
5.3.3 Counters (OUT C) ...........................................................................................................................5 - 24
5.3.4 Annunciator output (OUT F)............................................................................................................5 - 26
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5.3.5 Setting devices (except for annunciators) (SET)............................................................................5 - 28
5.3.6 Resetting devices (except for annunciators) (RST)........................................................................5 - 30
5.3.7 Setting and resetting the annunciators (SET F, RST F).................................................................5 - 32
5.3.8 Leading edge and trailing edge output (PLS, PLF).........................................................................5 - 34
5.3.9 Bit device output reverse (FF).........................................................................................................5 - 36
5.3.10 Pulse conversion of direct output (DELTA, DELTAP).................................................................. 5 - 38
5.4 Shift Instruction.......................................................................................................................................5 - 40
5.4.1 Bit device shift (SFT, SFTP)............................................................................................................5 - 40
5.5 Master Control Instructions ....................................................................................................................5 - 42
5.5.1 Setting and resetting the master control (MC, MCR)......................................................................5 - 42
5.6 Termination Instructions.........................................................................................................................5 - 46
5.6.1 End main routine program (FEND).................................................................................................5 - 46
5.6.2 End sequence program (END)........................................................................................................5 - 48
5.7 Other Instructions...................................................................................................................................5 - 50
5.7.1 Sequence program stop (STOP)....................................................................................................5 - 50
5.7.2 No operation (NOP, NOPLF, PAGE n)...........................................................................................5 - 52
6. BASIC INSTRUCTIONS 6 - 1 to 6 - 133
6.1 Comparison Operation Instruction.........................................................................................................6 - 2
6.1.1 BIN 16-bit data comparisons (=, < >, >, <=, <, >=) .........................................................................6 - 2
6.1.2 BIN 32-bit data comparisons (D=, D< >, D>, D<=,D<, D>=) ..........................................................6 - 4
6.1.3 Floating decimal point data comparisons (E=, E< >, E>, E<=, E<, E>=).......................................6 - 6
6.1.4 Character string data comparisons ($=, $< >, $>, $<=, $<, $>=)...................................................6 - 8
6.1.5 BIN block data comparisons (BKCMP, BKCMPP).........................................................................6 - 12
6.2 Arithmetic Operation Instructions...........................................................................................................6 - 16
6.2.1 BIN 16-bit addition and subtraction operations (+, +P, -, -P).......................................................... 6 - 16
6.2.2 BIN 32-bit addition and subtraction operations (D+, D+P, D-, D-P) ...............................................6 - 20
6.2.3 BIN 16-bit multiplication and division operations (
6.2.4 BIN 32-bit multiplication and division operations (D
, P, /, /P).......................................................6 - 24
, D P, D/, D/P) ...........................................6 - 26
6.2.5 BCD 4-digit addition and subtraction operations (B+, B+P, B-, B-P)..............................................6 - 28
6.2.6 BCD 8-digit addition and subtraction operations (DB+, DB+P, DB-, DB-P)...................................6 - 32
6.2.7 BCD 4-digit multiplication and division operations (B
6.2.8 BCD 8-digit multiplication and division operations (DB
, B P, B/, B/P).......................................... 6 - 36
, DB P, DB/, DB/P)...............................6 - 38
6.2.9 Addition and subtraction of floating decimal point data (E+, E+P, E-, E-P)....................................6 - 40
6.2.10 Multiplication and division of floating decimal point data (E
, E P, E/, E/P)..............................6 - 44
6.2.11 Block addition and subtraction (BK+, BK+P, BK-, BK-P)..............................................................6 - 46
6.2.12 Linking character strings ($+, $+P) ...............................................................................................6 - 49
6.2.13 Incrementing and decrementing 16-bit BIN data (INC, INCP, DEC, DECP)...............................6 - 53
6.2.14 Incrementing and decrementing 32-bit BIN data (DINC, DINCP, DDEC, DDECP).....................6 - 55
6.3 Data Conversion Instructions.................................................................................................................6 - 57
6.3.1 Conversion from BIN data to 4-digit and 8-digit BCD (BCD, BCDP, DBCD, DBCDP)..................6 - 57
6.3.2 Conversion from BCD 4-digit and 8-digit data to BIN data (BIN, BINP, DBIN, DBINP).................6 - 59
6.3.3 Conversion from BIN 16 and 32-bit data to floating decimal point (FLT, FLTP, DFLT, DFLTP)... 6 - 61
6.3.4 Conversion from floating decimal point data to BIN 16- and 32-bit data
(INT, INTP, DINT, DINTP) ..............................................................................................................6 - 63
6.3.5 Conversion from BIN 16-bit to BIN 32-bit data (DBL, DBLP) .........................................................6 - 65
6.3.6 Conversion from BIN 32-bit to BIN 16-bit data (WORD, WORDP)................................................6 - 66
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6.3.7 Conversion from BIN 16 and 32-bit data to Gray code (GRY, GRY P, DGRY , DGRYP)...............6 - 67
6.3.8 Conversion of Gray code to BIN 16 and 32-bit data (GBIN, GBINP, DGBIN, DGBINP) ...............6 - 69
6.3.9 Complement of 2 of BIN 16- and 32-bit data (sign reversal) (NEG, NEGP, DNEG, DNEGP)......6 - 71
6.3.10 Sign reversal for floating decimal point data (ENEG, ENEGP)....................................................6 - 73
6.3.11 Conversion from block BIN 16-bit data to BCD 4-digit data (BKBCD, BKBCDP)........................6 - 74
6.3.12 Conversion from block BCD 4-digit data to block BIN 16-bit data (BKBIN, BKBINP)..................6 - 76
6.4 Data Transfer Instructions......................................................................................................................6 - 78
6.4.1 16-bit and 32-bit data transfers (MOV, MOVP, DMOV, DMOVP).................................................. 6 - 78
6.4.2 Floating decimal point data transfers (EMOV, EMOVP) ................................................................6 - 80
6.4.3 Character string transfers ($MOV, $MOVP)...................................................................................6 - 82
6.4.4 16-bit and 32-bit negation transfers (CML, CMLP, DCML, DCMLP).............................................. 6 - 84
6.4.5 Block 16-bit data transfers (BMOV, BMOVP).................................................................................6 - 87
6.4.6 Identical 16-bit data block transfers (FMOV, FMOVP)...................................................................6 - 89
6.4.7 16-bit and 32-bit data exchanges (XCH, XCHP, DXCH, DXCHP).................................................6 - 91
6.4.8 Block 16-bit data exchanges (BXCH, BXCHP)...............................................................................6 - 93
6.4.9 Upper and lower byte exchanges (SWAP, SWAPP)......................................................................6 - 95
6.5 Program Branch Instruction ...................................................................................................................6 - 96
6.5.1 Pointer branch instructions (CJ, SCJ, JMP)....................................................................................6 - 96
6.5.2 Jump to END (GOEND) ..................................................................................................................6 - 99
6.6 Program Execution Control Instructions..............................................................................................6 - 100
6.6.1 Interrupt disable/enable instructions, interrupt program mask (DI, EI IMASK) ............................6 - 100
6.6.2 Recovery from interrupt programs (IRET)....................................................................................6 - 109
6.7 I/O Refresh Instructions .......................................................................................................................6 - 111
6.7.1 I/O Refresh (RFS, RFSP)..............................................................................................................6 - 111
6.8 Other Convenient Instructions..............................................................................................................6 - 113
6.8.1 Count 1-phase input up or down (UDCNT1).................................................................................6 - 113
6.8.2 Counter 2-phase input up or down (UDCNT2) .............................................................................6 - 115
6.8.3 Teaching timer (TTMR).................................................................................................................6 - 117
6.8.4 Special function timer (STMR)......................................................................................................6 - 119
6.8.5 Rotary table near path rotation control (ROTC)............................................................................6 - 122
6.8.6 Ramp signal (RAMP).....................................................................................................................6 - 124
6.8.7 Pulse density measurement (SPD)...............................................................................................6 - 126
6.8.8 Fixed cycle pulse output (PLSY)...................................................................................................6 - 128
6.8.9 Pulse width modulation (PWM).....................................................................................................6 - 130
6.8.10 Matrix input (MTR).......................................................................................................................6 - 132
7. APPLICATION INSTRUCTIONS 7 - 1 to 7 - 332
7.1 Logical Operation Instructions................................................................................................................7 - 2
7.1.1 Logical products with 16-bit and 32-bit data (WAND, WANDP, DAND, DANDP)........................7 - 3
7.1.2 Block logical products (BKAND, BKANDP) ....................................................................................7 - 8
7.1.3 Logical sums of 16-bit and 32-bit data (WOR, WORP, DOR, DORP)...........................................7 - 10
7.1.4 Block logical sum operations (BKOR, BKORP)..............................................................................7 - 14
7.1.5 16-bit and 32-bit exclusive OR operations (WXOR, WXORP, DXOR, DXORP)..........................7 - 16
7.1.6 Block exclusive OR operations (BKXOR, BKXORP)......................................................................7 - 20
7.1.7 16-bit and 32-bit data non-exclusive logical sum operations
(WXNR, WXNRP, DXNR, DXNRP)................................................................................................7 - 22
7.1.8 Block non-exclusive logical sum operations (BKXNR, BKXNRP)..................................................7 - 28
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7.2 Rotation Instruction.................................................................................................................................7 - 30
7.2.1 Right rotation of 16-bit data (ROR, RORP, RCR, RCRP)..............................................................7 - 30
7.2.2 Left rotation of 16-bit data (ROL, ROLP, RCL, RCLP) ...................................................................7 - 32
7.2.3 Right rotation of 32-bit data (DROR, DRORP, DRCR, DRCRP)....................................................7 - 34
7.2.4 Left rotation of 32-bit data (DROL, DROLP, DRCL, DRCLP) ........................................................7 - 36
7.3 Shift Instruction.......................................................................................................................................7 - 38
7.3.1 n-bit shift to right or left of 16-bit data (SFR, SFRP, SFL, SFLP)...................................................7 - 38
7.3.2 1-bit shift to right or left of n-bit data (BSFR, BSFRP, BSFL, BSFLP)........................................... 7 - 40
7.3.3 1-word shift to right or left of n-word data (DSFR, DSFRP, DSFL, DSFLP) ..................................7 - 42
7.4 Bit Processing Instructions.....................................................................................................................7 - 44
7.4.1 Bit set and reset for word devices (BSET, BSETP, BRST, BRSTP)..............................................7 - 44
7.4.2 Bit tests (TEST, TESTP, DTEST, DTESTP) ..................................................................................7 - 46
7.4.3 Batch reset of bit devices (BKRST, BKRSTP)................................................................................7 - 48
7.5 Data Processing Instructions .................................................................................................................7 - 50
7.5.1 16-bit and 32-bit data searches (SER, SERP, DSER, DSERP).....................................................7 - 50
7.5.2 16-bit and 32-bit data checks (SUM, SUMP, DSUM, DSUMP)......................................................7 - 54
7.5.3 Decoding from 8 to 256-bits (DECO, DECOP)...............................................................................7 - 56
7.5.4 Encoding from 256 to 8-bits (ENCO, ENCOP)...............................................................................7 - 58
7.5.5 7-segment decode (SEG, SEGP) ...................................................................................................7 - 60
7.5.6 4-bit groupings of 16-bit data (DIS, DISP).......................................................................................7 - 62
7.5.7 4-bit linking of 16-bit data (UNI, UNIP)............................................................................................7 - 64
7.5.8 Dissociation or linking of random data (NDIS, NDISP, NUNI, NUNIP)..........................................7 - 66
7.5.9 Data dissociation and linking in byte units (WTOB, WTOBP, BTOW, BTOWP)...........................7 - 71
7.5.10 Maximum value search for 16 and 32-bit data (MAX, MAXP, DMAX, DMAXP)..........................7 - 75
7.5.11 Minimum value search for 16 and 32-bits data (MIN, MINP, DMIN, DMINP)..............................7 - 77
7.5.12 BIN 16 and 32-bits data sort operations (SORT, SORTP, DSORT, DSORTP) ..........................7 - 80
7.5.13 Calculation of totals for 16-bit data (WSUM, WSUMP)................................................................ 7 - 83
7.5.14 Calculation of totals for 32-bit data (DWSUM, DWSUMP)...........................................................7 - 85
7.6 Structured Program Instructions............................................................................................................7 - 87
7.6.1 FOR to NEXT instruction loop (FOR, NEXT)..................................................................................7 - 87
7.6.2 Forced end of FOR to NEXT instruction loop (BREAK, BREAKP)................................................7 - 89
7.6.3 Sub-routine program calls (CALL, CALLP).....................................................................................7 - 91
7.6.4 Return from sub-routine programs (RET).......................................................................................7 - 94
7.6.5 Sub-routine program output OFF calls (FCALL, FCALLP).............................................................7 - 95
7.6.6 Sub-routine calls between program files (ECALL, ECALLP)..........................................................7 - 99
7.6.7 Sub-routine output OFF calls between program files (EFCALL, EFCALLP)...............................7 - 102
7.6.8 Refresh instruction (COM).............................................................................................................7 - 106
7.6.9 Index modification of entire ladder (IX, IXEND)............................................................................7 - 112
7.6.10 Designation of modification values in index modification of entire ladders (IXDEV, IXSET).....7 - 120
7.7 Data Table Operation Instructions .......................................................................................................7 - 125
7.7.1 Writing data to the data table (FIFW, FIFWP)..............................................................................7 - 125
7.7.2 Reading oldest data from tables (FIFR, FIFRP) ...........................................................................7 - 127
7.7.3 Reading newest data from data tables (FPOP, FPOPP).............................................................7 - 129
7.7.4 Deleting and inserting data from and in data tables (FDEL, FDELP, FINS, FINSP)..................7 - 131
7.8 Buffer Memory Access Instruction.......................................................................................................7 - 134
7.8.1 Reading 1-/2-word data from the intelligent function module/special function module
(FROM, FROMP, DFRO, DFROP)...............................................................................................7 - 134
A - 7 A - 7
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7.8.2 Writing 1-/2-word data to intelligent function module/special function module
(TO, TOP, DTO, DTOP)................................................................................................................7 - 137
7.9 Display Instructions ..............................................................................................................................7 - 140
7.9.1 Print ASCII code instruction (PR)..................................................................................................7 - 140
7.9.2 Print comment instruction (PRC)...................................................................................................7 - 143
7.9.3 ASCII code LED display instruction (LED)....................................................................................7 - 148
7.9.4 LED display instruction for comments (LEDC).............................................................................7 - 150
7.9.5 Error display and annunciator reset instruction (LEDR) ...............................................................7 - 152
7.10 Debugging and Failure Diagnosis Instructions..................................................................................7 - 155
7.10.1 Special format failure checks (CHKST, CHK) ............................................................................7 - 155
7.10.2 Changing check format of CHK instruction (CHKCIR, CHKEND) .............................................7 - 159
7.10.3 Setting and resetting status latch (SLT, SLTR)..........................................................................7 - 167
7.10.4 Setting and resetting sampling trace (STRA, STRAR)...............................................................7 - 169
7.10.5 Execution, setting, and resetting of program trace
(PTRAEXE, PTRAEXEP, PTRA, PTRAR) .................................................................................7 - 171
7.11 Character String Processing Instructions ..........................................................................................7 - 173
7.11.1 Conversion from BIN 16-bit or 32-bit to decimal ASCII
(BINDA, BINDAP, DBINDA, DBINDAP)......................................................................................7 - 173
7.11.2 Conversion from BIN 16-bit or 32-bit data to hexadecimal ASCII
(BINHA, BINHAP, DBINHA, DBINHAP)......................................................................................7 - 176
7.11.3 Conversion from BCD 4-digit and 8-digit to decimal ASCII data
(BCDDA, BCDDAP, DBCDDA, DBCDDAP)...............................................................................7 - 179
7.11.4 Conversion from decimal ASCII to BIN 16-bit and 32-bit data
(DABIN, DABINP, DDABIN, DDABINP)......................................................................................7 - 182
7.11.5 Conversion from hexadecimal ASCII to BIN 16-bit and 32-bit data
(HABIN, HABINP, DHABIN, DHABINP)......................................................................................7 - 185
7.11.6 Conversion from decimal ASCII to BCD 4-digit or 8-digit data
(DABCD, DABCDP, DDABCD, DDABCDP)...............................................................................7 - 187
7.11.7 Reading device comment data (COMRD, COMRDP)................................................................7 - 190
7.11.8 Character string length detection (LEN, LENP)..........................................................................7 - 194
7.11.9 Conversion from BIN 16-bit or 32-bit to character string (STR, STRP, DSTR, DSTRP)...........7 - 196
7.11.10 Conversion from character string to BIN 16-bit or 32-bit data
(VAL, VALPP, DVAL, DVALP) ..................................................................................................7 - 202
7.11.11 Conversion from floating decimal point to character string data (ESTR, ESTRP)...................7 - 207
7.11.12 Conversion from character string to floating decimal point data (EVAL, EVALP)....................7 - 214
7.11.13 Conversion from hexadecimal BIN to ASCII (ASC, ASCP)......................................................7 - 218
7.11.14 Conversion from ASCII to hexadecimal BIN (HEX, HEXP) .....................................................7 - 220
7.11.15 Extracting character string data from the right or left (RIGHT, RIGHTP, LEFT, LEFTP)........7 - 222
7.11.16 Random selection from and replacement in character strings
(MIDR, MIDRP, MIDW, MIDWP)..............................................................................................7 - 225
7.11.17 Character string search (INSTR, INSTRP)...............................................................................7 - 229
7.11.18 Floating decimal point to BCD (EMOD, EMODP).....................................................................7 - 231
7.11.19 From BCD format data to floating decimal point (EREXP, EREXPP)......................................7 - 233
7.12 Special Function Instructions .............................................................................................................7 - 235
7.12.1 SIN operation on floating decimal point data (SIN, SINP)..........................................................7 - 235
7.12.2 COS operation on floating decimal point data (COS, COSP)....................................................7 - 237
7.12.3 TAN operation on floating decimal point data (TAN, TANP)......................................................7 - 239
7.12.4 SIN
-1
operation on floating decimal point data (ASIN, ASINP)..................................................7 – 241
A - 8 A - 8
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7.12.5 COS
7.12.6 TAN
-1
operation on floating decimal point data (ACOS, ACOSP).............................................7 - 243
-1
operation on floating decimal point data (ATAN, ATANP)...............................................7 - 245
7.12.7 Conversion from floating decimal point angle to radian (RAD, RADP)......................................7 - 247
7.12.8 Conversion from floating decimal point radian to angle (DEG, DEGP)......................................7 - 249
7.12.9 Square root operations for floating decimal point data (SQR, SQRP).......................................7 - 251
7.12.10 Exponent operations on floating decimal point data (EXP, EXPP)..........................................7 - 253
7.12.11 Natural logarithm operations on floating decimal point data (LOG, LOGP).............................7 - 255
7.12.12 Random number generation and series updates (RND, RNDP, SRND, SRNDP)..................7 - 257
7.12.13 BCD 4-digit and 8-digit square roots (BSQR, BSQRP, BDSQR, BDSQRP)...........................7 - 259
7.12.14 BCD type SIN operation (BSIN, BSINP)...................................................................................7 - 262
7.12.15 BCD type COS operations (BCOS, BCOSP)............................................................................7 - 264
7.12.16 BCD type TAN operation (BTAN, BTANP)...............................................................................7 - 266
7.12.17 BCD type SIN
7.12.18 BCD type COS
7.12.19 BCD type TAN
-1
operations (BASIN, BASINP)..........................................................................7 - 268
-1
operation (BACOS, BACOSP)......................................................................7 - 270
-1
operations (BATAN, BATANP)......................................................................7 - 272
7.13 Data Control Instructions....................................................................................................................7 - 274
7.13.1 Upper and lower limit controls for BIN 16-bit and BIN 32-bit data
(LIMIT, LIMITP, DLIMIT, DLIMITP).............................................................................................7 - 274
7.13.2 BIN 16-bit and 32-bit dead band controls (BAND, BANDP, DBAND, DBANDP).......................7 - 277
7.13.3 Zone control for BIN 16-bit and BIN 32-bit data (ZONE, ZONEP, DZONE, DZONEP).............7 - 280
7.14 File Register Switching Instructions...................................................................................................7 - 283
7.14.1 Switching file register numbers (RSET, RSETP)........................................................................7 - 283
7.14.2 Setting files for file register use (QDRSET, QDRSETP) ............................................................7 - 285
7.14.3 File setting for comments (QCDSET, QCDSETP).....................................................................7 - 287
7.15 Clock Instructions...............................................................................................................................7 - 289
7.15.1 Reading clock data (DATERD, DATERDP)................................................................................7 - 289
7.15.2 Writing clock data (DATEWR, DATEWRP)................................................................................7 - 293
7.15.3 Clock data addition operation (DATE+, DATE+P)......................................................................7 - 297
7.15.4 Clock data subtraction operation (DATE-, DATE-P) ..................................................................7 - 299
7.15.5 Changing time data formats (SECOND, SECONDP, HOUR, HOURP)....................................7 - 301
7.16 Peripheral Device Instructions ...........................................................................................................7 - 303
7.16.1 Message displays to peripheral devices (MSG) .........................................................................7 - 303
7.16.2 Keyboard input from peripheral devices (PKEY) ........................................................................7 - 305
7.17 Program Control Instructions .............................................................................................................7 - 307
7.17.1 Program standby instruction (PSTOP, PSTOPP).......................................................................7 - 308
7.17.2 Program output OFF standby instruction (POFF, POFFP) ........................................................7 - 309
7.17.3 Program scan execution registration instruction (PSCAN, PSCANP) .......................................7 - 311
7.17.4 Program low speed execution registration instruction (PLOW, PLOWP)..................................7 - 313
7.18 Other Instructions...............................................................................................................................7 - 315
7.18.1 Resetting watchdog timer (WDT, WDTP) ..................................................................................7 - 315
7.18.2 Timing pulse generation (DUTY).................................................................................................7 - 317
7.18.3 Direct 1-byte read from file register (ZRRDB, ZRRDBP) ...........................................................7 - 319
7.18.4 File register direct 1-byte write (ZRWRB, ZRWRBP).................................................................7 - 321
7.18.5 Indirect address read operations (ADRSET, ADRSETP)...........................................................7 - 323
7.18.6 Numerical key input from key board (KEY)..................................................................................7 - 324
7.18.7 Batch save or recovery of index register (ZPUSH, ZPUSHP, ZPOP, ZPOPP).........................7 - 328
7.18.8 Batch write operation to E
2
PROM file register (EROMWR, EROMWRP).................................7 - 332
A - 9 A - 9
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8. INSTRUCTIONS FOR DATA LINK 8 - 1 to 8 - 103
8.1 Network Refresh Instruction...................................................................................................................8 - 6
8.1.1 Network refresh (ZCOM).................................................................................................................8 - 6
8.2 Instructions Dedicated to QnA Links......................................................................................................8 - 12
8.2.1 Reading word device data from another station (READ)................................................................8 - 12
8.2.2 Reading word device data from another station (SREAD).............................................................8 - 18
8.2.3 Device data write to station on MELSECNET/10 network (WRITE)..............................................8 - 24
8.2.4 Writing device data to other stations (SWRITE).............................................................................8 - 31
8.2.5 Sending data to other stations (SEND)...........................................................................................8 - 38
8.2.6 Receiving data from another station (RECV)..................................................................................8 - 46
8.2.7 Transient requests from other stations (read/write clock data, remote RUN/STOP) (REQ).........8 - 52
8.2.8 Reading data from special function modules at remote I/O stations (ZNFR) ................................8 - 64
8.2.9 Writing data to special function module of remote I/O station (ZNTO)..........................................8 - 69
8.3 Instructions for A-Series Compatible Link..............................................................................................8 - 74
8.3.1 Reading device data from other stations (MELSECNET/10) (ZNRD) ...........................................8 - 74
8.3.2 Reading device data from local stations (MELSECNET) (ZNRD) .................................................8 - 78
8.3.3 Writing device data to other stations (MELSECNET/10) (ZNWR).................................................8 - 81
8.3.4 Writing data to devices at local stations (MELSECNET) (ZNWR).................................................8 - 85
8.3.5 Reading data from a remote I/O station special function module (MELSECNET) (RFRP)...........8 - 88
8.3.6 Writing data to special function modules of remote I/O stations (MELSECNET) (RTOP) ............8 - 92
8.4 Routing Information Read/Write ............................................................................................................8 - 96
8.4.1 Reading routing information (RTREAD)..........................................................................................8 - 96
8.4.2 Registering routing information (RTWRITE).................................................................................8 - 100
9. QCPU INSTRUCTIONS 9 - 1 to 9 - 42
9.1 Reading Module Information (UNIRD (P)).............................................................................................9 - 2
9.2 Trace Set/reset (TRACE, TRACER)......................................................................................................9 - 6
9.3 Writing Data to Designated File (FWRITE) ...........................................................................................9 - 8
9.4 Reading Data from Designated File (FREAD).......................................................................................9 - 16
9.5 Loading Program from Memory Card (PLOADP)..................................................................................9 - 27
9.6 Unloading program from program memory (PUNLOADP) ...................................................................9 - 29
9.7 Load + Unload (PSWAPP).....................................................................................................................9 - 31
9.8 High speed Block Transfer of File Register (RBMOV (P))....................................................................9 - 33
9.9 Write to Host Station CPU Shared Memory (S. TO (P)).......................................................................9 - 36
9.10 Read from Shared Memory of Another Station (FROM (P))...............................................................9 - 38
9.11 Refresh Instruction (COM)...................................................................................................................9 - 40
10. REDUNDANT SYSTEM INSTRUCTION (FOR Q4ARCPU) 10 - 1 to 10 - 14
10.1 Operation Mode Setting Instructions During CPU Start Up (S.STMODE)........................................10 - 2
10.2 CPU Switch Time Operation Mode Setting Instructions (S.CGMODE)............................................10 - 4
10.3 Data tracking instruction (S.TRUCK).................................................................................................10 - 6
10.4 Buffer memory batch refresh instruction (S.SPREF) ........................................................................10 - 10
A - 10 A - 10
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11. ERROR CODES 11- 1 to 11 - 46
11.1 How to Read Error Codes..................................................................................................................11 - 1
11.2 Error Code List ...................................................................................................................................11 - 2
11.2.1 Error Code List of Basic model QCPU........................................................................................11 - 2
11.2.2 Error Code List of High Performance model QCPU/QnACPU...................................................11 - 10
11.2.3 Error Code List of Process CPU .................................................................................................11 - 28
11.3 Resetting an error...............................................................................................................................11 - 46
APPENDICES APP - 1 to APP - 118
APPENDIX1 OPERATION PROCESSING TIME..................................................................................APP - 1
1.1 Definition........................................................................................................................................APP - 1
1.2 Operation Processing Times of Basic model QCPU....................................................................APP - 2
1.3 Operation Processing Times of High Performance model (QCPU/Process CPU/QnACPU).....APP - 14
APPENDIX 2 COMPARISON OF PERFORMANCE BETWEEN CPUs..............................................APP – 40
2.1 Comparison of Q/QnACPU with AnNCPU, AnACPU, and AnUCPU...........................................APP - 40
2.1.1 Usable devices........................................................................................................................APP - 40
2.1.2 I/O Control Mode.....................................................................................................................APP - 41
2.1.3 Data That Can Be Used by Instructions.................................................................................APP - 41
2.1.4 Timer Comparison..................................................................................................................APP - 42
2.1.5 Comparison of Counters.........................................................................................................APP - 43
2.1.6 Comparison of Display Instructions........................................................................................APP - 43
2.1.7 Instructions Whose Designation Format Has Changed
(Except Dedicated Instructions for AnACPU and AnUCPU).................................................APP - 44
2.1.8 AnACPU and AnUCPU Dedicated Instructions .....................................................................APP - 45
2.1.9 Instructions Which Can Be Programmed Only in the General Purpose Mode .....................APP - 45
APPENDIX 3 SPECIAL RELAY LIST.....................................................................................................APP - 46
3.1 Special Relay List of Basic model QCPU......................................................................................APP - 46
3.2 Special Relay List of High Performance model QCPU/QnACPU................................................APP – 50
3.3 Special Relay List of Process CPU...............................................................................................APP - 71
APPENDIX 4 SPECIAL REGISTER LIST ..............................................................................................APP - 87
4.1 Special Register List of Basic Model QCPU .................................................................................APP - 87
4.2 Special Register List of High Performance model QCPU/QnACPU...........................................APP – 98
4.3 Special Register List of Process CPU.........................................................................................APP - 134
APPENDIX 5 APPLICATION PROGRAM EXAMPLES.......................................................................APP - 162
5.1 Concepts of Programs Which Perform Operations of X
n
n
X
,
....................................................APP - 162
A - 11 A - 11
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Manuals
Related Manuals
The following table lists the manuals related to the Q/QnACPU.
Please order the one you need.
Manual Name
Basic model QCPU (Q mode) User's Manual (Hardw are design, Maintenance and Inspection)
Describes the specifications of the CPU module, power supply module, base unit, and extension cables.
(Sold separately)
Basic model QCPU (Q mode) User's Manual (Functions Ex planation, Programming
Fundamentals)
Describes the functions, programming method, and devices to create programs with Basic model QCPU
(Q mode). (Sold separately)
High Performance model QCPU (Q mode) User's Manual (Hardw are design, Maintenance and
Inspection)
Describes the specifications of the CPU module, power supply module, base unit, extension cables, and
memory c ard. (Sold separately)
High Performance model QCPU (Q mode) User's Manual (Functions Ex planation, Programming
Fundamentals)
Describes the functions, programming method, and devices to create programs with High Performance model
QCPU (Q mode). (Sold separately)
Process CPU User’s Manual (Hardware Design, Maintenance and Inspection)
Describes the specifications of the CPU module, power supply module, base unit, extension cables, and
memory c ard. (Sold separately)
Process CPU User’s Manual (Functions Explanation, Programming Fundamentals)
Describes the functions, programming method and devices that are required to create programs.
(Sold separately)
Manual Number
(Model Code)
SH-080187
(13JR43)
SH-080188
(13JR44)
SH-080037
(13JL97)
SH-080038
(13JL98)
SH-080314E
(13JR55)
SH-080315E
(13JR56)
QCPU (Q mode)/QnACPU Programming Manual (SFC)
Describes the system configuration, performance specifications, functions, programming, debugging, and error
codes for MELSAP3. (Sold separately)
QCPU (Q mode) Programming Manual (MELSAP-L)
Describes the system configuration, performance specifications, functions, programming, debugging, and error
codes for MELSAP-L. (Sold separately)
QCPU (Q mode)/QnACPU Programming Manual (PID Control Instructions)
Describes the dedicated instructions for PID control. (Sold separately)
QnPHCPU Programming Manual (Process Control Instructions)
Describes the dedicated instructions for performing process control. (Sold separately)
QnACPU Guidebook
Aimed at people using QnACPU for the first time. Describes procedures for everything from creating programs
and writing created programs to the CPU module, to debugging.
Also describes how to use the QnACPU most effectively.
Q2A(S1)/Q3A/Q4ACPU User's Manual
Describes the performance, functions, and handling of the Q2ACPU(S1), Q3ACPU, and Q4ACPU, and the
specifications and handling of memory cards and base units. (Sold separately)
Model Q2AS(H)CPU(S1) User's Manual
Describes performance, functions, and handling of the Q2ASCPU, Q2ASCPU-S1, Q2ASHCPU, and
Q2ASHCPU-S1, power supply module, memory card, specifications, and handling of the base unit.
(Sold separately)
SH-080041
(13JF60)
SH-080076
(13JF61)
SH-080040
(13JF59)
SH-080316E
(13JR67)
IB-66606
(13JF10)
IB-66608
(13J821)
SH-3599
(13J858)
A - 12 A - 12
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Manual Name
Q4ARCPU User's Manual
Describes the Q4ARCPU features, functions, and usage. Also describes the specification and usage of the
bus switching module, system management module, power supply module, memory card, and base unit.
(Sold separately)
Manual Number
(Model Code)
IB-66685
(13J852)
QnACPU Programming Manual (Fundamentals)
Describes how to create programs, the names of devices, parameters, and types of program.
(Sold separately)
QnACPU Programming Manual (Special Function Module)
Describes the dedicated instructions for special function modules available when using the Q2ACPU(S1),
Q3ACPU, and Q4ACPU. (Sold separately)
QnACPU Programming Manual (AD57 Instructions)
Describes the dedicated instructions for controlling an AD57(S1) type CRT controller module available
when using the Q2ACPU(S1), Q3ACPU, or Q4ACPU. (Sold separately)
QnACPU Programming Manual (PID Control Instructions)
Describes the dedicated instructions for PID control available when using the Q2ACPU(S1), Q3ACPU, or
Q4ACPU. (Sold separately)
QnACPU Programming Manual (SFC)
Describes the system configuration, performance specifications, functions, programming, debugging, and
error codes for MELSAP3. (Sold separately)
For QnA/Q4AR MELSECNET/10 N etw ork Sy stem R eference M anual
Describes the general concept, specifications, and part names and settings for MELSECNET/10.
(Sold separately)
type MELSECNET, MELSECNET/B Data Link System Reference Manual
Describes the general concept, specifications, and part names and settings for MELSECNET (II) and
MELSECNET/B. (Sold separately)
GX Developer Version 7 Operating Manual
Describes the online functions of GX Developer Version 7 including the programming procedure, printing
out procedure, monitoring procedure, and debugging procedure. (Sold separately)
IB-66614
(13JF46)
SH-4013
(13JF56)
IB-66617
(13JF49)
IB-66618
(13JF50)
IB-66619
(13JF51)
IB-66690
(13JF78)
IB-66350
(13JF70)
SH-080166
(13JU14)
Type SW2IVD-GPPQ software package OPERATING MANUA L (Offline)
Describes how to create programs and print out data when using SW2IVD-GPPQ, and the offline functions
of SW2IVD-GPPQ such as file maintenance. (Included with product)
Type SW2IVD-GPPQ software package OPERATING MNUA L (Online)
Describes the online functions of SW2IVD-GPPQ, including the methods for monitoring and debugging.
(Included with product)
Type SW2IVD-GPPQ software package OPERATING MANUAL (SFC )
Describes SFC functions such as SFC program editing and monitoring. (Included with product)
IB-66774
(13J921)
IB-66775
(13J922)
IB-66776
(13J923)
A - 13 A - 13
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MEMO
A - 14 A - 14
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1 GENERAL DESCRIPTION
g
1. GENERAL DESCRIPTION
MELSEC-Q/QnA
This manual describes the common instructions for QCPU, QnACPU, and Q2AS(H)CPU(S1) that
are required when programming with a QCPU, QnACPU, and Q2AS(H)CPU(S1).
Common instructions are all instructions except those used for special function modules such as
AJ71QC24, AJ71PT32-S3, etc.; the instructions for AD57; the instructions for PID control, and
those for MELSAP3.
1.1 Related Programming Manuals
Before reading this manual, check the programs, I/O processes, and devices that can be used
with your CPU module in the CPU Module User's Manual or in the QnACPU Programming
Manual.
(1) Q02(H ) CP U, Q0 6 HC PU , Q1 2H CPU, Q25HCPU
High Performance
model
QCPU (Q mode)
User's Manual
(Functions Explanation,
Programm ing
fundamentals)
1
Describes the functions,
executable programs,
I/O processing, and
device names of High
Performance model QCPU.
This manual
QCPU (Q mode)/
QnACPU
Programming
Manual
(Common
Instructions)
Describes the instructions
other than described in the
manuals on the ri
ht.
QCPU (Q mode)/
QnACPU
Programming
Manual
(PID
Control Instructions)
Describes the instructions
to perform PID control.
QCPU (Q mode)/
QnACPU
Programming
Manual (SFC)
Describes SFC.
QCPU (Q mode)
Programming
Manual
(MELSAP-L)
Describes MELSAP-L.
1 - 1 1 - 1
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1 GENERAL DESCRIPTION
(2) Q00JCPU, Q00CPU, Q01CPU
MELSEC-Q/QnA
1
(3) Q12PHCPU, Q25PHCPU
Basic model
QCP U (Q mode )
User's Manual
(Functions
Explanation,
Programming
fundam e ntals )
This manual
QCPU (Q mode)/
QnACPU
Programming
Manual
(Common
Instructions)
Process CPU
User’s Manual
(Function
Explanation,
Programming
Fundamentals)
Describes the functions,
executable programs,
I/O processing, and
device names of
Basic model QCPU.
Describes the functions,
executable programs,
I/O processing, and
device name of
Process CPU.
This manual
QCPU (Q mode)/
QnACPU
Programming
Manual
(Common
Instructions)
Describes the instructions
other than described in the
manuals on the right.
QnPHCPU
Programming
Manual
(Process Control
Instructions)
Describes the instructions
to perform process control.
QCPU (Q mode)/
QnACPU
Programming
Manual
(SFC)
Describes SFC.
QCPU (Q mode)
Programming
Manual
(MELSAP-L)
Describes MELSAP-L.
1 - 2 1 - 2
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1 GENERAL DESCRIPTION
(4) Q2ACPU, Q3ACPU, Q4ACPU, Q4ARCPU, Q2AS(H)CPU
MELSEC-Q/QnA
This manual
QCPU (Q mode)/
QnACPU
Programming
Manual
(Common
Instructions)
Describes the instructions
other than described in the
manuals on the right.
QnACPU
Programming
Manual
(Special
Function Modules)
Describes the instructions
for special function modules
such as AJ71QC24 and
AJ71PT32-S3.
QnACPU
Programming
Manual
(Fundamentals)
QnACPU
Programming
Manual
(AD57 Command)
Describes AD57
command to control
AD57/AD58.
Describes the executable programs, I/O processing,
and device names of QnACPU.
QCPU (Q mode)/
QnACPU
Programming
Manual
(PID
Control Instructions)
Describes the instructions
to perform PID control.
QCPU (Q mode)/
QnACPU
Programming
Manual (SFC)
Describes SFC.
Q4ARCPU
Programming
Manual
(Application
PID Instructions)
Describes the instructions
for application PID control.
1 - 3 1 - 3
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1 GENERAL DESCRIPTION
1.2 Abbreviation and Generic Name
The module names are abbreviated as follows
Module Type Name Abbreviation Abbreviation in Tables Generic Name
Q00JCPU PLC CPU
Q00CPU PLC CPU
Q01CPU PLC CPU
Q02CPU PLC CPU
Q02HCPU PLC CPU
Q06HCPU PLC CPU
Q12HCPU PLC CPU
Q25HCPU PLC CPU
Q12PHCPU PLC CPU
Q25PHCPU PLC CPU
Q00JCPU PLC CPU
Q00CPU PLC CPU
Q01CPU PLC CPU
Q02CPU PLC CPU
Q02HCPU PLC CPU
Q06HCPU PLC CPU
Q12HCPU PLC CPU
Q25HCPU PLC CPU
Q12PHCPU PLC CPU
Q25PHCPU PLC CPU
Q2ACPU(S1) PLC CPU
Q3ACPU PLC CPU
Q4ACPU PLC CPU
Q2ASCPU(S1) PLC CPU
Q2ASHCPU(S1) PLC CPU
Q4ARCPU PLC CPU
MELSECNET/H Network system
(MELSECNET/H mode)
MELSECNET/H Network system
(MELSECNET/10 mode)
MELSECNET/10 Network system
Ethernet interface module
Control and Communication Link System
Master/Local Module
Basic model QCPU Basic model QCPU
High Performance
model QCPU
Process CPU Process CPU
MELSECNET/H
MELSECNET/10
Ethernet interface
CC-Link module CC-Link module ——
QCPU ——
High Performance
model QCPU
QnACPU QnA
Q2ASCPU Q2AS
Q4ARCPU Q4AR
MELSECNET/10(H) ——
Ethernet interface
module
module
MELSEC-Q/QnA
CPU
——
1 - 4 1 - 4
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2 INSTRUCTION TABLES
2. INSTRUCTION TABLES
2.1 Types of Instructions
The major types of CPU module instructions consist of sequence instructions, basic instructions,
application instructions, data link instructions, QCPU instructions and redundant system
instructions. These types of instructions are listed in Table 2.1 below.
Table 2.1 Types of Instructions
Types of Instructions Meaning
Sequence
instructions
Basic
instructions
Application
instructions
Data link
instructions
QCPU
instructions
Redundant system
instructions
Contact instr uc t ion Operation star t, ser i es con ne cti on , pa ra ll el conn ec t ion
Connection instructions
Output instruction Bit device output, pulse output, output reversal
Shift instruction Bit device shift
Master cont ro l in st ru ct i on Master cont ro l
Termination instruction Program termination
Other instructions
Comparison operation instruction Comparisons such as =, >, <
Arithmetic operation instruction Addition, subtraction, multiplication or division of BIN or BCD
BCD BIN conversion instruction
Data transfer instruction Transmits designated data
Program branch in stru ct ion Program jumps
Program run control instruction Enable or prohibit interrupt programs
I/O refresh Run partial refresh
Other convenient instructions
Logical operation instructions Logical operations such as logical sum, logical product, etc.
Rotation instruction Rotation of designated data
Shift instruction Shift of designated data
Bit processing instructions Bit set and reset, bit test, batch reset of bit devices
Data processing instructions 16-bit data searches, data processing such as decoding and encoding
Structure creation instructions
Table operation instruction Read/Write of FIFO table
Buffer memory access instruction Data read/write for special function modules
Display instructions Print ASCII code, LED character display, etc.
Debugging and failure diagnosis
instructions
Character string processing
instructions
Special funct ion ins tru ct ion s
Data control instructions Upper and lower limit controls, dead band controls, zone controls
Switching instructions File register block No. switches, designation of file registers and comment files
Clock instructions
Peripheral device instructions I/O to peripheral devices
Program in st ru ct io n s Instruct ion s to sw i t ch prog ra m execu t io n co nd i ti on s
Other instructions
Link refresh instructions Designated network refresh
Instructi on s de di ca te d to Qn A lin ks
Instructions for A-series-compatible
link
Routing information read/write
instructions
Instruction for QCPU
Instruct i on s fo r Q4 A R CPU
Ladder block connection, creation of pulses from operation results, store/read
operation results
Program stop, instructions such as no operation which do not fit in the above
categories
Conversion from BC D to BI N and fr o m BI N to BC D
Instructions for: Counter increment/decrement, teaching timer, special function
timer, rotary table shortest direction control, etc.
Repeated opera tio n, sub rou tin e pr ogr a m call s, In dex mod if ic ati on in ladder
units
Check, status check, sampling trace, program trace
Conversion betw e en BIN / BCD and AS CI I ; con vers io n be twee n BI N and
character st r ing; con ver s ion be tw ee n f loat in g de ci mal po int da ta and c har ac te r
strings, character string processing, etc.
Trigonometric functions, conversion between angles and radians, exponential
operations, automatic logarithms, square roots
Read/write of year, month, day, hour, minute, second, and day of the week;
conversion between time statement (hour, minute, second) and seconds
Instructions that do not fit in the above categories, such as watchdog timer
reset instructions and timing clock instructions
Read/write of dat a fr o m othe r s ta tion s ; d ata tran s mis si on sign al s to ot he r
stations; processing reques ts to other stations
Read/write for designated station word device, read/write data from remote I/O
station special function module
Reads, writes, and registers routing information.
Reading module i nf or mat ion ; tr ac e se t/re s et ; re adin g/w r it in g bina ry dat a;
load/unload/ lo ad + unlo ad prog ra m fro m me mory ca rd ; hi gh - speed blo c k
transfer of file register
Operation mode se tt ing dur ing C PU st ar tup; oper at i on mode sett in g
instruction s dur ing CPU sw i tch ; da ta tra c ki ng ; bu ffer memory batch refresh
MELSEC-Q/QnA
2
Reference
Chapter
5
6
7
8
9
10
2 - 1 2 - 1
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2 INSTRUCTION TABLES
g
2.2 How to Read Instruction Tables
The instruction tables found from Section 2.3 to 2.6 have been made according to the following
format:
Table 2.2 How to Read Instruction Tables
MELSEC-Q/QnA
2
Category
BIN 16-bit
addition
and
subtraction
operations
1
Symbol
Symbols
Instruction
+
+P
+
+P
2 3 4 5 6
+ SD
+P
+ S1 S2 D
+P
SD
S1 S2
(D)+(S) (D)
(S1)+(S2) (D)
D
Processing Details
Execution
Condition
Description
1
...........Classifies instructions according to their application
2
...........Indicates the instruction symbol added to the instruction in a program
Instruction code is built around the 16-bit instruction. The following notations are used to
mark 32-bit instructions, instructions executed only at the leading edge of OFF to ON,
real number instructions, and character string instructions:
•
32-bit instruction......................... The letter "D" is added to the first line of the instruction
Example
+
D+
Subset
See for
Number of
Basic Steps
3
4
7
Description
6-16
6-18
8
16-bit instruction 32-bit instruction
•
Instruction s e xecut ed only at the leading edge of OFF t o ON
................................. The letter "P" is added to the end of the instruction
Example
Instructions
executed when ON
•
Real number instructions ........... The letter "E" is added to the first line of the instruction
Example
•
Character string instructions ...... A dollar sign “$” is added to the first line of the
+
+
Real number instructions
+P
Instructio ns e xec u t ed on ly at the
leadin
edge of OFF to ON
E+
instruction
Example
+
Character string instructions
$+
2 - 2 2 - 2
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2 INSTRUCTION TABLES
3
...........Shows sy mbol diagram on the ladder
MELSEC-Q/QnA
+
SD
Indicates destination
Indicates source
Indicates instruction symbol
+ DS1 S2
Indicates destination
Indicates source
Indicates instruction symbol
Fig. 2.1 Shows Symbol Diagram on the La dd e r
Destination ....................Indicates where data will be sent after operation
Source...........................Stores data prior to operation
4
...........Indicates the type of processing that is performed by individual instructions
(D)+(S) (D)
Indicates 16 bits
(D+1, D)+(S+1, S)
16 bits 16 bits
D+1 D
The upper 16 bits The lower 16 bits
(D+1, D)
Indicates 32 bits
Fig. 2.2 Type o f Pro cessi ng Pe r for med by Individual Instru ctio n s
5
...........The details of conditions for the execution of individual instructions are as follows:
Symbol Execution Condition
Instruction executed under normal circumstances, w ith no regard to the O N/O FF
No symbol recorded
status of conditions prior to the instruction.
If the preconditions is OFF, the instruction will conduct O FF proces sing.
Executed during ON; instruction is executed only while the precondition i s O N.
If the preconditions is OFF, the instruction is not executed, and no proc essi ng is
conducted.
Executed once at ON; instruction executed only at leading ed ge w hen precondition
goes from OFF to ON. Following execution, instruction will not be executed and no
processing conducted even if condition remains ON .
Executed during OFF; instruction is executed only while the preconditio n is O FF.
If the precondition is ON, the instruction is not ex ecuted, and no proces sing is
conducted.
Executed once at OFF; instruction executed only at trailing edge when precondition
goes from ON to OFF. Following execution, instruction will not be executed and no
processing conducted even if condition remains OFF.
6
...........Indicates the basic number of steps for individual instructions.
See Section 3.8 for a description of the number of steps.
7
...........The “ ” mark indicates instructions for which subset processing is possible.
See Section 3.5 for details on subset processing.
8
...........Indicates the page numbers where the individual instructions are explained.
2 - 3 2 - 3
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2 INSTRUCTION TABLES
2.3 Sequence Instructions
2.3.1 Contact Instruction
MELSEC-Q/QnA
Table 2.3 Contact Instructions
Category
Contact
Symbol Processing Details
Symbols
Instruction
LD
LDI
AND
ANI
OR
ORI
LDP • Starts leading edge pulse operation
LDF • Starts trailing edge pulse operation
ANDP • Leading edge pulse series connection
ANDF • Trailing edge pulse series connection
ORP • Leading edge pulse parallel connection
ORF
• Starts logic operation
(Starts a contact logic operation)
• Starts logical NOT operation
(Starts b contact logic operation)
• Logical product
(a contact series connection)
• Logical product NOT
(b contact series connection)
• Logical sum
(a contact parallel connection)
• Logical sum NOT
(b contact parallel connection)
• Trailing edge pulse parallel connection
Execution
Condition
Number of
Basic Steps
1
2
Subset
See for
Description
5-2
3
5-5
3
REMARKS
1) 1 : The number of steps may vary depe ndi ng on the d evi ce bei ng used .
Device Number of Steps
Internal device, file register (R0 to R32767) 1
Direct access input (DX) 2
Devices other than above 3
2) 2 : The number of steps may vary depending on the device and type of CPU module being
used.
Device
Internal device, file register (R0 to R32767) 1 2
Direct access input (DX) 2 2
Devices other than above 3 3
3) 3: The subset is effective only with QCPU.
2 - 4 2 - 4
Number of Steps
QCPU QnACPU
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2 INSTRUCTION TABLES
2.3.2 Connection instructions
Table 2.4 Connection Instructions
MELSEC-Q/QnA
Category
Connection
Symbol Processing Details
Symbols
Instruction
ANB
ORB
MPS • Memory storage of operation results
MRD
MPP
INV • Inversion of operation result 1 5-13
MEP
MEF
EGP
EGF
MPS
MRD
MPP
ANB
ORB
Vn
Vn
• AND between logical blocks (Series
connection between logical blocks)
• OR between logical blocks
(Series connection between logical blocks)
• Read of operation results stored with MPS
instruction
• Read and reset of operation results stored
with MPS instruction
• Conversion of operation result to leading
edge pulse
• Conversion of op era tio n r e sult to tr a ilin g
edge pulse
• Conversion of operation result to leading
edge pulse
(Stored at Vn)
• Conversion of op era tio n r e sult to tr a ilin g
edge pulse
(Stored at Vn)
Execution
Condition
Subset
Number of
Basic Steps
15-7
15-9
15-14
1
See for
5-16
1
Description
REMARKS
1:The number of steps may vary depending on the type of CPU module being used.
Component Number of basic steps
High Performance model QCPU
Process CPU
QnACPU
Basic model QCPU 2
1
2 - 5 2 - 5
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2 INSTRUCTION TABLES
2.3.3 Output instructions
MELSEC-Q/QnA
Table 2.5 Output Instructions
Category
Output
Symbol Processing Details
Symbols
Instruction
OUT • Device output 15-18
SET
RST
PLS
PLF PLF D
FF
DELTA
DELTAP
SET D
RST D
PLS D
FF
DELTA D
DELTAP D
• Set device
• Reset device
• Generates 1 cycle program pulse at
leading edge of input signal
• Generates 1 cycle program pulse at trailing
edge of input signal
• Reversal of device output
D
• Pulse conversion of direct output
Execution
Condition
Subset
Number of
Basic Steps
2
1
2
1
25-34
25-36
25-38
See for
5-28
5-32
5-30
5-32
Description
REMARKS
1) 1: The number of steps may va ry depe nd in g on th e device in use.
See description pages of individual instructions for number of steps.
2)
2: The execution condition applies only when an annunciator (F) is in use.
2.3.4 Shift instructions
Table 2.6 Shift Instructions
Category
Shift
SFT
SFTP
Symbols
Instruction
Symbol Processing Details
SFT D
• 1-bit shift of device
SFTP D
2 - 6 2 - 6
Execution
Condition
Subset
Number of
Basic Steps
25-40
See for
Description
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2 INSTRUCTION TABLES
2.3.5 Master control instructions
Table 2.7 Master Control Instructions
MELSEC-Q/QnA
Category
Master
control
MC
MCR
Symbols
Instruction
Symbol Processing Details
MC n D
MCR n
2.3.6 Termination instruction
Category
Program
end
FEND
END
Symbols
Instruction
Symbol Processing Details
• Starts master control 2
• Resets master contr ol 1
Table 2.8 Termination Instructions
FEND
END
• Termination of main program 5-46
• Termination of sequence program
Execution
Condition
Execution
Condition
Number of
Basic Steps
Number of
Basic Steps
1
Subset
See for
Description
5-42
Subset
See for
Description
5-48
2.3.7 Other instructions
Category
Symbols
Instruction
Stop STOP
NOP • Ignored (For program deletion or space)
Ignored
NOPLF
PAGE
Table 2.9 Other Instructions
Symbol Processing Details
• Terminates sequence operation after input
condition has been met
STOP
NOPLF
PAGE n
• Sequence program is executed by placing
the RUN/STOP key switch back in the
RUN position
• Ignored (To change pages during
printouts)
• Ignored (Subsequent programs will be
controlled from step 0 of page n)
Execution
Condition
Subset
Number of
Basic Steps
15-50
15-52
See for
Description
2 - 7 2 - 7
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2 INSTRUCTION TABLES
2.4 Basic Instructions
2.4.1 Comparison operation instruction
Table 2.10 Comparison Operation Instruction
MELSEC-Q/QnA
Category
16-bit data
comparisons
LD=
AND=
OR=
LD<>
AND<>
OR<>
LD>
AND>
OR>
LD<=
AND<=
(S2)
(S2)
Execution
Condition
Number of
Basic Steps
3
3
3
3
Subset
See for
Description
6-2
6-2
6-2
6-2
Symbol Processing Details
Symbols
Instruction
=
=
=
< >
< >
< >
>
>
>
< =
< =
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1
S2
• Conductive status when (S1) = (S2)
• Non-conductive status when (S1)
• Conductive status when (S1)
• Non-conductive status when (S1) = (S2)
• Conductive status when (S1) > (S2)
• Non-conductive status when (S1)
• Conductive status when (S1)
• Non-conductive status when (S1) > (S2)
(S2)
(S2)
OR<=
LD<
AND<
OR<
LD>=
AND>=
OR>=
< =
<
<
<
> =
> =
> =
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
• Conductive status when (S1) < (S2)
• Non-conductive status when (S1)
• Conductive status when (S1)
• Non-conductive status when (S1) < (S2)
(S2)
(S2)
3
3
2 - 8 2 - 8
6-2
6-2
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2 INSTRUCTION TABLES
Table 2.10 Comparison Operation Instructions (Continued)
MELSEC-Q/QnA
Category
32-bit data
comparisons
Instruction
LDD=
ANDD=
ORD=
LDD<>
ANDD<>
ORD<>
LDD>
ANDD>
ORD>
LDD<=
ANDD<=
Symbols
=
DS1S2
=
DS1S2
=
DS1S2
< >
DS1S2
< >
DS1S2
< >
DS1S2
>
DS1S2
>
D
>
< =
DS1S2
< =
DS1S2
Symbol Processing Details
• Conductive status when
(S1+1, S1) = (S2+1, S2)
• Non-Conductive status when
S1 S2
S1 S2D
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1) = (S2+1,S2)
• Conductive status when
(S1+1, S1) > (S2+1, S2)
• Non-Conductive status when
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1) > (S2+1, S2)
(S2+1, S2)
(S2+1, S2)
(S2+1, S2)
(S2+1, S2)
Execution
Condition
Subset
Number of
Basic Steps
1 6-4
1 6-4
1 6-4
1 6-4
See for
Description
ORD<=
LDD<
ANDD<
ORD<
LDD>=
ANDD>=
ORD>=
< =
DS1S2
<
DS1S2
<
D
<
D
> =
D
> =
DS1S2
> =
D
S1 S2
S1 S2
S1 S2
S1 S2
• Conductive status when
(S1+1, S1) <(S2+ 1 , S2 )
• Non-Conductive status when
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1) < (S2+1, S2)
(S2+1, S2)
(S2+1, S2)
1 6-4
1 6-4
2 - 9 2 - 9
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2 INSTRUCTION TABLES
REMARK
1 : The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
MELSEC-Q/QnA
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1) 3
3
5
2 - 10 2 - 10
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2 INSTRUCTION TABLES
Table 2.10 Comparison Operation Instructions (Continued)
MELSEC-Q/QnA
Category
Real
number
data comparisons
Instruction
LDE=
ANDE=
ORE=
LDE<>
ANDE<>
ORE<>
LDE>
ANDE>
ORE>
LDE<=
ANDE<=
Symbols
=
ES1S2
=
ES1S2
=
ES1S2
< >
ES1S2
< >
ES1S2
< >
ES1S2
>
ES1S2
>
E
>
ES1S2
< =
E
< =
E
Symbol Processing Details
• Conductive status when
(S1+1, S1) = (S2+1, S2)
• Non-Conductive status when
(S2+1, S2)
(S2+1, S2)
(S2+1, S2)
=
(S2+1, S2)
(S2+1, S2)
S1 S2
S1 S2
S1 S2
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1)
• Conductive status when
(S1+1, S1) > (S2+1, S2)
• Non-Conductive status when
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1) > (S2+1, S2)
Execution
Condition
Subset
Number of
Basic Steps
36-6
36-6
36-6
36-6
See for
Description
ORE<=
LDE<
ANDE<
ORE<
LDE>=
ANDE>=
ORE>=
< =
E
<
E
<
ES1S2
<
ES1S2
> =
E
> =
E
> =
ES1S2
S1 S2
S1 S2
S1 S2
S1 S2
• Conductive status when
(S1+1, S1) < (S2+1, S2)
• Non-Conductive status when
(S1+1, S1)
• Conductive status when
(S1+1, S1)
• Non-Conductive status when
(S1+1, S1) < (S2+1, S2)
(S2+1, S2)
(S2+1, S2)
36-6
36-6
2 - 11 2 - 11
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2 INSTRUCTION TABLES
Table 2.10 Comparison Operation Instructions (Continued)
MELSEC-Q/QnA
Category
Character
string data
comparisons
Instruction
LD$=
AND$=
OR$=
LD$<>
AND$<>
OR$<>
LD$>
AND$>
OR$>
LD$<=
AND$<=
OR$<=
LD$<
AND$<
OR$<
LD$>=
AND$>=
OR$>=
Symbols
=
$
=
$
=
$
< >
$S1S2
< >
$
< >
$S1S2
>
$
>
$
>
$
< =
$S1S2
< =
$
< =
$S1S2
<
$
<
$
<
$
> =
$
> =
> =
$
Symbol Processing Details
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S1 S2
S2
S1
S1 S2
S1 S2$
S2
S1
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1) = (character string S2)
• Non-Conductive status when (character
string S1)
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1)
• Non-Conductive status when (character
string S1) = (character string S2)
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1) > (character string S2)
• Non-Conductive status when (character
string S1)
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1)
• Non-Conductive status when (character
string S1) > (character string S2)
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1) < (character string S2)
• Non-Conductive status when (character
string S1)
• Compares character string S1 and
character string S2 one character at a
time.
• Conductive status when (character string
S1)
• Non-Conductive status when (character
string S1) < (character string S2)
(character string S2)
(character string S2)
(character string S2)
(character string S2)
(character string S2)
(character string S2)
Execution
Condition
Subset
Number of
Basic Steps
36-8
36-8
36-8
36-8
36-8
36-8
See for
Description
REMARK
1) : The conditions under which character string comparisons can be made are as shown
below
•
Match: All characters in the strings must match
•
Larger string: If character strings are different, determines the string with the largest
number of character codes
If the lengths of the character strings are different, determines the
longest character string
•
Smaller string: If the character strings are different, determines the string with the
smallest number of character codes
If the lengths of the character strings are different, determines the
shortest character string
2 - 12 2 - 12
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2 INSTRUCTION TABLES
Table 2.10 Comparison Operation Instructions (Continued)
MELSEC-Q/QnA
Category
Block data
comparisons
Symbols
Instruction
BKCMP=
BKCMP<>
BKCMP>
BKCMP<=
BKCMP<
BKCMP>=
BKCMP=P
BKCMP< >P
BKCMP>P
BKCMP<=P
BKCMP<P
BKCMP>=P
Symbol Processing Details
< >
< =
> =
< >
< =
> =
=
>
<
=
>
<
P
P
S1 S2 D
S1
S1 S2 D
P
D
S2 D
S2 D
BKCMP nS1 S2 D
BKCMP
BKCMP nS1 S2
BKCMP nS1 S2 D
BKCMP nS1 S2 D
BKCMP n
BKCMP nS1 S2 DP
BKCMP nS1 S2 DP
BKCMP nS1
BKCMP nS1 S2 D
BKCMP
Execution
Condition
• Compares n points of data from S1
with n points of data from S2 in 1-w ord
n
nS1 S2 DBKCMP P
n
units, and stores the results of the
comparison at n points from the bit
device designated by (D).
Subset
Number of
Basic Steps
56-12
See for
Description
2 - 13 2 - 13
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2 INSTRUCTION TABLES
2.4.2 Arithmetic operation instructions
Table 2.11 Arithmetic Operation Instructions
MELSEC-Q/QnA
Category
BIN 16-bit
addition
and
subtraction
operations
BIN 32-bit
addition
and
subtraction
operations
BIN 16-bit
multiplication and
division
operations
BIN 32-bit
multiplication and
division
operations
+
+P
+
+P
-
-P
-
-P
D+
D+P
D+
D+P
D-
D-P
D-
D-P
P
/
/P
D
D P
D/
D/P
Symbol Processing Details
Symbols
Instruction
+ SD
+P
+ S1 S2 D
+P S1 S2 D
−
−
P
−
−
P S1 S2 D
D+ SD
D+P S
D+P S
D+
D+P
−
D
−
−
D S1 S2 D
−
/
/P S1 S2 D
D S1 S2 D
D/
D/P S1 S2 D
S2 D
S1
S2 D
S1
S2 D
S1
S2 DDP
S1
S1 S2 D
S1 S2 DP
S2 D
S1
S1 S2 DDP
S2 D
S1
• (D)+(S) (D)
SD
• (S1)+(S2) (D)
• (D) - (S)
SD
SD
• (S1) - (S2)
• (D+1, D)+(S+1 , S)
D
D
• (S1+1, S1)+(S2+1, S2) (D+1, D)
• (D+1, D)-(S+1, S)
DS
SDDP
• (S1+1, S1)-(S2+1, S2) (D+1, D)
• (S1) (S2) (D+1, D)
• (S1)/(S2) Quotient(D), Remainder
(D+1)
• (S1+1, S1) (S2+1, S2) (D+3, D+2,
D+1, D)
• (S1+1, S1)/(S2+1, S2)
D), Remainder (D+3, D+2)
(D)
(D)
(D+1, D)
(D+1, D)
Quotient (D+1,
Execution
Condition
Subset
Number of
Basic Steps
3 6-16
4 6-18
3 6-16
4 6-18
1 6-20
2 6-22
1 6-20
2 6-22
3 6-24
4 6-24
4 6-26
4 6-26
See for
Description
2 - 14 2 - 14
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2 INSTRUCTION TABLES
REMARKS
1) 1:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
2)
2:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
MELSEC-Q/QnA
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
3 Note 2)
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
4 Note 2)
Note 1)
5
Note 2)
3
Note 1)
6
Note 2)
4
3)
3:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
QCPU
QnCPU 4
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1) 4
3
2 - 15 2 - 15
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2 INSTRUCTION TABLES
Table 2.11 Arithmetic Operation Instructions (Continued)
MELSEC-Q/QnA
Category
BCD 4digit
addition
and
subtraction
operations
BCD 8digit
addition
and
subtraction
operations
BCD 4digit multiplication
and
division
operations
BCD 8digit multiplication
and
division
operations
B+
B+P
B+
B+P
B-
B-P
B-
B-P
DB+
DB+P
DB+
DB+P
DB-
DB-P
DB-
DB-P
B
B P
B/
B/P
DB
DB P
DB/
DB/P
Symbol Processing Details
Symbols
Instruction
B+ DS
B+P
B+ S1 S2 D
B+P
−
B DS
−
−
B S1 S2 D
−
DB+ SD
DB+P SD
DB+ S1 S2 D
DB+P
DB
DB SDP
−
DB
−
DB S1 S2 DP
B
B
P
B/
B/P S1 S2 D
DB S1 S2 D
DB S1 S2 DP
DB/ S1 S2 D
DB/P
S2 D
S1
S1 S2 DBP
S2 D
S1
−
−
S2 D
S1
S2 D
S1
S2 D
S1
S2 D
S1
S2 D
S1
• (D)+(S) (D)
SD
• (S1)+(S2) (D)
• (D)-(S) (D)
DSBP
• (S1)-(S2)
• (D+1, D)+(S+1 , S)
• (S1+1, S1)+(S2+1, S2) (D+1, D)
• (D+1, D)-(S+1, S) (D+1, D)
SD
• (S1+1, S1)-(S2+1, S2)
• (S1) (S2) (D+1, D)
• (S1)/(S2) Quotient(D), Remainder
(D+1)
• (S1+1, S1)
D+1, D)
• (S1+1, S1)/(S2+1, S2)
D), Remainder (D+3, D+2)
(D)
(S2+1, S2) (D+3, D+2,
(D+1, D)
(D+1, D)
Quotient (D+1,
Execution
Condition
Subset
Number of
Basic Steps
3 6-28
46-30
3 6-28
46-30
36-32
46-34
36-32
46-34
4 6-36
4 6-36
46-38
4 6-38
See for
Description
2 - 16 2 - 16
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2 INSTRUCTION TABLES
Table 2.11 Arithmetic Operation Instructions (Continued)
MELSEC-Q/QnA
Category
Floating
decimal
point data
addition
and subtraction
operations
Floating
decimal
point data
multiplication and
division
operations
BIN block
addition
and subtraction
operations
Character
string data
combinations
Symbol Processing Details
Symbols
Instruction
E+
E+P
E+
E+P
E-
E-P
E-
E-P
E
E P E S1 S2 DP
E/
E/P
BK+
BK+P
BK-
BK-P
$+
$+P
$+
$+P
E+
E+P S1 S2 D
−
E S1 S2 D
−
E S1 S2 D
E/ S1 S2 D
E/P S1 S2 D
BK+ S1 S2nD
BK+P S1 S2 nD
−
BK S1 S2 nD
−
BK S1 S2 nDP
$+
$+P
E+
E+P SD
−
E S
−
EP
$+ SD
$+P SD
SD
S2 D
S1
SD
S1 S2 DEP
S1 S2 D
S1 S2 D
D
• (D+1, D)+(S+1 , S) (D +1, D)
• (S1+1, S1)+(S2+1, S2)
• (D+1, D)-(S+1, S) (D+1, D)
• (S1+1, S1)-(S2+1, S2)
• (S1+1, S1)
• (S1+1, S1)/(S2+1, S2)
(D+1, D)
• Adds data of n points from (S1) and data
of n points from (S2) in batch.
• Subtracts data of n points from (S1) and
data of n points from (S2) in batch.
• Links character string designated with
(S) to character string designated with
(D), and stores the result from (D)
onward.
• Links character string designated with
(S2) to character string designated with
(S1), and stores the result from (D)
onward.
(S2+1, S2) (D+1, D)
(D+1, D)
(D+1, D)
Quotient
Execution
Condition
Subset
Number of
Basic Steps
36-40
46-42
36-40
46-42
36-44
46-44
56-46
56-46
36-49
46-51
See for
Description
2 - 17 2 - 17
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2 INSTRUCTION TABLES
Table 2.11 Arithmetic Operation Instructions (Continued)
MELSEC-Q/QnA
Category
BIN data
increment
Execution
Condition
Number of
2 6-53
1 6-55
2 6-53
1 6-55
Instruction
INC
INCP
DINC
DINCP
DEC
DECP
DDEC
DDECP
Symbol Processing Details
Symbols
INC D
INCP D
DINC D
DINCP D
DEC
DECP D
DDEC D
DDECP D
• (D)+1
• (D+1, D)+1
• (D)-1 (D)
D
• (D+1, D)-1
(D)
(D+1, D)
(D+1, D)
REMARKS
1) 1:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
2 Note 2)
Subset
See for
Basic Steps
Description
Note 1)
3
Note 2)
2
2 - 18 2 - 18
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2 INSTRUCTION TABLES
)
)
)
2.4.3 Data conversion instructions
Table 2.12 Data Conversion Instructions
MELSEC-Q/QnA
Category
BCD conversions
BIN conversions
Conversion
from BIN to
floating
decimal
point
Conversion
from floating decimal
point to
BIN
Conversion
between
BIN 16-bit
and 32-bit
Conversion
from BIN to
gray code
Instruction
BCD
BCDP
DBCD
DBCDP
BIN
BINP
DBIN
DBINP
FLT
FLTP
DFLT
DFLTP
INT
INTP
DINT
DINTP
DBL
DBLP
WORD
WORDP
GRY
GRYP
DGRY
DGRYP
Symbol Processing Details
Symbols
BCD SD
BCDP
DBCD SD
DBCDP SD
BIN S
BINP SD
DBIN SD
DBINP
FLT SD
FLTP
DFLT SD
DFLTP
INT SD
INTP SD
DINT SD
DINTP SD
DBL SD
DBLP SD
WORD SD
WORDP SD
GRY SD
GRYP SD
DGRY SD
DGRYP S
SD
D
D
S
D
S
D
S
D
BCD conversion
(S)
BIN (0 to 9999
BCD conversion
(S+1, S)
BIN conve rsion
(S)
BCD (0 to 9999
BIN conversion
(S+1, S)
Conversion to floating
decimal point
(S+1, S)
Conversion to floating
decimal point
(S+1, S)
Conversion to BIN
(S+1, S)
Conversion to BIN
(S+1, S )
Conversion
(S)
BIN (-32768 to 32767)
(S+1, S)
Conversion to gray code
(S)
BIN (-32768 to 32767
Conversion to gray code
(S+1, S)
(D)
BIN (0 to 99999999)
(D)
BCD (0 to 99999999)
BIN (-32768 to 32767)
Real number
(-2147483648 to 2147483647)
Real number
(-32768 to 32767)
Real number
(-2147483648 to 2147483647)
(D+1, D)
Conversion
BIN (-32768 to 32767)
(D)
BIN
(-2147483648 to 2147483647)
(D+1, D)
(D+1, D)
(D)
(D+1, D)
(D)
(D+1, D)
(D)
(D+1, D)
Execution
Condition
Subset
Number of
Basic Steps
3 6-57
3 6-57
3 6-59
3 6-59
36-61
36-61
36-63
36-63
36-65
36-66
36-67
36-67
See for
Description
2 - 19 2 - 19
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2 INSTRUCTION TABLES
)
Table 2.12 Data Conversion Instructions (Continued)
MELSEC-Q/QnA
Category
Conversion
from gray
code to
BIN
Complement to 2
Block conversions
Instruction
GBIN
GBINP
DGBIN
DGBINP
NEG
NEGP
DNEG
DNEGP
ENEG
ENEGP
BKBCD
BKBCDP
BKBIN
BKBINP
Symbol Processing Details
Symbols
GBIN
GBINP
DGBIN
DGBINP SD
BKBCD
BKBCDP nSD
BKBIN nSD
BKBINP nSD
SD
S
SD
NEG
NEGP
DNEG D
DNEGP D
ENEG
ENEGP
Conversion to BIN data
(S)
D
D
D
D
D
nSD
Gray code
(-32768 to 32767)
Conversion to BIN data
(S+1, S)
(D)
BIN data
(D+1, D)
(D+1, D)
• Batch converts BIN data n points from
(S) to BCD data and stores the result
from (D) onward.
• Batch converts BCD data n points from
(S) to BIN data and stores the result
from (D) onward.
(D)
(D+1, D)
Gray code
(-2147483648 to 2147483647)
(D
(D+1, D)
BIN data
(D+1, D)
Real number data
Execution
Condition
Subset
Number of
Basic Steps
36-69
36-69
26-71
26-71
26-73
46-74
46-76
See for
Description
2 - 20 2 - 20
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2 INSTRUCTION TABLES
)
2.4.4 Data transfer instructions
Table 2.13 Data Transfer Instructions
MELSEC-Q/QnA
Category
16-bit data
transfer
32-bit data
transfer
Floating
decimal
point data
transfer
Character
string data
transfer
negation
transfer
negation
transfer
Block
transfer
Multiple
transfers of
same data
block
16-bit data
exchange
Instruction
MOV
MOVP
DMOV
DMOVP
EMOV
EMOVP
$MOV
$MOVP
CML
CMLP
DCML
DCMLP
BMOV
BMOVP
FMOV
FMOVP
XCH
XCHP
Symbol Processing Details
Symbols
MOV
MOVP
DMOV
DMOVP
EMOV
EMOVP
$MOV
$MOVP
CML SD16-bit data
CMLP
DCML SD32-bit data
DCMLP SD
BMOV nSD
BMOVP nSD
FMOV nSD
FMOVP nSD
XCH SD
XCHP SD
SD
SD
SD
SD
SD
SD
SD
S
S
(S)
(S+1, S )
(S+1, S)
• Transfers character string designated by
(S) to device designated by (D) onward.
D
(S)
D
(S)
(S)
(S)
(D)
Real number data
(D)
(D
(D+1, D)
(D+1, D)
(D+1, D)(S+1, S)
(D)
n
(D)
n
Execution
Condition
Subset
Number of
Basic Steps
4
1
2 6-78
2
36-82
1 6-84
2 6-84
4 6-87
4 6-89
3 6-91
See for
Description
6-78
6-80
3
32-bit data
exchange
Block data
exchange
Exchange
of upper
and lower
bytes
DXCH
DXCHP
BXCH
BXCHP
SWAP
SWAPP
DXCH SD
DXCHP SD
BXCH nSD
BXCHP nSD
SWAP D
SWAPP D
(S)
b15 b8b7to to
(S)
8 bits
b15 b8 b7to
8 bits
(D)
(D+1, D)(S+1, S)
(D)
8 bits
to
8 bits
b0
b0
3 6-91
n
46-93
36-95
2 - 21 2 - 21
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2 INSTRUCTION TABLES
REMARK
1) 1:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
2)
2:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
MELSEC-Q/QnA
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
3 Note 2)
2
Note 2)
3
Note 1)
2
Note 2)
3
3)
3 : The subset is effective only with QCPU.
4)
4 : The number of st ep s may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
High Performance model QCPU
Process CPU
Basic model QCPU
QnACPU 3 Note 2)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
Note 1)
Note 2)
Note 1)
Note 2)
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
3
3
2
3
2 - 22 2 - 22
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2 INSTRUCTION TABLES
2.4.5 Program branch instruction
Table 2.14 Program Branch Instruction
MELSEC-Q/QnA
Category
Jump
Symbols
Instruction
CJ
SCJ SCJ Pn
JMP
GOEND
Symbol Processing Details
CJ Pn
JMP Pn
GOEND
• Jumps to Pn when input conditions are
met
• Jumps to Pn from the scan after the
meeting of input condition
• Jumps unconditionally to Pn
• Jumps to END instruction when input
condition is met
2.4.6 Program execution control instructions
Table 2.15 Program Execution Control Instructions
Category
Disable
interrupts
Enable
interrupts
Interrupt
disable
/enable
setting
Return IRET
DI
EI
IMASK
Symbols
Instruction
Symbol Processing Details
DI
EI
IMASK
IRET
• Prohibits the running of an interrupt
program
• Resets interrupt program execution
prohibition
• Prohibits or permits interrupts for each
interrupt program
S
• Returns to sequence program following
an interrupt program
Execution
Condition
Execution
Condition
Subset
Number of
Basic Steps
2 6-96
2 6-96
2
16-99
Number of
Basic Steps
1 6-100
1 6-100
2 6-100
1 6-109
See for
Description
6-96
Subset
See for
Description
2.4.7 I/O refresh instructions
Table 2.16 I/O Refresh Instructions
Category
I/O
Refresh
RFS
RFSP
Symbols
Instruction
Symbol Processing Details
RFS nD
RFSP nD
• Refreshes the relevant I/O area during
scan
2 - 23 2 - 23
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Execution
Condition
Number of
Basic Steps
3 6-111
Subset
See for
Description
2 INSTRUCTION TABLES
C
(D)
2.4.8 Other convenient instructions
Table 2.17 Other Convenient Instructions
MELSEC-Q/QnA
Category
Up/Down
Counter
Teaching
timer
Special
timer
Nearest
path
control
Ramp
signal
Pulse
density
Pulse
output
Instruction
UDCNT1
UDCNT2
TTMR
STMR
ROTC
RAMP
SPD
PLSY
(D)
Execution
Condition
Subset
Number of
Basic Steps
See for
4 6-113
4 6-115
3 6-117
Description
Symbol Processing Details
Symbols
(S)+0
Up Down Up
UDCNT1 nSD
UDCNT2 nSD
(S)+1
urrent Cn value
Cn contact point
Current Cn valu e
Cn contact point
1 2 3 4 6 7 6 5 3 2 1 0 -1 -2 -3 -2 -1 00 45
(S)+0
(S)+1
12 45 43 10-10 3 2
• (Time that TTMR is ON)
n
TTMR nD
n = 0:1, n = 1:10, n = 2:100
• The 4 points from the bit device
designated by (D) operate as shown
below, depending on the ON/OFF status
of the input conditions for the STMR
STMR nSD
instruction:
3 6-119
(D)+0: Off delay timer output
(D)+1: One shot after off timer output
(D)+2: One shot after on timer output
(D)+3: On delay timer output
• Rotates a rotary table with n1 divisions
ROTC n2n1SD
from the stop position to the position
5 6-122
designated by (S+1) by the nearest path.
RAMP D1 n3n1 n2 D2
• Changes device data designated by D1
from n1 to n2 in n3 scans.
6 6-124
• Counts the pulse input from the device
SPD nSD
designated by (S) for the duration of time
designated by n, and stores the count in
4 6-126
the device designated by (D).
PLSY n1 n2 D
(n1)Hz (D)
Output n2 times
4 6-128
Pulse
width
PWM
PWM
n1
n2 D
n1
n2
4 6-130
modulation
Matrix
input
MTR
MTR
S
D2
D1
• Store 16 times of n lows in the device
specified by (S).to the device specified by
n
(D2) in sequence.
5 6-132
2 - 24 2 - 24
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2 INSTRUCTION TABLES
)
)
)
)
)
2.5 Application Instructions
2.5.1 Logical operation instructions
Table 2.18 Logical Operation Instructions
MELSEC-Q/QnA
Category
Logical
product
Instruction
WAND
WANDP
WAND
WANDP
DAND
DANDP
DAND
DANDP
BKAND
BKANDP
WOR
WORP
Symbol Processing Details
Symbols
WAND SD
WANDP SD
WAND S1 S2 D
WANDP S1 S2 D
DAND
DANDP SD
DAND
DANDP
BKAND nS1 S2 D
BKANDP nS1 S2 D
S1 S2 D
S1 S2 D
WOR
WORP
SD
D
S
SD
(S)
(D)
(S2)
(S1)
(D+1, D)
(S1+1, S1)
(S1)
(S)
(D)
(D
(D)
(D+1, D)(S+1, S)
(D+1, D)(S2+1, S2)
(S2) (D)
n
(D
Execution
Condition
Subset
Number of
Basic Steps
3 7-3
4
1 7-3
2
57-8
3 7-10
See for
Description
7-5
3
7-5
3
Logical
sum
Exclusive
OR
WOR
WORP
DOR
DORP
DOR
DORP
BKOR
BKORP
WXOR
WXORP
WXOR
WXORP
WOR S1 S2 D
WORP S1 S2 D
DOR DS
DORP DS
DOR S1 S2 D
DORP S1 S2 D
BKOR nS1 S2 D
BKORP nS1 S2 D
WXOR SD
WXORP SD
WXOR S1S2 D
WXORP S1 S2 D
(S1)
(D)
(S1)
(S2)
(S1)
(S)
(S2)
(D
(S2) (D)
(D
(D
4
(D+1, D)(S+ 1, S)(D+1, D)
(D+1, D)(S2+1, S2)(S1+1, S1)
n
1 7-10
2
57-14
3 7-16
4
7-12
3
7-12
3
7-18
3
2 - 25 2 - 25
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2 INSTRUCTION TABLES
)
)
Table 2.18 Logical Operation Instructions (Continued)
MELSEC-Q/QnA
Category
Exclusive
OR
NON
exclusive
logical sum
Instruction
DXOR
DXORP
DXOR
DXORP
BKXOR
BKXORP
WXNR
WXNRP
WXNR
WXNRP
DXNR
DXNRP
Symbol Processing Details
Symbols
DXOR SD
DXORP SD
DXOR S1 S2 D
DXORP S1 S2 D
BKXORP nS1 S2 D
BKXORP nS1 S2 D
WXNR DS
WXNRP DS
WXNR S1 S2 D
WXNRP S1 S2 D
DXNR DS
DXNRP DS
(D+1, D)
(S1+1, S 1 )
(D)
(S1)
(D+1, D)
(S+1, S ) (D+ 1, D)
(S2+1, S 2 ) (D+1, D
(S1)
(S)
(S2) (D)
(D)
(S2)
(D)
(S+1, S) (D+1, D
n
Execution
Condition
Subset
Number of
Basic Steps
1 7-16
2
57-20
3 7-22
4
1 7-22
See for
Description
7-18
3
7-26
3
DXNR
DXNRP
BKXNR
BKXNRP
DXNR S1 S2 D
DXNRP S1 S2 D
BKXNR nS1
BKXNRP nS1 S2 D
S2 D
(S1+1, S 1 )
(S1)
(S2+1, S 2 ) (D+1, D)
(S2) (D)
n
2
57-28
REMARK
1) 1:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
3 Note 2)
3
Note 1)
Note 2)
7-26
5
3
2 - 26 2 - 26
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2 INSTRUCTION TABLES
2) 2:The number of steps may vary depending on the device and type of CPU module being
used.
Component Nomber of basic steps
High Performance model QCPU
Process CPU
Basic model QCPU
QnCPU
Note 1:With High Performance module QCPU, (1) requires more number of steps, while it can
process the steps faster, as compared with (2).
Note 2:The number of steps may increase due to the conditions described in Section 3.8.
3)
3 : The subset is effective only with QCPU.
2.5.2 Rotation instructions
MELSEC-Q/QnA
(1) When using the following devices only
• Word device : Internal device (except for file register ZR)
• Bit device : Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no index modification.
• Constant : No li mitatio n s
(2) When using devices other than (1)
4 Note 2)
Table 2.19 Rotation Instructions
Note 1)
6
Note 2)
4
Category
Right
rotation
Left
rotation
Right
rotation
Left
rotation
Symbol Processing Details
Symbols
Instruction
ROR
RORP
RCR
RCRP
ROL
ROLP
RCL
RCLP
DROR
ROR nD
RORP nD
RCR nD
RCRP nD
ROL n
ROLP nD
RCL nD
RCLP nD
DROR nD
DRORP DRORP nD
DRCR
DRCRP
DROL
DROLP
DRCL
DRCLP
DRCR nD
DRCRP
DROL nD
DROLP nD
DRCL nD
DRCLP nD
Execution
Condition
(D) b0b15
SM700
Number of
Basic Steps
Subset
See for
Description
3 7-30
Rotates n bits to the right
(D) b0b15
SM700
3 7-30
Rotates n bits to the right
D
SM700
(D) b0b15
3 7-32
Rotates n bits to the left
SM700
b15
(D) b0
3 7-32
Rotates n bits to the left
(D+1) (D)
b16tob15
to
SM700
b0b31
3 7-34
Rotates n bits to the right
(D+1) (D)
b31 b16
to
to
SM700
b0b15
3 7-34
n
D
Rotates n bits to the right
(D+1) (D)
b0b31SM700 b16tob15
to
3 7-36
Rotates n bits to the left
(D+1) (D)
b0b31SM700 b16tob15
to
3 7-36
Rotates n bits to the left
2 - 27 2 - 27
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2 INSTRUCTION TABLES
S
2.5.3 Shift instructions
MELSEC-Q/QnA
Table 2.20 Shift Instructions
Category
n-bit shift
1-bit shift
1-word
shift
Symbol Processing Details
Symbols
Instruction
SFR
SFR nD
SFRP SFRP nD
SFL
SFLP
BSFR
BSFRP
BSFL
BSFLP
DSFR
DSFRP
DSFL
DSFLP
SFL nD
SFLP nD
BSFR nD
BSFRP nD
BSFL nD
BSFLP n
DSFR nD
DSFRP nD
DSFL n
DSFLP n
Execution
b15
b15
0 to 0
b15
bn
bn
Condition
b0
b0 SM700
b0
Subset
Number of
Basic Steps
See for
3 7-38
Description
3 7-38
M700
b15
n
(D)
b0
0 to 0
37-40
0
SM700
n
(D)
37-40
D
SM700
0
n
(D)
3 7-42
0
D
n
(D)
3 7-42
D
0
2.5.4 Bit processing instructions
Table 2.21 Bit processing instructions
Category
Bit set /
reset
Instruction
BSET
BSETP
BRST
BRSTP
Symbols
Symbol Processing Details
BSET nD
(D)
b15
BSETP nD
BRST nD
(D)
b15
bn
BRSTP nD
b0bn
1
b0
0
2 - 28 2 - 28
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Execution
Condition
Subset
Number of
Basic Steps
See for
3 7-44
3 7-44
Description
2 INSTRUCTION TABLES
Table 2.21 Bit processing Instructions (Continued)
MELSEC-Q/QnA
Category
Instruction
TEST
TESTP
Symbols
Symbol Processing Details
TEST S1 S2 D
TESTP S1 S2 D
Bit tests
Batch reset
DTEST
DTESTP
BKRST
DTEST S1 S2 D
DTESTP S1 S2 D
BKRST nS
of bit
devices
BKRSTP
BKRSTP nS
2.5.5 Data processing instructions
Table 2.22 Data Processing Instructions
(S1)
(S1)
(S)
to
Bit designated by (S2)
b31
to
Bit designated by (S2)
ON
OFF
ON
ON
Reset
(S)
OFF
OFF
OFF
OFF
Execution
Condition
(D)b0b15
Number of
Basic Steps
Subset
See for
Description
47-46
(D)b0
47-46
n
37-48
Category
Data
searches
Bit checks
Decode
Encode
Instruction
SER
SERP
DSER
DSERP
SUM
SUMP
DSUM
DSUMP
DECO
DECOP
ENCO
ENCOP
Symbol Processing Details
Symbols
SER nS1 S2 D
SERP nS1 S2 D
DSER nS1 S2 D
DSERP nS1 S2 D
SUM SD
SUMP SD
DSUM SD
DSUMP SD
DECO nDS
DECOP nDS
ENCO nDS
ENCOP nDS
(S1)
32 bits
(S1)
(S)
b15
Decode from 8 to 256
(S)
Decode from 256 to 8
(S)
2nbits
(S2)
(D) :Match No.
(D+1) :Number of matches
(S2)
(D) :Match No.
(D+1) :Number of matches
b0
(D): Number of 1s
(S)(S+1)
(D): Number of 1s
Decode
n
(D)
Encode
n
n
n
2
bits
(D)
n
Execution
Condition
Subset
Number of
Basic Steps
See for
Description
57-50
57-50
3 7-54
3 7-54
47-56
47-58
2 - 29 2 - 29
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2 INSTRUCTION TABLES
Table 2.22 Data Processing Instructions (Continued)
MELSEC-Q/QnA
Category
7-segment
decode
Separating
and linking
Symbol Processing Details
Symbols
Instruction
SEG
SEGP
DIS
DISP
UNI
UNIP
NDIS
NDISP
NUNI NUNI S1 S2D
NUNIP
WTOB
WTOBP
BTOW
BTOWP
SEG SD
SEGP SD
DIS nSD
DISP n
UNI nSD
UNIP nSD
NDIS S1 S2D
NDISP S1 S2D
NUNIP S1 S2D
WTOB nSD
WTOBP nSD
BTOW nSD
BTOWP nSD
S
b3 to b0
(S)
• Separates 16-bit data designated by (S)
into 4-bit units, and stores at the lower 4
bits of n points from (D). (n
D
• Links the lower 4 bits of n points from the
device designated by (S) and stores at
the device designated by (D). (n
• Separates the data at the devices below
that designated by (S1) into bits
designated below (S2) and stores in
sequence from the device designated by
(D).
• Links the data at the devices below that
designated by (S1) in the bits designated
below (S2) and stores in sequence from
the device designated by (D).
• Breaks n-points of 16-bit data from the
device designated by (S) into 8-bit units,
and stores in sequence at the device
designated by (D).
• Links the lower 8 bits of 16-bit data of npoints from the device designated by (S)
into 16-bit units, and stores in sequence
at the device designated by (D).
7SEG
(D)
4)
4)
Execution
Condition
Subset
Number of
Basic Steps
3 7-60
47-62
47-64
47-66
47-71
See for
Description
• Searches the data of n-points from the
device designated by (S) in 16-bit units,
and stores the maximum value at the
device designated by (D).
• Searches the data of n-points from the
device designated by (S) in 16-bit units,
and stores the minimum value at the
device designated by (D).
• Searches the data of 2
the device designated by (S) in 32-bit
units, and stores the maximum value at
the device designated by (D).
• Searches the data of 2
the device designated by (S) in 32-bit
units, and stores the minimum value at
the device designated by (D).
n-points from
n-points from
4
4
Search
MAX
MAXP
MIN
MINP
DMAX
DMAXP
DMIN
DMINP
MAX nSD
MAXP nSD
MIN nSD
MINP nSD
DMAX nSD
DMAXP nSD
DMIN nSD
DMINP nSD
2 - 30 2 - 30
7-75
7-77
7-75
7-77
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2 INSTRUCTION TABLES
Table 2.22 Data Processing Instructions (Continued)
MELSEC-Q/QnA
Category
Sort
Total value
calculations
Instruction
SORT
DSORT
WSUM
WSUMP
DWSUM
DWSUMP
Symbols
SORT S2 D1S1 n D2
S2: Number of comparisons made
•
during one run
D1: Device to turn ON when sort is
•
completed
D2: For system use
•
DSORT S2 D1S1 n D2
S2: Number of comparisons made
•
during one run
D1: Device to turn ON when sort is
•
completed
D2: For system use
•
WSUM nSD
WSUMP nSD
DWSUM nSD
DWSUMP nSD
Symbol Processing Details
• Sorts data of n-points from device
designated by (S1) in 16-bit units.
(n x (n-1)/2 scans required)
• Sorts data of 2 n-points from device
designated by (S1) in 32-bit units.
(n x (n+1)/2 scans required)
• Adds 16 bit BIN data of n points from the
device specified by (S), and stores it in
the device specified by (D).
• Adds 32 bit BIN data of n points from the
device specified by (S), and stores it in
the device specified by (D).
Execution
Condition
Subset
Number of
Basic Steps
See for
Description
67-80
7-83
4
7-85
2 - 31 2 - 31
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2 INSTRUCTION TABLES
2.5.6 Structure creation instruction s
Table 2.23 Structure Creation Instructions
MELSEC-Q/QnA
Category
Number of
repeats
Subroutine
program
calls
Instruction
FOR
NEXT
BREAK
BREAKP
CALL
CALLP
RET
FCALL
FCALLP
ECALL
ECALLP
EFCALL
EFCALLP
COM
Symbol Processing Details
Symbols
FOR n
NEXT
BREAK PnD
BREAKP Pn
CALL Pn S1 to Sn
CALLP Pn S1 to Sn
RET
FCALL Pn S1 to Sn
FCALLP Pn S1 to Sn
ECALL Pn S1 to Sn
: Program Name
ECALLP Pn S1 to Sn
: Program Name
EFCALL Pn S1 to Sn
: Program Name
EFCALLP Pn S1 to Sn
: Program Name
COM
• Executes n times between FOR and
NEXT
• Forcibly ends the execution of the FOR
to NEXT cycle and jumps pointer to Pn.
D
• Executes sub-routine program Pn when
input condition is met.
(S1 to Sn are arguments sent to subroutine program. 0
• Returns from sub-routine program
• Performs non-execution processing on
sub-routine program Pn if input
conditions have not been met
• Executes sub-routine program Pn from
within designated program name when
input condition is met.
(S1 to Sn are arguments sent to subroutine program. 0
• Performs non-execution processing of
sub-routine program Pn from within
designated program name if input
condition is not met.
• Performs link refresh and general data
processing.
n 5)
n 5)
Execution
Condition
Subset
Number of
Basic Steps
2
1
37-89
1
2
+
n
17-94
1
2
+
n
2
3
+
n
2
3
+
n
1 7-016
See for
7-87
7-91
7-95
7-99
7-102
Description
IX 2
Device modification ladder
IXEND
Fixed index modification
1 : n indicates number of arguments for sub-routine program.
2 : n indicates the total of the number of arguments used in the sub-routine program and the number of program name steps.
IXDEV
IXSET
Designates modification value
The number of program name steps is calculated as "number of characters in the program / 2" (decimal fraction is rounded up).
IX
IXEND
IXDEV
IXSET Pn D
• Conducts index modification for
S
individual devices used in device
modification ladder.
• Stores modification value used for index
modification performed between IX
in the device below that
IXEND
designated by (D).
and
1
1
3
2 - 32 2 - 32
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7-112
7-120
2 INSTRUCTION TABLES
2.5.7 Table operation instructions
Table 2.24 Table Operation Instructions
MELSEC-Q/QnA
Category
Table
processing
Instruction
FIFW
FIFWP
FIFR
FIFRP
FPOP
FPOPP
FINS
FINSP
FDEL
FDELP
Symbol Processing Details
Symbols
FIFW SD
FIFWP SD
FIFR SD
FIFRP SD
FPOP SD
FPOPP SD
FINS nSD
FINSP nSD
FDEL nSD
FDELP nSD
(S)
Pointer +1
device
(S)
Pointer
Pointer
(S)
(S)
Designated by n
Pointer
(S)
Pointer
(D)
Pointer -1
Pointer -1
Pointer +1 device
(D)
Pointer
Pointer -1
Designated by n
Pointer +1
(D)
(D)
Pointer +1
(D)
Execution
Condition
Subset
Number of
Basic Steps
3 7-125
3 7-127
3 7-129
4 7-131
4 7-131
See for
Description
2 - 33 2 - 33
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2 INSTRUCTION TABLES
2.5.8 Buffer memory access instru ctions
Table 2.25 Buffer Memory Access Inst ructi ons
MELSEC-Q/QnA
Category
Data read
Data write
Instruction
FROM
FROMP
DFRO
DFROP
TO
TOP
DTO
DTOP
Symbols
Symbol Processing Details
FROM n3n1 n2 D
FROMP n3n1 n2
DFRO n3n1 n2
DFROP n3n1 n2
TO n3n1 n2
TOP n3n1 n2
DTO n3n1 n2
DTOP n3n1 n2
2.5.9 Display instructions
• Reads data in 16-bit units from special
function module
D
• Reads data in 32-bit units from special
D
D
S
S
S
S
function module
• Writes data in 16-bit units to special
function module
• Writes data in 32-bit units to special
function module
Execution
Condition
Subset
Number of
Basic Steps
5 7-134
5 7-134
5 7-137
5 7-137
See for
Description
Category
PR
ASCII print
Display
Reset LEDR
PR
PRC
LED
LEDC
Table 2.26 Display Instructions
Symbol Processing Details
Symbols
Instruction
SM701 When OFF
PR SD
SM701 When ON
PR SD
PRC
S
LED S
LEDC S
LEDR
• Outputs ASCII code of 8 points (16
characters) from device designated by (S)
to output module.
• Outputs ASCII code from device
designated by (S) to 00
• Converts comments from device
designated by (S) to ASCII code and
D
outputs to output module.
• Displays ASCII code of 8 points (16
characters) from the device designated by
(S) at the LED display device on the front
of the CPU.
• Displays the comments from the device
designated by (S) at the LED display
device on the front of the CPU module.
• Resets annunciator and display unit
display.
H
to output module.
Execution
Condition
Subset
Number of
Basic Steps
3
2
1 7-152
See for
7-140
7-143
7-148
7-150
Description
2 - 34 2 - 34
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2 INSTRUCTION TABLES
2.5.10 Debugging and failure diagnosis instructions
Table 2.27 Debu gg in g an d Failure Diagnosis In str uctions
MELSEC-Q/QnA
Category
Checks
Status
latch
Sampling
trace
Program
trace
Symbols
Instruction
CHKST
CHK
CHKCIR
CHKEND
SLT
SLTR
STRA
STRAR
PTRA
PTRAR
PTRAEXE
PTRAEXE
P
Symbol Processing Details
Check Condition
CHKST
CHK
CHKCIR
CHKEND
SLT
SLTR
STRA
STRAR
PTRA
PTRAR
PTRAEXE
PTRAEXEP
• CHK instruction is executed when
CHKST is executable.
• Jumps to the step following the CHK
instruction when CHKST is in a nonexecutable status
• During normal conditions SM80: OFF,
SD80: 0
• During abnormal conditions
ON, SD80: Failure No .
• Starts update in ladder pattern being
checked by CHK instruction
• Ends update in ladder pattern being
checked by CHK instruction
• Executes status latch
• Resets status latch to enable reexecution
• Applies trigger to sampling trace
• Resets sampling trace to enable reexecution
• Applies trigger to program trace
• Resets program trace to enable reexecution
• Executes program trace
SM80:
Execution
Condition
Subset
Number of
Basic Steps
1 7-155
1 7-159
1 7-167
1 7-169
1 7-171
1 7-171
See for
Description
2 - 35 2 - 35
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2 INSTRUCTION TABLES
2.5.11 Character string processing instructions
Table 2.28 Character String Processing Instructions
MELSEC-Q/QnA
Category
BIN to
decimal
ASCII
BIN to
hexadecimal
ASCII
BCD to
decimal
ASCII
Decimal
ASCII to
BIN
Symbols
Instruction
BINDA
BINDAP
DBINDA
DBINDAP
BINHA
BINHAP
DBINHA
DBINHAP
BCDDA
BCDDAP
DBCDDA
DBCDDAP
DABIN
DABINP
DDABIN
DDABINP
Symbol Processing Details
BINDA SD
BINDAP SD
DBINDA SD
DBINDAP SD
BINHA SD
BINHAP DS
DBINHA SD
DBINHAP SD
BCDDA SD
BCDDAP SD
DBCDDA SD
DBCDDAP SD
DABIN SD
DABINP SD
DDABIN SD
DDABINP SD
• Converts 1-word BIN value designated
by (S) to a 5-digit, decimal ASCII value,
and stores it at the word device
designated by (D).
• Converts 2-word BIN value designated
by (S) to a 10-digit, decimal ASCII value,
and stores it at word devices following
the word device number designated by
(D).
• Converts 1-word BIN value designated
by (S) to a 4-digit, hexadecimal ASCII
value, and stores it at a word device
following the word device number
designated by (D).
• Converts 2-word BIN value designated
by (S) to an 8-digit, hexadecimal ASCII
value, and stores it at word devices
following the word device number
designated by (D).
• Converts 1-word BCD value designated
by (S) to a 4-digit, decimal ASCII value,
and stores it at a word device following
the word device number designated by
(D).
• Converts 2-word BCD value designated
by (S) to an 8-digit, decimal ASCII value,
and stores it at word devices following
the word device number designated by
(D).
• Converts a 5-digit, decimal ASCII value
designated by (S) to a 1-word BIN value,
and stores it at a word device number
designated by (D).
• Converts a 10-digit, decimal ASCII value
designated by (S) to a 2-word BIN value,
and stores it at a word device number
designated by (D).
Execution
Condition
Subset
Number of
Basic Steps
3 7-173
3 7-173
3 7-176
3 7-176
3 7-179
3 7-179
3 7-182
3 7-182
See for
Description
• Converts a 4-digit, hexadecimal ASCII
value designated by (S) to a 1-word BIN
value, and stores it at a word device
number designated by (D).
• Converts an 8-digit, hexadecimal ASCII
designated by (S) value to a 2-word BIN
value, and stores it at a word device
number designated by (D).
3 7-185
3 7-185
Hexadecimal ASCII
to BIN
HABIN
HABINP
DHABIN
DHABINP
HABIN SD
HABINP SD
DHABIN SD
DHABINP SD
2 - 36 2 - 36
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2 INSTRUCTION TABLES
Table 2.28 Character String Processing Instructions (Continued)
MELSEC-Q/QnA
Category
Decimal
ASCII to
BCD
Device
comment
read
operation
Character
string
length
detection
BIN to
decimal
character
string
Decimal
character
string to
BIN
Symbols
Instruction
DABCD
DABCDP
DDABCD
DDABCDP
COMRD
COMRDP
LEN
LENP
STR
STRP
DSTR
DSTRP
VAL
VALP
DVAL
DVALP
Symbol Processing Details
DABCD SD
DABCDP SD
DDABCD SD
DDABCDP SD
COMRD SD
COMRDP SD
LEN SD
LENP SD
STR S1 S2 D
STRP S1 S2 D
DSTR S1 S2 D
DSTRP S1 S2 D
VAL D1 D2S
VALP D1 D2S
DVAL D1 D2S
DVALP D1 D2S
• Converts a 4-digit, decimal ASCII value
designated by (S) to a 1-word BCD
value, and stores it at a word device
number designated by (D).
• Converts an 8-digit, decimal ASCII
designated by (S) value to a 2-word
BCD value, and stores it at a word
device number designated by (D).
• Stores comment from device designated
by (S) at a device designated by (D).
• Stores data length (number of
characters) in character string
designated by (S) at a device designated
by (D).
• Converts a 1-word BIN value designated
by (S2) to a decimal character string with
the total number of digits and the
number of decimal fraction digits
designated by (S1) and stores them at a
device designated by (D).
• Converts a 2-word BIN value designated
by (S2) to a decimal character string with
the total number of digits and the
number of decimal fraction digits
designated by (S1) and stores them at a
device designated by (D).
• Converts a character string including
decimal point designated by (S) to a 1word BIN value and the number of
decimal fraction digits, and stores them
at devices designated by (D1) and (D2).
• Converts a character string including
decimal point designated by (S) to a 2word BIN value and the number of
decimal fraction digits, and stores them
at devices designated by (D1) and (D2).
Execution
Condition
Subset
Number of
Basic Steps
3 7-187
3 7-187
3 7-190
3 7-194
4 7-196
4 7-196
4 7-202
4 7-202
See for
Description
Floating
decimal
point to
character
string
Character
string to
floating
decimal
point
ESTR
ESTRP
EVAL
EVALP
ESTR S1 S2 D
ESTRP S1 S2 D
EVAL SD
EVALP SD
• Converts floating decimal point data
designated by (S1) to character string,
and stores them in a device designated
by (D).
• Converts character string designated by
(S) to floating decimal point data, and
stores them in a device designated by
(D).
4 7-207
3 7-214
2 - 37 2 - 37
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2 INSTRUCTION TABLES
Table 2.28 Character String Processing Instructions (Continued)
MELSEC-Q/QnA
Category
Hexadecimal BIN to
ASCII
ASCII to
hexadecimal BIN
Character
string
processing
Floating
decimal
point to
BCD
BCD to
floating
decimal
point data
Instruction
ASC
ASCP
HEX
HEXP
RIGHT
RIGHTP
LEFT
LEFTP
MIDR
MIDRP
MIDW
MIDWP
INSTR
INSTRP
EMOD
EMODP
EREXP
EREXPP
Symbol
Symbols
ASC nSD
ASCP nSD
HEX nSD
HEXP nSD
RIGHT nSD
RIGHTP nSD
LEFT nSD
LEFTP nSD
MIDR S1 S2D
MIDRP S1 S2D
MIDW S1 S2D
MIDWP S1 S2D
INSTR nS1 S2 D
INSTRP nS1 S2 D
EMOD S1 S2 D
EMODP S1 S2 D
EREXP S1 S2 D
EREXPP S1 S2 D
• Converts 1-word BIN values of the device
number and later designated by (S) to
ASCII, and stores only n characters of
them at the device number designated by
(D).
• Converts only n ASCII characters of the
device number and later designated by (S)
to BIN values, and stores them at the
device number designated by (D).
• Stores n characters from the end of a
character string designated by (S) at the
device designated by (D).
• Stores n characters from the beginning of
a character string designated by (S) at the
device designated by (D).
• Stores the designated number of
characters in the character string
designated by (S1) from the position
designated by (S2) at the device
designated by (D).
• Stores the designated number of
characters in the character string
designated by (S1) from the position
designated by (S2) at the device
designated by (D).
• Searches character string (S1) from the
nth character of character string (S2), and
stores matched positions at (D).
• Converts floating decimal point data (S1)
to BCD data with number of decimal
fraction digits designated by (S2) , and
stores at device designated by (D).
• Converts BCD data (S1) to floating
decimal point data with the number of
decimal fraction digits designated by (S2),
and stores at device designated by (D).
Processing Details
Execution
Condition
Subset
Number of
Basic Steps
4 7-218
4 7-220
4 7-222
4 7-225
5 7-229
4 7-231
4 7-233
See for
Description
2 - 38 2 - 38
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2 INSTRUCTION TABLES
(
)
2.5.12 Special function instructions
Table 2.29 Special Function Instructions
MELSEC-Q/QnA
Category
Trigonometric
functions
(Floating
decimal
point data)
Conversion
between
angles and
radians
Instruction
SIN
SINP
COS
COSP
TAN
TANP
ASIN
ASINP
ACOS
ACOSP
ATAN
ATANP
RAD
RADP
DEG
DEGP
Symbol Processing Details
Symbols
SIN SD
SINP SD
COS SD
COSP SD
TAN SD
TANP SD
ASIN SD
ASINP SD
ACOS SD
ACOSP SD
ATAN SD
ATANP SD
RAD SD
RADP SD
DEG SD
DEGP SD
Cos (S+1, S)
-1
(S+1, S)
-1
(S+1, S)
-1
Tan
(S+1, S)
(S+1, S)
Conversion from
angles to radians
(S+1, S)
Conversion from
radians to angles
(D+1, D)Sin (S+1, S)
(D+1, D)
(D+1, D)Tan (S+1, S)
(D+1, D)Sin
(D+1, D)Cos
(D+1, D)
(D+1, D)
(D+1, D)
Execution
Condition
Subset
Number of
Basic Steps
3 7-235
3 7-237
3 7-239
3 7-241
3 7-243
3 7-245
3 7-247
3 7-249
See for
Description
Square
root
Exponent
operations
Natural
logarithms
number
generation
Random
number
series
update
SQR
SQRP
EXP
EXPP
LOG
LOGP
RND
RNDP
SRND
SRNDP
SQR SD
SQRP SD
EXP SD
EXPP SD
LOG SD
LOGP SD
RND DRandom
RNDP D
SRND S
SRNDP S
(S+1, S)
S+1, S
• Generates a random number (from 0 to
less than 32767) and stores it at the
device designated by (D).
• Updates random number series
according to the 16-bit BIN data stored
in the device designated by (S).
(D+1, D)
(D+1, D)e
(D+1, D)Log e (S+1, S)
3 7-251
3 7-253
3 7-255
2 7-257
2 - 39 2 - 39
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2 INSTRUCTION TABLES
Table 2.29 Special Function Instructions (Continued)
MELSEC-Q/QnA
Category
Square
root
Trigonometric
function
Instruction
BSQR
BSQRP
BDSQR
BDSQRP
BSIN
BSINP
BCOS
BCOSP
BTAN
BTANP
BASIN
BASINP
BACOS
BACOSP
BATAN
BATANP
Symbol Processing Details
Symbols
BSQR SD
(S)
(D)+0
+1
Decimal fraction part
Integer part
Execution
Condition
Subset
Number of
Basic Steps
See for
3 7-259
Description
BSQRP SD
BDSQR SD
(S+1, S)
(D)+0
+1
Decimal fraction part
Integer part
3 7-259
BDSQRP SD
BSIN SD
BSINP SD
BCOS SD
BCOSP SD
BTAN SD
BTANP SD
BASIN SD
BASINP SD
BACOS SD
BACOSP SD
BATAN SD
BATANP SD
Sin (S)
Cos (S)
Tan (S)
-1
Sin
(S) (D)+0
-1
Cos
(S) (D)+0
-1
Tan
(S) (D)+0
(D)+0
+1
+2
Decimal fraction pa rt
(D)+0
+1
+2
Decimal fraction part
(D)+0
+1
+2
Decimal fraction part
+1
+2
Decimal fraction part
+1
+2
Decimal fraction p art
+1
+2
Decimal fraction part
Sign
Integer part
Sign
Integer part
Sign
Integer part
Sign
Integer part
Sign
Integer part
Sign
Integer part
3 7-262
3 7-264
3 7-266
3 7-268
3 7-270
3 7-272
2 - 40 2 - 40
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2 INSTRUCTION TABLES
2.5.13 Data control instructions
Table 2.30 Data Control Instructions
MELSEC-Q/QnA
Category
Upper and
lower limit
controls
Dead band
controls
Instruction
LIMIT
LIMITP
DLIMIT
DLIMITP
BAND
BANDP
DBAND
DBANDP
Symbol Processing Details
Symbols
LIMIT S3S1 S2
LIMITP S3S1 S2
DLIMIT S3S1 S2 D
DLIMITP S3S1 S2 D
BAND S3S1 S2 D
BANDP S3S1 S2 D
DBAND S3S1 S2 D
DBANDP S3S1 S2 D
• When (S3) < (S1)
D
D
................ Store va lu e o f ( S1 ) a t ( D)
• When (S1)
• When (S2) < (S3)
• When ((S3)+1, (S3)) < ((S1)+1, S1)
...Store value of ((S1)+1, (S1)) at
((D)+1, (D))
• When ((S1)+1, (S1))
(S2+1, S2)
...Store value of ((S3)+1, (S3)) at
((D)+1, (D))
• When ((S2), (S2)+1) < ((S3), (S3)+1)
...Store value of ((S2)+1, (S2)) at
((D)+1, (D))
• When (S1)
• When (S3) < (S1) ..............(S3)-(S1)
(D)
• When (S2) < (S3) ..............(S3)-(S2)
(D)
• When ((S1)+1, (S1))
((S2)+1, (S2))
...0
• When ((S3)+1, (S3)) < ((S1)+1, (S1))
..((S3)+1, (S3)) - ((S1)+1, (S1))
((D)+1, (D))
• When ((S2)+1, (S2)) < ((S3)+1, (S3))
..((S3)+1, (S3)) - ((S2)+1, (S2))
((D)+1, (D))
(S3) (S2)
................ Store va lu e o f ( S3 ) a t ( D)
................ Store va lu e o f ( S2 ) a t ( D)
((S3)+1, (S3))<
(S3) (S2) ...0 (D)
((S3)+1, (S3))
((D)+1, (D))
Execution
Condition
Subset
Number of
Basic Steps
5 7-274
5 7-274
5 7-277
5 7-277
See for
Description
(D)
(D)
(D)
5 7-280
5 7-280
Zone
controls
ZONE
ZONEP
DZONE
DZONEP
ZONE S3S1 S2 D
ZONEP S3S1 S2 D
DZONE S3S1 S2 D
DZONEP S3S1 S2 D
• When (S3) = 0............0
• When (S3) > 0............(S3)+(S2)
• When (S3) < 0............(S3)-(S1)
• When ((S3)+1, (S3)) = 0
...0
((D)+1, (D))
• When ((S3)+1, (S3)) > 0
...((S3)+1, (S3))+((S2)+1, (S2))
((D)+1, (D))
• When ((S3)+1, (S3)) < 0
...((S3)+1, (S3)) + ((S1)+1, (S1))
((D)+1, (D))
2 - 41 2 - 41
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2 INSTRUCTION TABLES
2.5.14 Switching instructions
MELSEC-Q/QnA
Table 2.31 Switching Instructions
Category
Block
number
designations
File set
Instruction
RSET
RSETP
QDRSE
T
QDRSE
TP
QCDSE
T
QCDSE
TP
Symbol Processing Details
Symbols
• Converts extension file register block
number to number designated by (S).
• Sets file names used as file registers.
• Sets file names used as comment files.
QDRSET
QDRSETP
QCDSET
QCDSETP
RSET S
RSETP S
File Name
File Name
File Name
File Name
: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)
Execution
Condition
Subset
Number of
Basic Steps
2 7-283
2
+
n
2
+
n
See for
7-285
7-287
Description
2 - 42 2 - 42
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2 INSTRUCTION TABLES
2.5.15 Clock instructions
MELSEC-Q/QnA
Table 2.32 Clock Instructions
Category
Read/write
clock data
Clock data
addition/
subtraction
Clock data
translation
Symbols
Instruction
DATERD
DATERDP
DATEWR
DATEWRP
DATE+
DATE+P
DATE-
DATE-P
SECOND
SECONDP
HOUR
HOURP
Symbol Processing Details
DATERD D
DATERDP D
DATEWR S
DATEWRP S
DATE+ S1 S2 D
DATE+P S1 S2 D
DATE S1 S2 D
DATE S1 S2 DP
SECOND SD
SECONDP SD
HOUR SD
HOURP SD
(Clock device) (D)+0 Year
(D)+0 Year
+1
Month
+2
Day
+3
Hour
Minute
+4
Sec.
+5
Day of
+6
week
(S1)
Hour
Minute
+
Sec.
(S1)
Hour
Minute
-
Sec.
(S)
Hour
Minute
Sec.
Sec. (lower level)
Sec. (upper level)
Month
+1
+2
Hour
+3
Minute
+4
+5
Day of
+6
week
(Clock device)
(S2)
Hour
Minute
Sec.
(S2)
Hour
Minute
Sec.
(D)
Sec. (lower level)
Sec. (upper level)
Day
Sec.
(D)
Minute
(D)
Minute
(D)(S)
Hour
Minute
Sec.
Hour
Sec.
Hour
Sec.
Execution
Condition
Subset
Number of
Basic Steps
See for
2 7-289
2 7-293
4 7-297
4 7-299
3 7-301
Description
2 - 43 2 - 43
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2 INSTRUCTION TABLES
2.5.16 Peripheral device instructions
Table 2.33 Peripheral Device Instructions
MELSEC-Q/QnA
Category
Input/
output to
peripheral
devices
Symbols
Instruction
MSG MSG S
PKEY
Symbol Processing Details
PKEY D
2.5.17 Program instructions
Category
Switching
program
execution
statuses
Instruction
PSTOP
PSTOPP
POFF
POFFP
PSCAN
PSCANP
PLOW
PLOWP
Symbols
Symbol Processing Details
PSTOP
PSTOPP
POFF
POFFP
PSCAN
PSCANP
PLOW
PLOWP Program Name
Program Name
Program Name
Program Name
Program Name
Program Name
Program Name
Program Name
• Stores message designated by (S) at
QnACPU.
This message is displayed at the
peripheral device
• Data input from the peripheral device is
stored at device designated by (D).
Table 2.34 Program Instructions
• Places designated program in standby
status
• Turns OUT instruction coil of designated
program OFF, and places program in
standby status.
• Registers designated program as scan
execution program.
• Registers designated program as lowspeed execution program.
Execution
Condition
Execution
Condition
Subset
Subset
See for
See for
7-308
7-309
7-311
7-313
Number of
Basic Steps
2 7-303
2 7-305
Number of
Basic Steps
2
+
n
2
+
n
2
+
n
2
+
n
Description
Description
: n ([number of program name characters] / 2) indicates a step. (Decimal fractions are rounded up.)
2 - 44 2 - 44
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2 INSTRUCTION TABLES
2.5.18 Other instructions
MELSEC-Q/QnA
Table 2.35 Other Instructions
Category
WDT reset
Timing
clock
Direct
read/write
operations
in 1-byte
units
Numerical
key input
from
keyboard
of index
register
Batch
recovery of
index
register
Batch write
operation
to
2
PROM
E
file register
Symbols
Instruction
WDT
WDTP
DUTY
ZRRDB
ZRRDBP
ZRWRB
ZRWRBP
ADRSET
ADRSETP
KEY
ZPUSH
ZPUSHP
ZPOP
ZPOPP
EROMWR
EROMWRP
Symbol Processing Details
WDT
• Resets watchdog timer during
sequence program
WDTP
(D)
DUTY n1 n2 D
ZRRDB nD
ZRRDBP nD
ZRWRB n S
(S)
n1 scan
SM420 to SM424, SM430 to SM434
0
Lower 8 bits
1
Upper 8 bits
2
Lower 8 bits
3
Upper 8 bits
n
8 bits
ZRWRBP n S
ADRSET DS
ADRSETP SD
(S) (D)
Device name
• Takes in ASCII data for 8 points of input
KEY D1D2nS
unit designated by (S), converts to
hexadecimal value following device
number designated by D1, and stores.
ZPUSH DBatch save
ZPUSHP D
ZPOP D
ZPOPP D
EROMWR D1 D2nS
• Saves the contents of index registers
Z0 to Z15 to a location starting from the
device designated by D.
• Reads the data stored in the location
starting from the device designated by
D to index registers Z0 toZ15.
• Writes a batch of data to E2PROM file
register.
EROMWRP D1 D2nS
n2 scan
ZR0
ZR1
(D)
0
Lower 8 bits
1
Upper 8 bits
2
Lower 8 bits
3
Upper 8 bits
n
8 bits
Indirect address of
designated device
ZR0
ZR1
Execution
Condition
Subset
Number of
Basic Steps
See for
1 7-315
4 7-317
3 7-319
3 7-321
3 7-323
5 7-324
2 7-328
5 7-332
Description
2 - 45 2 - 45
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2 INSTRUCTION TABLES
2.5.19 Instructions for data link
Table 2.36 Instructions for Data Link
MELSEC-Q/QnA
Category
Network
refresh
QnA link
instruction:
Reading
data from
another
station
QnA link
instruction:
Writing
data to
other
stations
Instruction
ZCOM
READ
SREAD
WRITE
SWRITE
Symbol Processing Details
Symbols
Execution
Condition
Number of
Basic Steps
Subset
See for
Description
J.ZCOM Jn
JP.ZCOM Jn
Refreshes the designated network. 58-6
G.ZCOM Un
GP.ZCOM Un
J.SREAD
G.SREAD
JP.SREAD
GP.SREAD
JnJ.READ
JnG.READ
JnJP.READ
UnGP.READ
Jn
S1
Un
S1
Jn
S1
Un
S1
JnJP.WRITE
UnGP.WRITE
JnJ.SWRITE
UnG.SWRITE
JnJP.SWRITE
UnGP.SWRITE
D2D1S2S1
D2
D1S2S1
D2D1S2S1
D2D1S2S1
Reads the word device data of another
station to host station.
D3D2D1S2
D3D2D1S2
D3D2D1S2
D3D2D1S2
D2D1S2S1JnJ.WRITE
D2D1S2S1UnG.WRITE
D2D1S2S1
D2D1S2S1
Writes the data of host station to the word
device of other stations.
D3
D2D1S2S1
D2D1S2S1
D3
D3
D2D1S2S1
D2D1S2S1
D3
98-12
10 8-18
10 8-24
11 8-31
QnA link
instruction:
Sending
data
QnA link
instruction:
Receiving
data
QnA link
instruction:
Transient
requests
from other
stations
SEND
RECV
REQ
JnJ.SEND
UnG.SEND
JnJP.SEND
UnGP.SEND
JnJ.RECV
UnG.RECV
JnJ.REQ
UnG.REQ
D1S2S1
D1S2S1
Sends data (message) to other stations. 88-38
D1S2S1
D1S2S1
D1S2S1
D1S2S1
Receives data (message) sent to the host
station.
D1S2S1JnJP.RECV
D1S2S1UnGP.RECV
D2D1S2S1
D2D1S2S1
Sends a transient request to other stations
and executes it.
D2D1S2S1JnJP.REQ
D2D1S2S1UnGP.REQ
88-46
88-52
2 - 46 2 - 46
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2 INSTRUCTION TABLES
Table 2.36 Instructions for Data Link (Continued)
MELSEC-Q/QnA
Category
QnA link
instruction:
Reading
data from
special
function
modules at
remote I/O
stations
QnA link
instruction:
Writing data
to special
function
module at
remote I/O
station
A-series
compatible
link instruction:
Reading
device data
from other
stations
A-series
compatible
link instruction: Writing
device data
to other
stations
A-series
compatible
link instruction:
Reading
data from
special
function
module at
remote I/O
station.
A-series
compatible
link instruction: Writing
data to
special
function
modules at
remote I/O
stations.
Reading
routing
information
Instruction
ZNFR
ZNTO
ZNRD
ZNWR
RFRP
RTOP
RTREAD
Symbol Processing Details
Symbols
Execution
Condition
Number of
Basic Steps
Subset
See for
Description
D1S2S1JnJP.ZNFR
Reads data from the special
function modules at remote I/O
88-64
stations.
D1S2S1UnGP.ZNFR
DS2S1JnJ.ZNTO
DS2S1JnJP.ZNTO
Writes data to the special
J.ZNWR
Jn n1
function module at remote I/O
D
S2S1UnG.ZNTO
S2S1UnGP.ZNTO
station
D
D2n2SD1J.ZNRD Jn n1
Reads the word device data of
other station to host station.
D2n2SD1JP.ZNRD Jn n1
n2
D2
SD1
Writes the data of host station
to the word device of other
stations.
D2n2SD1JP.ZNWR Jn n1
88-69
32
32
8-74
8-78
8-81
8-85
D2n2D1n1G.RFRP Un
Reads data from the special
function module at remote I/O
11 8-88
station.
D2n2D1n1GP.RFRP Un
Dn2D1n1G.RTOP Un
Writes data to the special
function module at remote I/O
11 8-92
station.
Dn2D1n1GP.RTOP Un
DnZ.RTREAD
Reads data set at routing
parameters.
DnZP.RTREAD
78-96
Writes routing data to the area
Registering
routing
information
RTWRITE
SnZ.RTWRITE
designated by routing
parameters.
SnZP.RTWRITE
8 8-100
2 - 47 2 - 47
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2 INSTRUCTION TABLES
2.5.20 QCPU instructions
MELSEC-Q/QnA
Table 2.37 QCPU Instructions
Category
Symbols
Instruction
Reading
module
information
Trace set TRACE
Trace reset TRACER TRACER
Writing
data to
designated
file
Reading
data from
designated
file
Loading
program
from
memory
Unloading
program
from
program
memory
Load +
unload
Highspeed
block
transfer of
file register
Writ e to
host station
CPU
shared
memory
Read from
another
station
CPU
shared
memory
Automatic
refresh of
CPU
shared
memory
UNIRD
UNIRDP
SP.FWRITE
SP.FREAD
PLOADP
PUNLOADP
PSWAPP
RBMOV
RBMOVP
S. TO
SP. TO
FROM
FROMP
COM
Symbol Processing Details
UNIRD n1 n2D
UNIRDP n1 n2D
TRACE
SP.FWRITE S1 S2S0 D0 D1U0
SP.FREAD S1 S2S0 D0 D1U0
PLOADP SD
PUNLOADP SD
PSWAPP S1 S2 D
RBMOV SnD
RBMOVP SnD
COM
Execution
Condition
Number of
Basic Steps
• Reads the module information stored in
the area starting from the I/O No.
designated by (n) by the points
designated by (n2), and stores it in the
area starting from the device
designated by (d).
• Stores trace data set at a peripheral
device to trace file in IC memory card
by the designated number when
SM800, SM801, and SM802 turns ON.
• Resets the data set by TRACE
instruction.
• Writes data to the designated file. 11 9-7
• Reads data from the designated file. 11 9-15
• Transfers the program stored in a
memory card or standard memory
(other than drive 0) to drive 0 and
places the program in standby status.
• Deletes the standby program stored in
standard memory (drive 0).
• Deletes standby program stored in
standard memory (drive 0) designated
by (S1). Then, transfers the program
stored in a memory card or standard
memory (other than drive 0) designated
by (S2) to drive 0 and places it in
standby status.
• Transfers n points of 16-bit data from
the device designated by (S) to the
location starting from the device
designated by (D).
Dn4n3n2S.TO n1
• Writes the device data of the host
station to the shared memory area of
the host station CPU module.
Dn4n3n2SP.TO n1
n3Dn2n1FROM
• Reads device data from the CPU
shared memory area of another station
CPU module to the host station.
n3Dn2n1FROMP
• Performs the automatic refresh of the
intelligent function module, general data
processing, and the automatic refresh
of the CPU shared memory.
49-2
19-5
19-5
39-26
39-28
49-30
49-32
59-35
59-37
19-39
Subset
See for
Description
2 - 48 2 - 48
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2 INSTRUCTION TABLES
2.5.21 Redundant system instructions (For Q4ARCPU)
Table 2.38 Redundant system instructions (For Q4ARCPU)
MELSEC-Q/QnA
Category
Operation
mode
setting
during
CPU start
up
Operation
mode
setting
instructions
during
CPU
switch
Data
tracking
Buffer
memory
batch
refresh
Symbols
Instruction
S.STMODE
S.CGMODE
S.TRUCK
S.SPREF
Symbol Processing Details
• Designates the operation mode at (S1)
whether to clear the Q4ARCPU devices
S.STMODE S1 S2
S.CGMODE S
S.TRUCK S
S.SPREF S
before startup or not to clear them
before startup when the power supply is
turned on for CPU startup.
• Designates the operation mode at (S1)
whether to clear the Q4ARCPU devices
before startup or not to clear them
before startup when control is switched
from the control system to the standby
system.
• Conducts device memory tracking in
accordance with the parameter block
data contents stored in the area starting
from the device designated by (S)
during END processing.
• Batch reads/writes the contents of
special function module buffer memory
in accordance with the contents of
parameter block data stored in the area
starting from the device designated by
(S).
Execution
Condition
Subset
Number of
Basic Steps
9 10-2
7 10-4
6 10-6
6 10-10
See for
Description
2 - 49 2 - 49
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3 CONFIGURATION OF INSTRUCTIONS
3. CONFIGURATION OF INSTRUCTIONS
3.1 Configuration of Instructions
Most CPU module instructions consist of an instruction part and a device part.
• Instruction part.....Indicates the function of the instruction
• Device part ..........Indicates the data that is to be used with the instruction.
The device part is classified into source data, destination data, and number of devices.
3
(1) Source
(a) Source is the data used for operations.
(b) The following source types are available, depending on the designated device:
S
• Constants.....................................Designates the numeric value to be used in the
operation.
This is set when the program is written, and cannot
be changed during the execution of the program.
Constants should be indexed when using them as
variable data.
• Bit devices and Word devices.....Designates the device that stores the data to be
used for the operation.
Data must be stored in the designated device until
when the operation is executed.
By changing the data stored in a designated device
during program execution, the data to be used in
the instruction can be chan g ed.
MELSEC-Q/QnA
(2) Destination
D
(a) The destination stores the data after the operation has been conducted.
However, some instructions require storing the data to be used in an operation at the
destination prior to the operation execution.
Example: A n addition in struction involving BIN 16-bit data
S1
DS D
Stores the data needed for operation
prior to the actual operation.
++
Stores only the operation results.
S2
(b) A device for the data storage must always be set to the destination.
3 - 1 3 - 1
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3 CONFIGURATION OF INSTRUCTIONS
e
(3) Number of devices and number of transfers (n)
(a) The number of devices and number of transfers designate the numbers of devices and
transfers used by instructions involving multiple devices.
Example: Block transfer instruction
S
Designates the number of transfers
used by a BMOV instruction
(b) The number of devices or number of transfers can be set between 0 and 32767.
However, if the numbe r i s 0, the in stru cti on will be a no- ope ratio n instru cti on .
3.2 Designating Data
The following five types of data can be used with CPU module instructions:
Data that can be
handled by CPU
Bit data
MELSEC-Q/QnA
D
nBMOV
3
3.2.1 Using bit data
Bit data is data used in one-bit units, such as for contact points or coils. "Bit devices" and "Bit
designated word devices" can be used as bit data.
(1) When using bit devices
Bit devices are designated in one-point units.
M0
Numeric data Integer data
Real number
(floating decimal
point) data
Character string data
The 1-point M0 is a bit device
SET Y10
The 1-point Y10 is a bit devic
Word data
Double word data
(2) Using word devices
(a) Word devices enable the use of a designated bit number 1/0 as bit data by the designation
of that bit number.
Word device
b15 b0
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
to
Each bit can be used as 1
for ON and 0 for OFF.
3 - 2 3 - 2
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3 CONFIGURATION OF INSTRUCTIONS
(b) Word device bit designation is done by designating ” Word Device Bit No. ” .
(Designation of bit numbers is done in hexadecimal.)
For example, bit 5 (b5) of D0 is designated as D0.5, and bit 10 (b10) of D0 is designated as
D0.A.
However, there can be no bit designation for timers (T), retentive timers (ST), counters (C)
or index register (Z). (Example Z0.0 is not available)
X0
SET D0.5
D0.5
SET Y10
3.2.2 Using word (16 bits) data
Word data is 16-bit numeric data used by basic instructions and application instructions.
The following two types of word data can be used with CPU module:
• Decimal constants..........................K-32768 to K32767
• Hexadecimal constants..................H0000 to HFFFF
MELSEC-Q/QnA
Word device bit designation.
(Bit 5 (b5) of D0 designated as
ON (1).)
Word device bit designation.
(Turned ON or OFF according
to the 1/O status of bit 5 (b5)
of D0.)
Word devices and bit devices designated by digit can be used as word data.
For direct access input (DX) and direct access output (DY), word data cannot be designated by
digit output (DY). (For details of direct access input and direct access output, refer to the User’s
Manual (Function Explanation, Program Fundamentals) of the CPU module in use, or the
QnACPU Programming Manual (Fundamentals).).
(1) When using bit devices
(a) Bit devices can deal with word data when digits are designated.
Digit designation of bit devices is done by designating ” Number of digits
Initial number o f bi t dev i ce ” .Digit designation of bit devices can be done in 4-point (4-bit)
units, and designation can be made for K1 to K4.
(For link direct devices, designation is done by ”J Network No.
Initial number o f bi t dev i ce
” . When X100 to X10F are designated for Network No.2, it is
\ Digit designation
done by J2\K4X100.)
For example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0.........The 4 points X0 to X3 are designated
• K2X0.........The 8 points X0 to X7 are designated
• K3X0.........The 12 points X0 to XB are designated
• K4X0.........The 16 points X0 to XF are designated
3 - 3 3 - 3
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3 CONFIGURATION OF INSTRUCTIONS
XB
XF
Fig 3.1 Digit Designation Setting Range for 16-Bit Instruction
XC
to to to to
K4 designation range
MELSEC-Q/QnA
X8 X7 X4 X3 X0
K1 designation
range
(4 points)
K2 designation range
(8 points)
K3 designation range
(12 points)
(16 points)
(b) In cases where digit designation has been made at the source
S
shown in Table 3.1 are those which can be dealt with as source data.
Table 3.1 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits Designated With 16-Bit Instruction
K1 (4 points) 0 to 15
K2 (8 points) 0 to 255
K3 (12 points) 0 to 4095
K4 (16 points) -32768 to 32767
In cases where the source is a bit device designated by digit designation, and the
destination is a word device, the word device for the destination becomes 0 following
the bit designated by digit designation at the source.
Ladder Example Processing
With 16-bit instruction
X010
MOV K1X0 D0
S
Source data
b15 b4
0 0 X3
D0
Become 0
0000000000 X2X1X0
Fig 3.2 Ladder Example and Processing Conducted
, the numeric values
K1X0
X3X2X1X0
b0
b1b2b3
(c) In cases where digit designation is made at the destination
D
, the number of points
designated are used as the destination. Bit devices below the number of points designated
as digits do no t ch an ge .
Ladder Example Processing
When source S data is a numerical value
X010
MOV H1234 K2M0
Destination
When source S data is a word device
X10
MOV D0 K2M100
Destination
12
M15 M8
D
D
K2M0
Do not change
b15 b8
D0 10011101
M115
K2M100
Do not change
3
0 0 1 1 0 1 00H1234 00100100
M7 M0
0 0 1 1 0 1 00
3 4
b7 b0
1 0 0 1 1 1 01
M108
M107
1
0 0 1 1 1 01
4
M100
Fig 3.3 Ladder Example and Processing Conducted
3 - 4 3 - 4
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3 CONFIGURATION OF INSTRUCTIONS
(2) When using word devices
Word devices are designated in 1-point (16 bits) units.
M0
MOV K100 D0
POINTS
(1) When digit designation processing is conducted, a random value can be used
for the bit device ini tial devi ce numbe r.
(2) Digit designation cannot be made for the direct device designation DX and DY.
3.2.3 Using double word data (32 bits)
Double word data is 32-bit numerical data used by basic instructions and application instructions.
The two types of double word data that can be dealt with by CPU module are as follows:
• Decimal constants...............K-2147483648 to K2147483647
• Hexadecimal constants.......H00000000 to HFFFFFFFF
MELSEC-Q/QnA
1 D0 point (16 bits) is word device
Word devices and bit devices designated by digit designation can be used as double word data.
For direct access input (DX) and direct access output (DY), designation of double word data is not
possible by digit designation.
(1) When using bit devices
(a) Digit designation can be used to enable a bit device to deal with double word data.
Digit designation of bit devices is done by designating ” Number of digits
Initial number o f bi t dev i ce ”.
Digit designation of bit devices can be done in 4-point (4-bit) units, and designation can be
made for K1 to K8.
(For link direct devices, designation is done by ”J Network No.
Initial number o f bi t dev i ce
done by J2\K8X100.)
For example, if X0 is designated for digit designation, the following points would be
designated:
• K1X0.........The 4 points X0 to X3 are designated
• K2X0.........The 8 points X0 to X7 are designated
• K3X0.........The 12 points X0 to XB are designated
• K4X0.........The 16 points X0 to XF are designated
• K5X0.........The 20 points X0 to X13 are designated
• K6X0.........The 24 points X0 to X17 are designated
• K7X0.........The 28 points X0 to X1B are designated
• K8X0.........The 32 points X0 to X1F are designated
” . When X100 to X11F are designated for Network No.2, it is
\ Digit designation
3 - 5 3 - 5
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3 CONFIGURATION OF INSTRUCTIONS
6
X1F X1C X1B X18X17 X14X13 X10XF XC XB X8X7 X4X3 X0
K7 designation range
K8 designation range
(32 points)
Fig 3.4 Digit Designation Setting Range for 32-Bit Instructions
MELSEC-Q/QnA
K1 designation
range
(4 points)
K2 designation range
(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)
K5 designation range
(20 points)
K6 designation range
(24 points)
(28 points)
(b) In cases where digit designation has been made at the source
S
, the numeric values
shown in Table 3.2 are those which can be dealt with as source data.
Table 3.2 List of Numeric Values that Can Be Dealt with as Digit Designation
Number of Digits
Designated
K1 (4 points) 0 to 15 K5 (20 points) 0 to 1048575
K2 (8 points) 0 to 255 K6 (24 points) 0 to 16777215
K3 (12 points) 0 to 4095 K7 (28 points) 0 to 268435455
K4 (16 points) 0 to 65535 K8 (32 points) -2147483648 to 2147483647
With 32 bit
Instructions
Number of Digits
Designated
With 32 bit Instructions
In cases where the source is a bit device designated by digit designation, and the
destination is a word device, the word device for the destination becomes 0 following the bit
designated by digit designation at the source.
Ladder Example Processing
With 32-bit instruction
X10
DMOV K1X0 D0
S
Souce data
Become 0
b15 b4
0000000000 X2X1X0
00 X3
0
00D1 0000000000
b31 b1
K1X0
X3X2 X1 X0
b2b3
b1
0000
b0
Become 0
Fig 3.5 Ladder Example and Processing Conducted
3 - 6 3 - 6
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3 CONFIGURATION OF INSTRUCTIONS
(c) In cases where digit designation is made at the destination D, the number of points
designated are used as the destination.
Bit devices after the number of points designated as digits do not change.
Ladder Example Processing
When source S data is a numerical value
X10
DMOV H78123456 K5M0
Destination
When source S data is a word device
X10
DMOV D0 K5M10
Destination
MELSEC-Q/QnA
H78123456
10 0 1010010011 100
3 4 5 6
10000011
7
K5M0
M15 M8M7 M0
D
M31 M20
b15 b8
1001110 0
D0
b15 b8
D1
D
10000011
M25 M18
1001110 0
M41 M30M29 M26
8 1 2
Do not change
00 1 00 011
10 0 10100
b7 b0
100 1 1 101
0b701 1 0 1 11
M17 M10
100 1 1 101
10011 100
M19 M16
1000
b0
1101
Do not change
Fig 3.6 Ladder Example and Processing Conducted
POINTS
(1) When digit designation processing is conducted, a random value can be used
for the bit device ini tial devi ce numbe r.
(2) Digit designation cannot be made for the direct device designation DX and DY.
(2) When using word devices
A word device designates devices used by the lower 16 bits of data.
A 32-bit instruction uses (designation device number) and (designation device number + 1).
M0
DMOV K100 D0
The 2 points D0 and D1 are used
32-bit data transfer instruction
3 - 7 3 - 7
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3 CONFIGURATION OF INSTRUCTIONS
3.2.4 Using real number data
Real number data is 32-bit floating decimal point data used with basic instructions and application
instructions.
Only word devices are capable of storing real number data.
Instructions which deal with real numbers designate devices which are used for the lower 16 bits
of data. Real numbers are stored in the 32 bits which make up (designated device number) and
(designated device number + 1).
M0
EMOV R100 D0
REMARK
MELSEC-Q/QnA
The 2 points D0 and D1 (32 bits) are used
The 2 points R100 and R101
(32 bits) are used
Real number data transfer
1) In sequence programs, real numbers are designated by E .
Floating decimal point data uses two word devices and is expressed in the following manner:
1. [Variable part] × 2 [exponent part]
The bit configuration and meaning of the internal representation of floating decimal point data is as
follows:
b31 b30
b31
Sign for variable part
to
b23 to b30
Expon en t part
b22 b16tob15 b0
b23
b0 to b22
Variable part
to
• Sign for variable part The sign for the variable part is represented at b31.
0: Positive
1: Negative
n
• Exponent part The n of 2
is represented from b23 to b30.
Depending on the BIN value of b23 to b30, the value of n is as follows.
b23 to b30 FFHFEHFD
Nonnumeric
n
127 126 2 1 0 -1 -125 -126
H
81H80H7FH7E
H
02H01H00
H
Nonnumeric
• Exponent part The 23 bits from b0 to b22, represents the XXXXXX... at binary
1.XXXXXX....
POINT
• The CPU module floating decimal point data can be monitored using the
monitoring function of a peripheral device.
• When this is expressed as 0, all data from b0 to b31 will be 0.
• The setting range of real numbers is 0 and ±2
3 - 8 3 - 8
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-126
| value | < 2
128
.
3 CONFIGURATION OF INSTRUCTIONS
3.2.5 Using character string data
Character string data is character data used by basic instructions and application instructions.
It encompasses all data from the designated character to the NULL code (00
(1) When designated character is the NULL code.
One word is used to store the NULL code.
M0
(2) When character string is even
Uses (number of characters/2 + 1) words, and stores character string and NULL code.
For example, if "ABCD" is transferred to D0, the character string ABCD is stored at D0 and D1,
and the NULL code is stored at D2.
M0
$MOV D0
" "
$MOV "ABCD"
D0
MELSEC-Q/QnA
D0 NULL
NULL code (00H) designation
Character string data transfer
H
).
H
H
NULL
41
43
H
H
D0
42
44
D1
D2
Designation of an even number
character string
Character string data transfer
(3) When number of characters is odd
Uses (number of characters/2) words (rounds up decimal fractions) and stores the character
string and NULL code.
For example, if "ABCDE" is transferred to D0, the character string (ABCDE) and the NULL
code are stored from D0 to D2.
M0
$MOV
"ABCDE"
D0
H
D0
42
D1
44
NULL
D2
Designation of an odd number
character string
Character string data transfer
H
41
H
H
43
H
45
3 - 9 3 - 9
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3 CONFIGURATION OF INSTRUCTIONS
=
3.3 Index Modification
(1) Index modification
(a) Index modification is an indirect setting made by using an index register.
When an index modification is used in a sequence program, the device to be used will
become the device number designated directly plus the contents of the index register.
For example, if D2Z2 has been designated the designated device is calculated as follows:
D(2+3)=D5 and the content of Z2 is 3 become the designated device.
(b) There are 16 index registers, from Z0 to Z15.
Each index register can be set between -32768 and 32767.
X0
MOV K-1 Z0
MELSEC-Q/QnA
The value -1 is stored at Z0
X0
MOV D10Z0 D0
Index modification
The data D10Z0
D9, is stored at D0
=
D {10 + (-1)}
Example
A case where index modification has been performed, and the actual process device, would be
as follows: (When Z0 = 20 and Z1 = -5)
Ladder Example Actual Process Device
X0
MOV K20 Z0
MOV K-5 Z1
X1
MOV K100Z0 W53Z1
X0
MOV K20 Z0
MOV K-5 Z1
X1
MOV K120 W04E
Description
K100Z....K (100+20) = K120
W53.......W (53-5) = W4E
Hexadecimal number
X1
MOV K2X64 K1M33
Description
K2X50Z....K2X (50+14) = K2X64
X1
X0
X1
MOV K2X50Z0 K1M38Z1
MOV K20 Z0
MOV K-5 Z1
MOV D0Z0 K3Y12FZ1
K1M38......K1M (38-5) = K1M33
X1
Description
D0Z.........D (0+20) = D20
K3Y12F... K3 Y ( 1 2 F-5) = K3Y12A
K20 is converted to hexadecimal
MOV D20 K3Y12A
Hexadecimal number
Fig. 3.7 Ladder Example and Actual Process Device
3 - 10 3 - 10
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3 CONFIGURATION OF INSTRUCTIONS
(2) Devices which can be index-modified
With the exception of the restrictions noted below, index modification can be used with devices
used with contacts, coils, basic instructions, and application instructions.
(a) Devices which cannot use index modification
Device Meaning
K, H 32-bit constant
E Floating decimal point data
$ Character-string data
, Bit designated for word device
FX, FY, FD Function devices
P Pointers used as label s
I Interrupt pointers used as labels
Z Index register
S Step relay
TR SFC transfer devices 1
BL SFC block devices 1
T, ST Value set for timer
C Value set for counter
MELSEC-Q/QnA
(b) Devices with limits for use with index registers
Device Meaning Application Example
T
C
• Only Z0 and Z1 can be used for timer
contacts and coils
• Only Z0 and Z1 can be used for counter
contacts and coils
T0Z0
C0Z1
K100
T1Z1
K100
C1Z0
REMARKS
1) 1: SFC transfer devices and SFC block devices are devices for SFC use.
Refer to the QCPU (Q mode)/QnACPU Programming Manual (SFC) for information on
how to use these devices.
2) For timer and counter present values, there are no limits on index register numbers used.
Set value of timer
X0
SM400
X1
SM400
K100
T0
T0Z4 K4Y30BCD
K10
C100
C100Z6 K2Y40BCD
(Index modification not possible)
Present value of timer
Set value of counter
(Index modification not possible)
Present value of counter
3 - 11 3 - 11
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3 CONFIGURATION OF INSTRUCTIONS
(c) Other
1) Bit data
Device numbers can be index modified when performing digit designation.
However, inde x mod i fi cati on is no t possible by digit designa ti on .
BIN K4X0Z2 D0
BIN K4Z3X0 D0
2) Both I/O numbers and buffer memories can be index modified with special function
module devices.
MOV U10Z1\G0Z2 D0
MELSEC-Q/QnA
Setting that enables device
number index modification
If Z2 = 3, then X (0+3) = X3.
Setting t hat canno t enable
digit designation index
modification
If Z1 = 2 and Z2 = 8, then
U (10+2)\G (0+8) = U12\G8.
3) Both network numbers and device numbers can be index modified with link direct
devices.
MOV J1Z1\K4X0Z2 D0
If Z1 = 2 and Z2 = 8, then
J (1+2)\K4X (0+8) = J3\K4X8.
REMARKS
1) 1: Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the
used CPU module or QnACPU Programming Manual (Fundamentals) for special
function module device.
2)
2: Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the
used CPU module or QnACPU Programming Manual (Fundamentals) for link direct
devices.
3 - 12 3 - 12
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3 CONFIGURATION OF INSTRUCTIONS
0
3.4 Indirect Designation
(1) Indirect Designation
(a) Indirect designation is a way of using a word device to designate a device address that will
be used in a sequence program.
This method can be used when the index register is insufficient.
(b) The device which designates the designated device address is designated by
"@+(word device number)".
For example, designation of @D100 will make the contents of D100 D101 the device
address.
(c) The address of the device performing indirect designation can be confirmed with the
ADRSET instruction.
MELSEC-Q/QnA
ADRSET W100 D100
MOV K1234 @D100
Reads the contents of
D100
W100 address is stored at D101 and D100
The value 1234 is
written to the designation
address by D101 and D10
D0
D1
W100D100
addressD101
Device area
1234W100
3 - 13 3 - 13
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3 CONFIGURATION OF INSTRUCTIONS
(2) Devices Cap abl e of Indi r e ct D e signa ti on
The CPU module devices that can be designated indirectly is shown in Table 3.3.
Table 3.3 List of Devices Capable of Indirect Designation
MELSEC-Q/QnA
Device Type
Bit devices 1 Incapable
Internal user devices
Link direct devices
Special direct devices Capable 3
Index register Incapable
File register Capable
Nesting
Pointer
Constants
Other
Word devices
Bit devices 1 Incapable
Word devices
SFC block devices
Devices below SFC
Network No.
I/O No.
1 Capable
1 Capable 3
Capable/Incapable of
Indirect Designation
Incapable
REMARKS
1) 1: Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the
used CPU module or QnACPU Programming Manual (Fundamentals) for device names.
2)
2: Indicates index modification by index register
3)
3: The device can be designated indirectly, however the address cannot be written in the
ADRSET instruction.
Example of Indirect
Designation
• @D100
• @D100Z2
• @J1\W10
• @J1Z1\W10Z2
• @U10\G0
• @U10Z1\G0Z2
• @R0, @ZR20000
• @R0Z1, @ZR20000Z1
2
2
2
2
(3) Cautions
The address for indirect designation is designated using two words.
Therefore, to substitute indirect designation for index modification, the addition/subtraction of
32-bit data is req ui r ed .
The following is the ladder used for the addition/subtraction of the address of the device stored
in D1 and D0 for indirect designation.
[To add "1" to the address of the device for indirect designation]
DINCP D0
Device used for indirect designation
32-bit instruction
[To subtract "1" from the address of the device for indirect designation]
DDECP D0
Device used for indirect designation
32-bit instruction
3 - 14 3 - 14
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3 CONFIGURATION OF INSTRUCTIONS
3.5 Subset Processing
Subset processing is used to place limits on bit devices used by basic instructions and application
instructions in order to increase processing speed.
However, the instruction symbol does not change.
To shorten scans, run instructions under the conditions indicated below.
(1) Conditions which each device must meet for subset processing
(a) When using word data
Device Condition
• Designates a bit device number in a factor of 16
Bit device
Word device • Internal device (File register ZR is not included)
Constants • No limitations
(b) When using double word data
Device Condition
Bit device
Word device • Internal device (File register ZR is not included)
Constants • No limitations
• Only K4 can be designated for digit designation
• Does not conduct index modification
• Designates a bit device number in a factor of 32
• Only K8 can be designated for digit designation
• Does not conduct index modification
MELSEC-Q/QnA
(2) Instructions for which subset processing can be used
Types of Instructions Instruction Symbols
Comparison instructions • =, < >, <, <=, >, >=, D=, D< >, D<, D<=, D>, D>=
Basic arithmetic operations
(addition, subtraction,
multiplication, and division)
Data conversion instructions • BCD, BIN, DBCD, DBIN
Data transfer instruction
Program branch instruction • CJ, SCJ, JMP
Logic operations • WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, DXNR
Rotation instruction • RCL, DRCL, RCR, DRCR, ROL, DROL, ROR, DROR
Shift instructions • SFL, DSFL, SFR, DSFR
Data processing instructions • SUM, SEG
Structured program instructions • FOR, CALL
• +, -,
• B+, B-, B
• MOV, DMOV, CML, DCML, XCH, DXCH
• FMOV, BMOV, EMOV (with QCPU only)
, /, INC, DEC, D+, D-, D , D/, DINC, DDEC
, B/
REMARK
1) : It is only QCPU that can use three devices to conduct subset processing of the logic
operation instructions WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, or DXNR.
D
S
WANDWAND
S2S1
D
Subset processing possible
with Q/QnACPU
Subset processing possible only
with QCPU
3 - 15 3 - 15
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3 CONFIGURATION OF INSTRUCTIONS
3.6 Cautions on Programming (Operation Errors)
Operation errors are returned in the following cases when executing basic instructions and
application instructions with CPU module:
• An error listed on the explanatory page for the individual instruction occurred.
• No intelligent function module or special function module is installed at the designated I/O No.
position when using the buffer register.
• The relevant network does not exist when using a link device.
• No network module is installed at the designated I/O No. when using a link device.
POINT
(1) When a file register setting has been made but no memory card has been
installed, or when no file register setting has been made, no error will be
returned even if an attempt is made to write to the file register.
However, "FFFF
register at which this write operation was attempted.
H
" will be stored if an attempt is made to read from the file
MELSEC-Q/QnA
(1) Device range check
Device range checks for the devices used by basic instructions and application instructions in
CPU module are a s indi ca te d below :
(a) No device range check is made for instructions dealing with fixed-length devices (MOV,
DMOV, etc.).
In cases where the corresponding device range is exceeded, data is written to other
devices.
For example, in a case whe re the da ta regi st e r has be en allo ca te d 12 k poi nts, th e re w ill be
no error even if it exceeds D12287.
DMOV K100 D12287
D12287 and D12288 have been
indicated here, but because
D12288 does not exist, the
contents of some other device
will be destroyed.
Device range checks are not conducted also in cases where index modification is being
performed.
(b) Device range checks are conducted for instructions dealing with variable-length devices
(BMOV, FMOV, and others which designate transfer numbers).
In cases where the corresponding device range has been exceeded, an operation error will
be returned.
For example, in a case wh ere the da ta regi st e r has be en alloca te d 12 k po i nt s, the re will be
an error if it exceeds D12287.
K100 D12287 K2
BMOV
D12287 and D12288 have been
indicated here, but because
D12288 does not exist, an
operation error is returned.
REMARK
1) : See section 3.4 (3) for the internal user device allocation order.
3 - 16 3 - 16
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3 CONFIGURATION OF INSTRUCTIONS
Device range checks are also conducted when index modification is performed.
However, if i nde x modi fi ca ti on ha s been con du ct ed , t he re wi ll be no er ro r re tu rn ed if t he
initial device number exceeds the relevant device range.
K2 Z1MOV
K100 D12285Z1 K2
BMOV
K100 D12287Z1 K2
BMOV
(c) Because all character string data is of variable length, device range checks are performed.
In cases where the corresponding device range has been exceeded, an operation error will
be returned.
For example, in a case whe re the da ta regi st e r has be en allo ca te d 12 k poi nts, th e re w ill be
an error if it exceeds D12287.
MELSEC-Q/QnA
D12287 and D12288 have been indicated here, but because
D12288 does not exist, an operation error is returned.
Because the initial device number is D12289 and that exceeds
the device range, the initial device number is made W0,
the operation is conducted, and no error is returned.
$MOV "ABC" D12287
D12287 and D12288 have been indicated here, but because
D12288 does not exist, an operation error is returned.
Note that an operation error does not occur even if the head device number exceeds the
device range as the result of index modification.
(d) Device range checks are conducted when index modification is performed by direct access
output (DY).
(2) Device data check
Device data checks for the devices used by basic instructions and application instructions in
CPU module are a s indi ca te d below :
(a) When using BIN data
• No error is returned even if the operation results in overflow or underflow.
The carry flag does not go on at such times, either.
(b) When using BCD data
1) Each digi t i s che c k for BCD valu e ( 0 / to 9 ).
An operation error is returned if individual digits are outside the 0 to 9 (A to F) range.
2) No error is returned even if the operation results in overflow or underflow.
The carry flag does not go on at such times, either.
(c) When using floating decimal point data
Operation errors are returned in the following cases:
• When value of floating decimal point data is 0
• When the absolute value of the floating decimal point data is 1.0 × 2
• When absolute value of floating decimal point data is 1.0 × 2
128
-127
or higher
or lower
(d) When using character string data
No data check is conducted.
3 - 17 3 - 17
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3 CONFIGURATION OF INSTRUCTIONS
(3) If internal user device allocation is changed by parameter device allocation, such allocations
are made in the device order indicated below:
If the allocation of the device used is less than 28.75 k words, the area following the device
used will be empty.
Initial address
(fixed)
SM
SD
X
Y
M
L
B
F
SB
V
S
T contact and coi l
ST contact and coil
C contact and coil
Present value of T
Present value of ST
Present value of C
D
W
SW
Empty area
File register
(32 k points)
MELSEC-Q/QnA
Empty area created when device
used is less than 28.75 k words.
REMARK
1) Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the used
CPU module or the QnA CP U P rog r ammi n g Man ual (F u nda men t al s), fo r how to chan ge th e
internal user device allocation.
3 - 18 3 - 18
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3 CONFIGURATION OF INSTRUCTIONS
3.7 Conditions for Execution of Instructions
The following four types of execution conditions exist for the execution of CPU module sequence
instructions, basic instructions, and application instructions:
• Non-conditional execution...................Instructions executed without regard to the ON/OFF status
of the device
Example: LD X0, OUT Y10
• Executed at ON...................................Instructions executed while input condition is ON
Example: MOV instruction, FR OM instru cti on
• Executed at leading edge...................Instructions executed only at the leading edge of the input
condition (when it goes from OFF to ON)
Example: PLS instruction, MOVP instruction
• Executed at trailing edge ....................Instructions executed only at the trailing edge of the input
condition (when it goes from ON to OFF)
Example: PLF instruction
For coil or equivalent basic instructions or application instructions, where the same instruction can
be designated for either execution at ON or leading edge execution, a "P" is added after the
instruction name to specify the condition for execution.
MELSEC-Q/QnA
• Instruction to be executed at ON Instruction name
• Instruction to be executed at leading edge Instruction name + P
Execution at ON and execution at leading edge for the MOV instruction are designated as follow:
MOV K4X0 D0
Execution at ON
MOVP K4X0 D0
Execution at leading edge
3 - 19 3 - 19
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3 CONFIGURATION OF INSTRUCTIONS
3.8 Counting Step Number
The number of steps in CPU module sequence instructions, basic instructions, and application
instructions differs depending on whether indirect setting of the device used is possible or not.
The basic number of steps for basic instructions and application instructions is calculated by
adding the device number and 1.
For example, the "+ instruction" would be calculated as follows:
MELSEC-Q/QnA
+D0 R0
1
+
D0 R0 D10
2 3
1
2
Indicates the number of devices
3 steps
4 steps
(1) Conditions for increasing the number of steps
The number of steps is increased over the number of basic steps in cases where a device is
used that is designated indirectly or for which the number of steps is increased.
(a) When device is designated indirectly
In cases where indirect designation is done by @
, the number of steps is increased
1 step over the number of basic steps.
For example, when a 3-step MOV instruction is designated indirectly (example: MOV K4X0
@D0), one step is added and the instruction becomes 4 steps.
(b) Devices where number of steps increases
Devices Where Number of Steps
Increases
Intelligent function module
device/special function module
device
Link direct devices MOV J3\B20 D0
Serial number access file registers MOV ZR123 D0
32-bit constants DMOV K123 D0
Real number constant
For even numbers:
Character string constant
(number of characters)/2
For odd numbers:
(number of characters + 1)/2
Added Steps Example
MOV U4\G10 D0
1
EMOV E0.1 D0
$MOV "123" D0
(c) In cases where the conditions described in (a) and (b) above overlap, the number of steps
becomes a culmination of the two.
For example, if MOV U1\G10 ZR123
has been designated, 1 step is added for buffer
register designation and 1 step is added for serial number access file register designation,
making a total of 2 step s ad de d.
3 - 20 3 - 20
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3 CONFIGURATION OF INSTRUCTIONS
MELSEC-Q/QnA
3.9 Operation when OUT, SET/RST, or PLS/PLF Instructions Use
the Same Device
The following describes the operation for executing multiple instructions of OUT, SET/RST, or
PLS/PLF that use the same device in one scan.
(1) OUT instructions using the same device
Do not program more than one OUT instruction using the same device in one scan.
If the OUT instructions using the same device are programmed in one scan, the specified
device will turn ON or OFF every time the OUT instruction is executed, depending on the
operation result of the program up to the relevant OUT instruction.
Since turning ON or OFF of the device is determined when each OUT instruction is executed,
the device may tu r n ON and OFF rep ea tedly during one scan.
The following diagram shows an example of a circuit that turns the same internal relay (M0)
with inputs X0 and X1 ON and OFF.
[Circuit]
[Timing Chart]
M0
X0
M0
X1
M0
X0
END
ON
OFF
0
ON
1
OFF
ON
OFF
M0 turns OFF because X1 is OFF.
M0 turns ON because X0 is ON.
M0
X1 X1
M0
END END
M0 remains OFF because X0 is OFF.
X0
M0
M0
M0 turns ON because
X1 is ON.
With the refresh type CPU module, when the output (Y) is specified by the OUT instruction, the
ON/OFF status of the last OUT instruction of the scan will be output.
3 - 21 3 - 21
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3 CONFIGURATION OF INSTRUCTIONS
(2) SET/RST instructions using the same device
(a) The SET instruction turns ON the specified device when the SET command is ON and
does not do anything when the SET command is OFF.
For this reason, when two or more SET instructions use the same device in one scan,
the specified device will be ON if any one of the SET commands is ON.
(b) The RST instruction turns OFF the specified device when the RST command is ON and
does not anything when the RST command is OFF.
For this reason, when two or more RST instructions use the same device in one scan,
the specified device will be OFF if any one of the RST commands is ON.
(c) When the SET instruction and RST instruction using the same device are programmed
in one scan, the SET instruction turns ON the specified device when the SET command
is ON and the RST instruction turns OFF the specified device when the RST command
is ON.
When both the SET and RST commands are OFF, the ON/OFF status of the specified
device will not be changed.
MELSEC-Q/QnA
[Circuit]
[Timing Chart]
M0
X0
M0
SET
X1
RST
M0
X0
SET
M0
X1
END
OFF
0
1
OFF
ON
OFF
RST M0 remains the same (ON)
because X1 is OFF.
M0 turns ON because X0 is ON.
M0
RST
END END
ON
X0
M0 turns OFF
because X1 is ON.
SET M0 remains the same (ON)
because X0 is OFF.
M0SET
X1
M0RST
3 - 22 3 - 22
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3 CONFIGURATION OF INSTRUCTIONS
(3) PLS instructions using the same device
The PLS instruction turns ON the specified device when the PLS command turns ON from
OFF. It turns OFF the specified device at any other time (OFF
OFF).
When two or more PLS instructions using the same device are programmed in one scan, each
PLS instruction turns ON the specified device when the corresponding PLS command turns
ON from OFF and it turns OFF the specified device at any other time.
For this reason, when two or more PLS instructions using the same device are programmed in
one scan, the device that has been turned ON by the PLS command may not turn ON again
throughout the scan.
[Circuit]
X0
M0
PLS
X1
PLS
M0
MELSEC-Q/QnA
OFF, ON ON, and ON
[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0
X1
M0
OFF
OFF
OFF
END
ON
M0 turns ON because X0 turns
ON from OFF.
X0
PLS
M0
X1
M0 turns OFF because
X1 is not turning ON from OFF.
M0
PLS
END
ON
M0 turns OFF because X0 is not turning
ON from OFF. (M0 stays OFF.)
X0
PLS
M0
X1
M0PLS
END
ON
M0 turns ON because X1
turns ON from OFF.
• The X0 and X1 turn ON from OFF at the same time.
END
X0
PLS
M0
X1
M0PLS
END END
X0
M0PLS
X1
M0PLS
OFF
X0
OFF
OFF
ON
ON
M0 turns ON because X1 turns
ON from OFF. (M0 stays ON.)
M0 turns ON because
X0 turns ON from OFF.
M0 turns OFF because X1 is
not turning ON from OFF.
M0 turns OFF because X0
is not turning ON from OFF.
(M0 stays OFF.)
X1
M0
3 - 23 3 - 23
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3 CONFIGURATION OF INSTRUCTIONS
(4) PLF instructions using the same device
The PLF instruction turns ON the specified device when the PLF command turns ON from
OFF. It turns OFF the specified device at any other time (OFF
ON).
When two or more PLF instructions using the same device are programmed in one scan, each
PLF instruction turns OFF the specified device when the corresponding PLF command turns
OFF from ON and it turns OFF the specified device at any other time.
For this reason, when two or more PLF instructions using the same device are programmed in
one scan, the device that has been turned ON by the PLF command may not turn ON again
throughout the scan.
[Circuit]
X0
M0
PLF
X1
PLF
M0
MELSEC-Q/QnA
OFF, OFF ON, and ON
[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON
throughout the scan.)
X0
X1
M0
OFF
OFF
END
OFF
M0 turns ON because X0
turns OFF from ON.
X0
ON
M0 turns OFF because X1 is
not turning OFF from ON.
M0
PLF
X1
END END
ON
M0PLF
M0 turns OFF because X0 is not turning
OFF from ON. (M0 stays OFF.)
X0
M0 turns OFF because X1
turns OFF from ON.
(M0 stays OFF.)
M0PLF
X1
M0PLF
• The X0 and X1 turn OFF from ON at the same time.
END
X0
M0
PLF
X1
M0PLF
END
X0
M0PLF
X1
M0PLF
END
OFF
X0
ON
X1
M0
OFF
OFF
M0 turns ON because
X0 turns OFF from ON.
ON
M0 turns ON because X1 turns
OFF from ON. (M0 stays ON.)
M0 turns OFF because X1
is not turning OFF from ON.
M0 turns OFF because X0 is not turning
OFF from ON.
(M0 stays OFF.)
3 - 24 3 - 24
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4 HOW TO READ INSTRUCTIONS
g
4. HOW TO READ INSTRUCTIONS
The description of instructions that are contained in the following chapters are presented in the
following format.
MELSEC-Q/QnA
1
2
3
4
5
6
8
4
1
Code used to write instruction (instruction symbol).
2
Section number and general category of instructions being discussed.
3
Devices which can be used by the instruction in question are indicated with circle.
The types of devices that can be used are as indicated below:
Special
Function
Module
\G
U
\G Z
U
Index
Register
Zn
Constant
1
Decimal
constants
Hexadecimal
constants
Real number
constant
Character
strin
constant
Other
P, I, J, U,
DX, DY, N,
BL, TR,
BL\S, V
1
Device Type
Usable 4
devices
Internal Dev i ce s
(System, User)
Bit Word
X, Y, M, L,
SM, F, V, B,
SB, FX, FY
2
: Devices which can be set are recorded in the "Constant" and the "O ther" co lumns.
1
: FX and FY can be used only for bit data, and FD only for word data.
2
: Usable with the MELSECNET/H, and MELSECNET/10.
3
T, ST, C,
D, W, SD,
SW, FD,
@
File Register
5
R, ZR
MELSECNET/10(H) 3
Direct J
Bit Word
J
\X
J
\Y
J
\B
J
\SB
\
\W
J
J
\SW
4 - 1 4 - 1
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4 HOW TO READ INSTRUCTIONS
4
MELSEC-Q/QnA
7
9
: Refer to the User's Manual (Functions Explanation, Programming Fundamentals) of the used C PU
4
or QnA Programming Manual for details of each device.
: When T, ST and C are used for other than the instructions below, only word data can be used.
5
(Bit data cannot be used .)
[Instructions that can be used with bit data]
LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, OUT, RST
4
Indicates ladder mode expressions and execution conditions for instructions.
Execution
Condition
Code recorded on
description page
Non-conditional
Execution
No symbol
recorded
Executed while ON
Executed One
Time at ON
Executed while
OFF
Executed One
Time at OFF
4 - 2 4 - 2
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4 HOW TO READ INSTRUCTIONS
5
Discusses the data set for each in st ru ction and the da ta ty pe.
Data Type Meaning
Bit Bit data or first number in bit data
BIN 16 bits BIN 16-bit data or first number in word device
BIN 32 bits BIN 32-bit data or first number in double word device
BCD 4 digits 4-digit BCD data
BCD 8 digits 8-digit BCD data
Real number Floating decimal point data
Character string Character string data
Device name Device name data
6
Indicates the function of the instruction.
7
Indicates conditions under which error is returned, and error number.
See Section 3.6 for errors not included here.
8
Indicates whether the instruction can be used with each CPU module type.
: Can be used
: Can be used with restrictions (function version, software version)
: Cannot be used
9
Indicates both ladder and list for simple program example.
Also indicates the types of individual devices used when the program is executed.
MELSEC-Q/QnA
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5 SEQUENCE INSTRUCTIONS
5. SEQUENCE INSTRUCTIONS
Sequence instructions include instructions for relay control ladders and the like. They are divided
into the following categories:
Instruction M eaning Reference
Contact instruction Operation start, series connection, parallel connection Chapter 5.1
Connection Instruction
Output instruction Bit device output, pulse output, output reversal Chapter 5.3
Shift instruction
Master control instruction Master control Chapter 5.5
Termination instruction Program termination Chapter 5.6
Other instructions
Ladder block connection, creation of pulses from operation
results, store/read operation results
Bit device shift
Program stop, instructions such as no operation which do not fit
in the above categories
MELSEC-Q/QnA
Chapter 5.2
Chapter 5.4
Chapter 5.7
5
5 - 1 5 - 1
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5 SEQUENCE INSTRUCTIONS
Basi
P
CPU
MELSEC-Q/QnA
QCPU
PLC CPU
High Perf ormance
c
5.1 Contact Instructions
5.1.1 Operation start, series connection, parallel connection
(LD, LDI, AND, ANI, OR, OR I)
Usable Devices
Set
Data
S
Internal Devices
(System, User)
Bit Word
File
Register
[Instruction Symbol] [Execution Condition]
LD
LDI
MELSECNET/10(H)
Direct J \
Bit Word
Bit device number/Bit designation of word device ( )
X1/D0.1
X1/D0.1
Special
Function
Module
U \G
Index
Register
Zn
rocess
Constant
S
K, H
QnA Q4AR
Other
DX, BL
5
[Set Data]
[Functions]
X2/D0.2
AND
ANI
OR
X3/D0.3
ORI
X3/D0.3
Set Data Meaning Data Type
S
Devices used as connections Bit
X2/D0.2
LD, LDI
(1) LD is the A contact operation start instruction, and LDI is the B contact operation start
instruction. They read ON/OFF information from the designated device (if a word device bit
has been designated, this becomes the 1/0 status of the designated bit), and use that as an
operation result.
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5 SEQUENCE INSTRUCTIONS
AND, ANI
(1) AND is the A contact series connection instruction, and ANI is the B contact series connection
instruction. They read the ON/OFF data of the designated bit device (if a bit designation has
been made for a word device, the 1/0 status of the designated bit is read), perform an AND
operation on that data and the operation result to that point, and take this value as the
operation result.
(2) There are no restrictions on the use of AND or ANI, but the following applies with a peripheral
device used in the ladder mode:
(a) Write............When AND and ANI are connected in series, a ladder with up to 21 stages
can be generated.
(b) Read ...........When AND and ANI are connected in series, a ladder with up to 24 stages
can be displayed.
If the number exceeds 24 stages, up to 24 will be displayed.
OR, ORI
(1) OR is the A contact single parallel connection instruction, and ORI is the B contact single
parallel connection instruction. They read ON/OFF information from the designated device (if a
word device bit has been designated, this becomes the 1/0 status of the designated bit), and
perform an OR operation with the operation results to that point, and use the resulting value as
the operation result.
MELSEC-Q/QnA
(2) There are no limits on the use of OR or ORI, but the following applies with a peripheral device
used in the ladder mode.
(a) Write................OR and ORI can be used to create connections of up to 23 ladders.
(b) Read................Up to 23 ladders connected with OR or ORI can be displayed.
The 24th or subsequent ladders cannot be displayed properly.
REMARK
Word device bit designations are made in hexadecimal
Bit b11 of D0 would be D0.0B.
See Section 3.2.1 for more information on word device bit designation.
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5 SEQUENCE INSTRUCTIONS
[Operation Errors]
(1) There are no operation errors with LD, LDI, AND, ANI, OR, or ORI instructions.
[Program Example]
(1) A program using LD, AND, OR, and ORI instructions.
[Ladder Mode] [List Mode]
b5b15
b0
D0
(2) A program linking contact points established through the use of ANB and ORB instructions.
1
0
MELSEC-Q/QnA
Steps Instruction Device
···Word
device bit
designa tion
[Ladder Mode] [List Mode]
D6
b4b15
101
b0
b1
0
ORB
ANB
Steps
(3) A parallel program with OUT instruction
[Ladder Mode] [List Mode]
Steps
Instruction
Instruction
Device
···Word
device bit
designa tion
Device
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