Mitsubishi M66281FP Datasheet

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

DESCRIPTION

The M66281FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts the
FIFO (First In First Out) structure consisting of 5120 words x 8 bits
x 2.
Since memory is available to simultaneously output 1 line delay and
2 line delay data, the M66281FP is optimal for the compensation of
data of multiple lines.

FEATURES

• Memory configuration 5120 words x 8 bits x 2 (dynamic memory)

• High speed cycle 25 ns (Min.)

• High speed access 18 ns (Max.)

• Output hold 3 ns (Min.)

• Reading and writing operations can be completely carried out
independently and asynchronously.

• Variable length delay bit

• Input/output TTL direct connection allowable

• Output 3 states

• Q00 – Q07 1 line delay

• Q10 – Q17 2 line delay

APPLICATION

• Digital copying machine,laser beam printer, high speed facsimile,
etc.

FUNCTION

When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are written into memory only for 1 line delay data in
synchronization with a rising edge of write clock input WCK to
perform writing operation. When this is the case, the write address
counter of memory only for 1 line delay data is incremented
simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter of memory only for 1 line delay data stops.

When write reset input WRESB is set to "L", the write address
counter of memory only for 1 line delay data is initialized.
When read enable input REB is set to "L", the contents of memory
only for 1 line delay data are output to data outputs Q00 to Q07
and the contents of memory only for 2 line delay data are output to
Q10 to Q17 in synchronization with a rising edge of read clock
input RCK to perform reading operation.
When this is the case, the read address counters of memory only
for 1 line delay data and memory only for 2 line delay data are
incremented simultaneously.
In addition, data of Q00 to Q07 is written into memory only for 2
line delay data in synchronization with a rising edge of RCK. When
this is the case, the write address counter of memory only for 2 line
delay data is then incremented.
When REB is set to "H", operation for reading data from memory
only for 1 line delay and from memory only for 2 line delay data is
inhibited and the read address counter of each memory stops.
Outputs Q00 to Q07 and Q10 to Q17 are placed in a high
impedance state. In addition, the write address counter of memory
only for 2 line delay data then stops.
When read reset input RRESB is set to "L", the read address
counters of memory only for 1 line delay data as well as the write
address counter and read address counter of memory only for 2
line delay data are then initialized.

PIN CONFIGURATION (TOP VIEW)

NC

38

39

NC

40

RCK

41

RRESB

42

REB

43

GND

44

CC

V

Q00

45

46

Q01

47

Q02

48

NC

1

NC

NC

37

2

Q03

WEB

36

3

Q04

WRESB

35

34

V

33

32

CC

GND

WCK

M66281FP

4

5

6

7

Q05

Q06

Q07

GND

Outline 48P6S-A(QFP)

8
CC

V

D0

31

D1

30

9

Q10

D2

29

10

Q11

D3

28

11

Q12

D4

27

12

Q13

NC

26

13

Q14

14

NC

NC

25

24

NC

23

D5

22

D6

21

D7

20

GND

19

V

CC

18

Q17

17

Q16

16

Q15

15

NC

NC : No connection

1

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

Q10 to Q17

Data outputs

Q0 to Q7

Data outputs

Read enable input

REB
42

Output buffer

47 2 6 9 10 11 125

45 46 43 13 16 17 18

Read reset input

RRESB
41

Read control circuit

Read address counter

Read clock input

RCK

40

Memory Array

5120 words x 8 bits x 2

Memory only for 1 line delay data

Memory only for 2 line delay data

GND20GND33GND

GND
7

43

D0 to D7

Data inputs

Input buffer

31 30 28 27 23 22 2129

36

WEB

Write enable input

Write address counter

Write control circuit

35

WRESB

Write reset input

34

WCK

Write clock input

8

19

32

44

CC

CC

V

VCC

V

VCC

BLOCK DIAGRAM

2

ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted)

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

Symbol

Vcc
VI
VO
Pd
Tstg

Note : Ta=0 – 63˚C. Ta > 63˚C are derated at -9mW/˚C

Supply voltage
Input voltage
Output voltage
Power dispersion
Storage temperature

Parameter Conditions

Value based on the GND pin

Note

Ratings

-0.3 – +4.6

-0.3

– VCC+0.3

-0.3

– VCC+0.3

540

-55

– 150

Unit

V
V
V

mW

°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Vcc Supply voltage 3.152.7
GND
Topr

Supply voltage
Operating temperature

Limits

Min.

Typ.

070

Max.

0

3.6

UnitParameter

V
V

°C

ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol Conditions UnitParameter

IH High-level input voltage

V
VIL
VOH
VOL

IIH

IIL

IOZH
IOZL

CC

I
CI

CO Off-time output capacitance

Low-level input voltage
High-level output voltage
Low-level output voltage

High-level input current

Low-level input current

Off-state high-level output current
Off-state low-level output current

Average supply current during operation
Input capacitance

OH =-4mA

I
I

OL =4mA

I =VCC

V

VI =GND

V

O =VCC

VO =GND
V

I =VCC, GND, output open

tWCK, tRCK = 25ns
f = 1MHz
f = 1MHz

WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7

WEB, WRESB, WCK,
REB, RRESB, RCK,
D0

– D7

VCC-0.4

Limits

Min. Typ. Max.

2.0

0.8

0.4

1.0

-1.0

5.0

-5.0
150

10 pF
15

V
V
V
V

µ

µ

µ
µ

mA

pF

A

A

A
A

3

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol Unit

AC

t
tOH
tOEN
tODIS

Access time
Output hold time
Output enable time
Output disable time

Parameter

TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol Unit

tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH

Note 1: For 1 line access, the following conditions must be satisfied:

2: Perform reset operation after turning on power supply.

Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data set up time for WCK
Input data hold time for WCK
Reset set up time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection set up time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB set up time for WCK
WEB hold time for WCK
WEB non-selection set up time for WCK
WEB non-selection hold time for WCK
REB set up time for RCK
REB hold time for RCK
REB non-selection set up time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
Data hold time (Note 1)

WEB high-level period ≤ 20 ms - 5120 • t
REB high-level period ≤ 20 ms - 5120 • t

WCK - WRESB low-level period

RCK - RRESB low-level period

Parameter

Limits

Min. Typ. Max.

18
3
3
3

Limits

Min. Typ. Max.

25
11
11
25
11
11

7
3
7
3
7
3
7
3
7
3
7
3
7
3

18
18

20

20

ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ms

4