Mitsubishi M66280FP Datasheet

MITSUBISHI <DIGITAL ASSP>

M66280FP

5120 x 8-BIT LINE MEMORY

DESCRIPTION

The M66280FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts
the FIFO (First In First Out) structure consisting of 5120 words x 8
bits.
The M66280FP, performing reading and writing operations at
different cycles independently and asynchronously, is optimal for
buffer memory to be used between equipment of different data
processing speeds.

FEATURES

• Memory configuration 5120 words x 8 bits (dynamic memory)

• High speed cycle 25 ns (Min.)

• High speed access 18 ns (Max.)

• Output hold 3 ns (Min.)

• Reading and writing operations can be completely carried out
independently and asynchronously.

• Variable length delay bit

• Input/output TTL direct connection allowable

• Output 3 states

APPLICATION

• Digital copying machine,laser beam printer, high speed facsimile,
etc.

FUNCTION

When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are read in synchronization with a rising edge of
write lock input WCK to perform writing operation. When this is the
case,the write address counter is also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter stops.
When write reset input WRESB is set to "L", the write address
counter is initialized.
When read enable input REB is set to "L", the contents of memory
are output to data outputs Q0 to Q7 in synchronization with a rising
edge of read clock input RCK to perform reading operation. When
this is the case, the read address counter is incremented
simultaneously.
When REB is set to "H", the reading operation is inhibited and the
read address counter stops. The outputs are placed in a high
impedance state.
When read reset input RRESB is set to "L", the read address
counter is initialized.

PIN CONFIGURATION (TOP VIEW)

DATA OUTPUT

READ ENABLE
INPUT

READ RESET
INPUT

READ CLOCK
INPUT

DATA OUTPUT

Q0

1

Q1

2

Q2

3

Q3

4

REB

RRESB

GND

7

RCK

8

Q4
Q5

Q6
Q7

Outline 24P2Q-A(SSOP)

24

D0
D1

23

D2

22

D3

21

M66280FP

205
196
18
17
169
1510
1411
1312

WEB
WRESB

CC

V
WCK
D4
D5
D6
D7

DATA INPUT

WRITE ENABLE
INPUT

WRITE RESET
INPUT

WRITE CLOCK
INPUT

DATA INPUT

1

MITSUBISHI <DIGITAL ASSP>

M66280FP

5120 x 8-BIT LINE MEMORY

Q0 to Q7

Data outputs

Read enable input

REB
5

Output buffer

1 2 4 9 10 11 123

Read reset input

RRESB
6

Read control circuit

Read address counter

Memory array 5120 x 8 bits

Read clock input

RCK
8

GND
7

D0 to D7

Data inputs

Input buffer

13 14 16 21 22 23 2415

20

WEB

Write enable input

Write address counter

Write control circuit

19

WRESB

Write reset input

17

WCK

Write clock input

18

CC

V

BLOCK DIAGRAM

2

ABSOLUTE MAXIMUM RATINGS (Ta=0 – 70 °C unless otherwise noted)

MITSUBISHI <DIGITAL ASSP>

M66280FP

5120 x 8-BIT LINE MEMORY

Symbol

Vcc
VI
VO
Pd
Tstg

Supply voltage
Input voltage
Output voltage
Power dispersion
Storage temperature

Parameter Conditions

Value based on the GND pin

T=25ns

Ratings

-0.3 – +4.6

-0.3

– VCC+0.3

-0.3

– VCC+0.3

300

-55

– 150

Unit

V
V
V

mW

°C

RECOMMENDED OPERATING CONDITIONS

Symbol

Vcc Supply voltage 3.152.7
GND
Topr

Supply voltage
Operating temperature

Limits

Min.

Typ.

070

Max.

0

3.6

UnitParameter

V
V

°C

ELECTRICAL CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol Conditions UnitParameter

IH High-level input voltage

V
VIL
VOH
VOL

IIH

IIL

IOZH
IOZL

CC

I
CI

CO Off-time output capacitance

Low-level input voltage
High-level output voltage
Low-level output voltage

High-level input current

Low-level input current

Off-state high-level output current
Off-state low-level output current

Average supply current during operation
Input capacitance

OH =-4mA

I
I

OL =4mA

I =VCC

V

VI =GND

V

O =VCC

VO =GND
V

I =VCC, GND, output open

tWCK, tRCK = 25ns
f = 1MHz
f = 1MHz

WEB, WRESB, WCK,
REB, RRESB, RCK,
D0 – D7

WEB, WRESB, WCK,
REB, RRESB, RCK,
D0

– D7

VCC-0.8

Limits

Min. Typ. Max.

2.0

0.8

0.55

1.0

-1.0

5.0

-5.0
70

10 pF
15

V
V
V
V

µ

µ

µ
µ

mA

pF

A

A

A
A

3

MITSUBISHI <DIGITAL ASSP>

M66280FP

5120 x 8-BIT LINE MEMORY

SWITCHING CHARACTERISTICS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol UnitParameter

AC

t
tOH
tOEN
tODIS

Access time
Output hold time
Output enable time
Output disable time

TIMING REQUIREMENTS (Ta=0 – 70 °C, Vcc=2.7 – 3.6V, GND=0V unless otherwise noted)

Symbol UnitParameter

tWCK
tWCKH
tWCKL
tRCK
tRCKH
tRCKL
tDS
tDH
tRESS
tRESH
tNRESS
tNRESH
tWES
tWEH
tNWES
tNWEH
tRES
tREH
tNRES
tNREH
tr, tf
tH

Note 1: For 1 line access, the following conditions must be satisfied:

2: Perform reset operation after turning on power supply.

Write clock (WCK) cycle
Write clock (WCK) "H" pulse width
Write clock (WCK) "L" pulse width
Read clock (RCK) cycle
Read clock (RCK) "H" pulse width
Read clock (RCK) "L" pulse width
Input data set up time for WCK
Input data hold time for WCK
Reset set up time for WCK/RCK
Reset hold time for WCK/RCK
Reset non-selection set up time for WCK/RCK
Reset non-selection hold time for WCK/RCK
WEB set up time for WCK
WEB hold time for WCK
WEB non-selection set up time for WCK
WEB non-selection hold time for WCK
REB set up time for RCK
REB hold time for RCK
REB non-selection set up time for RCK
REB non-selection hold time for RCK
Input pulse up/down time
Data hold time (Note 1)

WEB high-level period ≤ 20 ms - 5120 • t
REB high-level period ≤ 20 ms - 5120 • t

WCK - WRESB low-level period

RCK - RRESB low-level period

Limits

Min. Typ. Max.

3
3
3

Limits

Min. Typ. Max.

25
11
11
25
11
11

7
3
7
3
7
3
7
3
7
3
7
3
7
3

18
18

18

20
20

ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

ms

4