Mitsubishi M66272FP Datasheet
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
DESCRIPTION
The M66272FP is a graphic display-only controller for dot matrix
type STN-LCD which is used widely for OA equipment, PDA,
amusement equipment, etc.
It is capable of displaying six types of LCD by combining the panel
configuration(single or dual scan), LCD display function(binary or
gray scale), LCD display data bus width(4 or 8 bit).
Panel
configuration
Single scan
Dual scan
Binary/
gray scale
Binary
Gray scale
Binary
Gray scale
LCD display data
4bit
8bit
4bit
8bit
4bit
4bit
Displayable LCD size
Equivalent to 640 x 240
Equivalent to 320 x 240
Equivalent to320 x 240x 2 scre ens
Equivalent to320 x 120x 2 scre ens
The M66272FP can support the reflective color type LCD (ECB :
Electrically Controlled Birefringence).
The IC has a built-in 19200-byte VRAM as a display data memory.
All of the
VRAM
addresses are externally opened. Direct
addressing of display data can be performed from MPU, thus
display data processing such as drawing can be efficiently carried
out.
The built-in arbiter circuit(cycle steal system) which gives priority to
display access allows timing-free access from MPU to VRAM,
preventing display screen distortion.
The IC provides has a function for LCD module built-in system by
lessening connect pins between the MPU and the IC.
FEATURES
• Display memory
• Built-in 19200-byte(153.6-Kbit) VRAM(Equivalent to 320 x 240
dots x 2 screens)
• All addresses of built-in VRAM are externally opened.
• Displayable LCD
• Binary display
Monochrome STN-LCD of up to 153600 dots(equivalent to 1/2
VGA)
• 4 gray scale display
Monoc hrome STN -LCD
of up to 76800 dots(equivalent to 1/4
VGA)
Reflective color STN-LCD of up to 76800 dots (equivalent to
1/4 VGA)
• Interface with MPU
• Capability of switching the interface with two-way 8/16-bit MPU
• Provides WAIT output pin(WAIT output when access from MPU
to VRAM is gained)
• Capability of controlling BHE or LWR/HWR at the interface with
a 16-bit MPU
• Interface with LCD
• LCD display data bus is a 4-bit or 8-bit parallel output.
• 4 kinds of control signals: CP, LP, FLM and M
• Display functions
• Graphic display only
• Binary or 4 gray scale display(gray scale palette is used to set
pseudo medium 2 gray scale.)
• Reflective color(ECB) uses a gray scale function.
• Vertical scrolling is allowed within memory range.
• Additional function for LCD module built-in system
• Capability of interfacing with two-way 8/16-bit MPU(16-bit MPU
byte access is not allowed.)
• Access from MPU to VRAM is gained via the I/O register.
• 5V or 3V single power supply
APPLICATION
• PPC/FAX operation panel, display/operation panel of other OA
equipment, multifunction/public telephone
• PDA/electronic notebook/information terminal, portable terminal
• Game, Amusements, kid's computer etc.
PIN CONFIGURATION
(TOP VIEW)
DISPLAY DATA TRANSFERCLOCK
DISPLAY DATA LATCH PULSE
FIRST LINE MARKER SIGNAL
LCD DISPLAY DATA BUS
VSS
CP
LP
FLM
VD<0>
VD<1>
VD<2>
VD<3>
VD<4>
VD<5>
VD<6>
VD<7>
VDD
N.C
N.C
VSS
LCD CONTROL
SIGNAL
LCD ALTERNATING
SIGNAL
VSS
6463626160595857565554535251504948474645444342
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
123456789
VSS
VDD
IOCS
LCDENB
M
LWRRDMCS
HWR
D<15>
D<13>
D<14>
WAIT
WAIT
MPUDATA BUS
VDD
D<8>
D<9>
D<12>
D<10>
D<11>
M66272FP
101112131415161718
VDD
VSS
MPUCLK
RESET
MPUSEL
VSS
SS
V
BHE
D<7>
A<0>
D<6>
A<1>
D<5>
A<2>
MPUDATA BUS
D<4>
D<3>
2021222324
19
A<3>
A<4>
D<2>
A<5>
D<1>
A<6>
D<0>
A<7>
VSS
VDD
41
40
VSS
39
N.C
38
N.C
37
N.C
36
35
34
33
32
31
30
29
28
27
26
25
VSS
VDD
CYCLE STEAL ENABLE
CSE
V
SS
VDD
SWAP BUS SWAP
A<14>
A<13>
A<12>
MPU ADDRESS
A<11>
BUS
A<10>
A<9>
A<8>
VSS
Outline 80P6N-A
CHIPSELECT
READSTROBE
LOW W RITESTROBE
HIGH WRITE STROBE
CONTROLREGISTER
VRAM CHIP SELECT
RESET
MPU CLOCK
8/16MPU SELECT
BUS HIGH ENABLE
MPU ADDRESS BUS
N.C : No Connection
1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI <DIGITAL ASSP>
M66272FP
LCD CONTROLLER with VRAM
BLOCK DIAGRAM 1
MPU ADD RESS
BUS
MPU DATA BUS
CONTROL REGISTER
CHIPSELECT
VRAM CHIP SELECT
HIGH WR ITE STROBE
LOW WRITE
READ STROBE
8/16MPU SELECT
RESET
BUS HIGH ENABLE
BUS SWAP
MPU CLOCK
WAIT
CYCLE STEAL ENABLE
STROBE
A<14:0>
D<15:0>
IOCS
MCS
HWR
LWR
MPUSEL
RESET
BHE
SWAP
MPUCLK
WAIT
CSE
RD
VDD
8 23 34 425263
15
–
22
26
–
32
43
––
50
53
60
2
6
3
4
5
12
11
14
33
9
7
36
ADDRESS
BUFFER
DATA
BUFFER
MPU I/F
CONTROL
CIRCUIT
CLOCK
CONTROL
(BASIC
TIMING
CONTROL)
1 10 13 2425354041 516465
VSS
77
CONTROL
REGISTER
VRAM
19200byte
BUS
ARBITER
TIMIG
CONTROL
(CYCLE
STEAL
CONTROL)
80
GRAY SCALE
PATTERN
TABLE
373839
N.C
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
78 79
61
LCDENB
DISPLAY DATA
66
CP
TRANSFER CLOCK
DISPLAY DATA LATCH
67
LP
PULSE
FIRST LINE MARKER
68
FLM
SIGNAL
62
LCD ALTERNATING
M
SIGNAL
69
–
VD<7:0>
76
LCD CONTROL
SIGNAL
LCD DISPLAY
DATA BUS
BLOCK DIAGRAM 2
MPU ADDRESS
BUS
MPU DATA BUS
CONTROL REGISTER
CHIP SELECT
LOW WRITE STROBE
READ STROBE
MPU CLOCK
2
A<7:1>
D<15:0>
IOCS
LWR
RD
MPUCLK
(When interfacingwiththeLCD module built-insystem andhaving the maximum number ofpins connectedwithMPU)
INPUT FIXED PIN
3 6 11 12 14
–
26
32
33
16
22
43
–––
50
53
60
2
4
5
9
ADDRESS
BUFFER
DATA
BUFFER
MPU I/F
CONTROL
CIRCUIT
CLOCK
CONTROL
(BASIC
TIMING
CONTROL)
OPEN PIN
15
7
VDD
8 23 34 425263
VRAM
ADDRESS
INDEX
REGISTER
DATA
PORT
REGISTER
77
CONTROL
REGISTER
VRAM
19200byte
BUS
ARBITER
TIMIG
CONTROL
1 10 13 2425354041 516465
VSS
61
LCDENB
66
LCD
DISPLAY
TIMING
CONTROL
CIRCUIT
GRAY SCALE
PATTERN
TABLE
LCD
DISPLAY
DATA
CONTROL
CIRCUIT
78 79
373839
80
36
CP
67
LP
FLM
68
62
M
69
–
VD<7:0>
76
LCD CONTROL
SIGNAL
DISPLAYDATA
TRANSFER CLOCK
DISPLAYDATALATCH
PULSE
FIRSTLINEMARKER
SIGNAL
LCD ALTERNATING
SIGNAL
LCD DISPLAY
DATA BUS
N.C
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