Mitsubishi M66244FP Datasheet

The M66244FP is a high-speed digitally programmable pulse width modulator (PWM) which
uses high-performance silicon gate CMOS process technology.Output pulse width is
proportional to a 6-bit DATA input value. Two additional CONTROL inputs determine if the
pulse is placed at the beginning , middle ,or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 72MHz.

FEATURES

• Frequency 45MHz to 72MHz

• 6 bit Resolution

• Center, Leading, Trailing Edge Modulation

• Single 3.3V Operation

• JTAG (IEEE Standard 1149.1Test Port)

PRELIMINARY DATA SHEET

DATA BUS

INPUT

PRELIMINARY DATA SHEET

MITSUBISHI <DIGITAL ASSP>

M66244FP

June 1998 Ver.8.0.0

High Speed Monolithic Pulse Width Modulator

NOTE:This is not final specification. Some parametric limits are subject to change

DESCRIPTION

APPLICATIONS

• Laser Printers
Gray Scale Capability
Resolution Enhancement

• Copiers

• Optical Disk Drives

• Precision Pulse Placement

PIN CONFIGURATION (TOP VIEW)

TEST PIN

(JTAG)

TEST CLOCK INPUT

TEST MODE INPUT

FREQUENCY
RANGE SET INPUT

LINE SIGNAL INPUT

PULSE MODE
CONTROL
INPUT

TCK
TMS

TRSTTEST RESET INPUT

GND
VDD
GND
VDD
GND

VDD
GND

VDD
GND
VDD

FRANGE1
FRANGE2

LS

SEM/DEM

LEM/TEM

1
2
3
4

5
6
7
8

9
10
11
12
13

14
15

16

17

18

36

TDI

35

TDO

34

GND

33

CLK CLOCK INPUT

32

VDD

31

RESET

30

SET

29

VDD

28

GND

27

PWMOUT
VDD

26

GND

25
24
23

22
21
20
19

D0(LSB)
D1
D2
D3
D4
D5(MSB)

TEST DATA INPUT

TEST DATA OUTPUT

RESET INPUT
SET INPUT

TEST PIN

(JTAG)

C 1998 MITSUBISHI ELECTRIC CORPORATION

Outline 36P2R

(1/15)

FRANGE1 and FRANGE2 are set up correspond to
operation frequency range (refer to page 8)

June 1998 Ver.8.0.0

BLOCK DIAGRAM

MITSUBISHI <DIGITAL ASSP>

M66244FP

High Speed Monolithic Pulse Width Modulator

RESET

SET

D0(LSB)

D1
D2
D3

D4

D5(MSB)

LEM/TEM
SEM/DEM

LS

FRANGE2
FRANGE1

CLK

TDI

TRST

31
30

24

23
22

21

20

19
18

17

16

15
14
33

BSR

BSR
BSR
BSR

BSR
BSR

BSR
BSR
BSR
BSR

BSR
BSR
BSR

PULSE
GENERATE
CIRCUIT

PULSE WIDTH
and MODE

CONTROL
CIRCUIT

27

PWM OUT

JTAG Block

36

3

Instruction register

ID register

Bypass register

35

TDO

TMS
TCK

2

1

PIN DESCRIPTION

PIN NAME

D0-D5 Digital Data Bit

CLK
PWM OUT
SEM/DEM
LEM/TEM

SET

RESET

LS

FRANGE1

FRANGE2

TRST

TMS
TCK

TDI

TDO

NAME IN/OUT buffer type

Clock input
PWM output

Control output
pulse mode

Set input
Reset input

Line Signal input

Operation Frequency
range set up

Test Reset input
Test Mode Select input

Test Clock input
Test Data In input
Test Data Out output

TAP Contoroller

normal Input
normal Input

normal output

normal Input

normal Input

schmitt Input (Pull-up 50kΩ)

normal Input
normal Input

schmitt Input (Pull-up 50kΩ)

normal Input (Pull-up 50kΩ)
schmitt Input(Pull-down 50kΩ)
normal Input (Pull-up 50kΩ)

3-sate output

DESCRIPTION
6 bit Digital Data from MPU
Dot Clock input

PWM output

Control pin of output pulse mode (refer to page 3)

When SET is "H", PWM output is "H" (direct set )
When SET is "L", PWM output depend on D<5:0>

When RESET is "L", M66244FP is reset to initial state.

refer to page 10

Test Reset input of JTAG test circuit
Test Mode Select input of JTAG test circuit
Test Clock input of JTAG test circuit
Test Data input of JTAG test circuit
Test Data output of JTAG test circuit

C 1998 MITSUBISHI ELECTRIC CORPORATION

(2/15)

In the third cycle (N+2cycle) , DATA is 0F , SEM/DEM is "L" and LEM/TEM is "X". This means
PWMoutput width is 25% and positioning is center justify.

In the fourth cycle (N+3cycle) , DATA is 2F , SEM/DEM is "H" and LEM/TEM is "L". This
means PWMoutput width is 75% and positioning is left hand justify.

In the fifth cycle (N+4cycle) , DATA is 00 . So the CONTROL value is shown "X" . This means
the value is not important because a 0% pulse will be output for any CONTROL value.

MITSUBISHI <DIGITAL ASSP>

M66244FP

June 1998 Ver.8.0.0

FUNCTION

M66244 can control "H" width and positioning of PWM output by DATA pins (D<5:0> ) and
CONTROL pins (SEM/DEM,LEM/TEM) in each CLK period.
These inputs can be updated on the rising edge of the CLK.
Positioning the width-controlled pulse are begging , middle ,or end of the clock period.
This is accomplished through CONTROL pins (SEM/DEM,LEM/TEM)
Pulse positioning within the clock period is defined by the following CONTROL truth table.

SEM/DEM LEM/TEM Alignment

1 1 Right hand justify
1 0 Left hand justify
0 X Center justify

SEM/DEM : single edge modulation / dual edge modulation
LEM/TEM : leading edge modulation / trailing edge modulation

High Speed Monolithic Pulse Width Modulator

The diagram of page4 illustrates the output of the M66244FP with various DATA(D<5:0>) ,
CONTROL(SEM/DEM, LEM/TEM) inputs and PWM output.
This does not take into account any delays,which will explain later.
The rising edge is delayed from the leading edge of the clock, and the falling edge is delayed
from the center of the clock period.

Top line shows the clock; the second shows DATA inputs ; third shows CONTROL inputs
being updated on the rising edge of clock. The forth line shows the resulting PWM pulse with an
explanation of the second and third lines.

In the first cycle (Ncycle) , DATA is 3F . So the CONTROL value is shown as "X". This
means the value is not important because a 100% pulse will be output for any CONTROL value.

In the second cycle (N+1cycle) , DATA is 1F , SEM/DEM is "H" and LEM/TEM is "H". This
means PWMoutput width is 50% and positioning is right hand justify.

C 1998 MITSUBISHI ELECTRIC CORPORATION

(3/15)

June 1998 Ver.8.0.0

PWM OUTPUT EXAMPLE

MITSUBISHI <DIGITAL ASSP>

M66244FP

High Speed Monolithic Pulse Width Modulator

N N+1

CLK

D<0:5>

SEMDEM

LEM/TEM

PWMOUT

Right hand justify Left hand justify

PWM Pulse linearity (image figure)

N+2

N

100% 50% 25% 75% 0%

N+1 N+2

N+3

2F3F 1F 0F 00 3F

N+4

N+3

Center hand justify

Minimum
"L" Pulse
Width

Minimum
"H" Pulse
Width

CLK

PWMOUT

100

0

(1) In case of next pulse is "H" (2) In case of next pulse is "L"

100

Liner region

Change of linearity

Minimum
"H" Pulse
Width

Liner region

Change of linearity

0

0

"L"

Code (Dec)

"H"

Next Pulse

63

0

"L"

Code (Dec)

Next Pulse

63

"L"

Minimum
"H" Pulse
Width

C 1998 MITSUBISHI ELECTRIC CORPORATION

Minimum
"L" Pulse
Width

Minimum
"H" Pulse
Width

(4/15)

MITSUBISHI <DIGITAL ASSP>

M66244FP

June 1998 Ver.8.0.0

OPERATING TIMING BETWEEN POWER ON TO NORMAL OPERATION

After Power on, it needs following oerations before start normal operation.
(1) Set the value of FRANGE1 and FRANGE2 depends on operation ferequency. (Refer to page 9)

(2) Input CLK same as normal operarion frequency.
(3) Reset operarion using RESET (31pin) and TRST (3pin) .

(reset to initial state of internal logic and BSR)
(4) CLK continue to input during 100msec.

High Speed Monolithic Pulse Width Modulator

Power ON

RESET

tsu(RESET)

TRST

CLK

FRANGE1

FRANGE2

D<5:0>

reset cycle

set up period
of internal circuit

100msec

th(RESET)

Fixed value determined page9

Fixed value determined page9

normal operation
period

n

n+2n+1

SEM/DEM

LEM/TEM

PWMOUT

Note: The reset cycle requires a minimum of two cycles.

C 1998 MITSUBISHI ELECTRIC CORPORATION

(5/15)

n

n

N cycle
output

n+1

n+2n+1

n+2

td(PWM)

n