Mitsubishi M66013FP Datasheet
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI <DIGITAL ASSP>
M66013FP
8-BIT I/O EXPANDER WITH ADDRESS
DESCRIPTION
The M66013FP is a semiconductor IC that is capable of performing
serial-parallel conversion of data. This IC can set addresses.
The microcomputer uses the four signal lines of EN, CLK, DI and
DO to send and receive data.
The IC adopts the two types of operation modes: echo-back mode
and normal mode. In the echo-back mode, data received in serial
can be sent to the sender within the same sequence (*1) as it is.
In the normal mode, restriction is given to the data to be sent to the
sender. However, the normal mode supports the same communication protocol as that of the M66009FP. (*1): one of the higher
order command bits is excluded.
Three bits in the echo-back mode and four bits in the normal mode
are available for addresses. The echo-back mode and the normal
mode have 8 types and 16 types of address, respectively, and any
address can be set.
Receiving serial data from the microcomputer, the M66013 compares address data included in the data with an address entered in
address setting. Only when these addresses match each other, a
specified command provided are to be executed.
For serial input-parallel output operation, low order 8 bits of the
received 16 bit serial data is converted to parallel data to output to
pins D0 to D7. High order 8 bits are handled as address or command bits. Since the writing operation to the data register for
parallel output and the outputting operation of register contents to
pins D0 to D7 are performed with different commands and can be
controlled independently, the register contents must be checked
before output of the specified data to pins D0 to D7.
For parallel input-serial output operation, parallel data of pins D0 to
D7 are outputted to low order 8 bits of the sended 16 bit serial
data. The contents of high order 8 bits of the sended 16 bit serial
data differs in the using operation mode.
In echo mode, the I/O port output format is capable of setting to
either N-ch or P-ch open drain. In normal mode, the I/O port output
format is fixed to P-ch open drain.
FEATURES
•Is capable of providing high speed serial communication at 8
MHz.
•Provides two modes: echo back mode and normal mode.
PIN CONFIGURATION (TOP VIEW)
CLOCK INPUT
SERIAL DATA
INPUT
SERIAL DATA
OUTPUT
DATA ENABLE
INPUT
ADDRESS SET
INPUT
ADDRESS
SET/OUTPUT
SET INPUT
MODE SET INPUT
A3
/PNSET
CLK
DO
EN
A0
A1
A2
MD
DI
GND
1
2
3
4
Outline 20P2N-A (20 pin SOP)
•Is capable of reading serial input data in echo back mode.
(However, 3 bits are available for the address.)
•Is capable of achieving communication protocol of current
M66009FP in the normal mode. (However, 4 bits are available for
the address.)
• Uses different commands in operations for output of data to I/O
port: command for writing data into an output register and
command for output operation to the I/O port.
•Provides an I/O port data read only command.
•Is capable of reading an output register.
•Adopts a decision by majority by reading three types of data when
serial data is received.
•Is capable of setting the I/O port output format to either N-ch or Pch open drain. (In echo mode)
20
VCC
19
18
M66013FP
17
165
156
147
138
129
1110
RESET
RESET
INPUT
D7
D6
D5
PARALLEL
D4
DATA
D3
INPUT/OUTPUT
D2
D1
D0
APPLICATIONS
Inter board communication in VTR, AV and OA equipment, expansion of microcomputer I/O port, etc.
BLOCK DIAGRAM
DATA ENABLE
CLOCK INPUT
SERIAL DATA INPUT
SERIAL DATA
OUTPUT
RESET INPUT
INPUT
EN
CLK
DO
RESET
V
GND
CC
ADDRESS SET INPUT
A0 A1 A2 A3 MD
5 6 7 8 9
4
1
2
DI
SELECTOR
3
19
20
10
COMMAND CONTROL
CIRCUIT
MODE SET INPUT
ACK BIT, OUTPUT SET FLAG
16
SHIFT REGISTER FOR
SERIAL INPUT (16 bits)
16
DATA REGISTER FOR
PARALLEL OUTPUT (16 bits)
SHIFT REGISTER FOR
SERIAL OUTPUT (16 bits)
D0
11
D1
12
D2
13
D3
8
8
14
15
16
17
18
PARALLEL DATA
INPUT/OUTPUT
D4
D5
D6
D7
1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI <DIGITAL ASSP>
M66013FP
8-BIT I/O EXPANDER WITH ADDRESS
BASIC PROTO C O L FOR SEND ING AN D RECEIVIN G DATA
The following diagram shows the basic protocol for sending and
receiving data between the microcomputer and the M66013.
Falling of EN from "H" to "L" starts a series of sequence and rising
of EN from "L" to "H" terminates the sequence. The concrete
operation sequence is as follows:
(1)At a falling edge of EN, 8-bit parallel data of I/O pins D0 to D7
are loaded into the shift register for serial output.
(2) At a rising edge of CLK, DI pin input data is read into the shift
register for serial input and the counter for CLK counts up.
(3)When all address bits are read, a received address is compared
with an address set in the address set pin to start the specified
operation only when these addresses matches each other. The
DO pin is kept in a high impedance status until the address
comparison is complete.
When these addresses do not match, the DO pin keeps the high
impedance status until the next sequence.
EN
1T 2T 3T 4T 5T 6T 7T 8T 9T 10T 11T 12T 13T 14T 15T 16T
In the
normal mode
CLK
DI
DO
A3X A2 A1 A0 C2 C1 C0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
Arbitrary
Address bit Command bit Data bit
"Z" (High impedance status)
Acknowledge bit
(4)When the addresses match each other, the operation for
reading serial data from the DI pin and the operation for output
serial data from the D0 pin in synchronization with a falling edge
of CLK is carried out.
(5) When 16-bit data has been completely sent or received, the
following operations are carried out in synchronization with a
rising edge of EN.
(a)The DO output pin is placed in a high impedance status.
(b)When the CLK counter does not count 16 CLK rising edges,
operation (c) below is skipped and the counter is reset to
wait for the next access.
(c)When the counter value is 16, operation for writing to the
data register for parallel output, operation for output to the
I/O port or operation for setting/resetting the data setting flag
is carried out, and the counter is then reset to wait for the
next address.
ACK
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
Data bit
"Z"
In the echo
back mode
2
CLK
DI
DO
1T 2T 3T 4T 5T 6T 7T 8T 9T 10T 11T 12T 13T 14T 15T 16T
A1A2 A0 C2 C1 C0 X X DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
"Z"
Basic Protocol (The actual protocol differs depending on the command.)
A2 A1 A0 C1 C0 DO7
DO6 DO5 DO4 DO3 DO2 DO1 DO0
"Z"
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