Mitsubishi M66011FP Datasheet

MITSUBISHI 〈DIGITAL ASSP〉

MITSUBISHI 〈DIGITAL ASSP〉

DESCRIPTION

M6601 1 Semiconductor Integrated Circuit is a serial bus con­troller. It converts 2-byte parallel data that arrives from micro­computer into serial and outputs it to serial bus. It also
converts serial data input from serial bus into parallel and out­puts it to microcomputer.
The M66011 is used for the extension of microcomputer I/O
ports and two-way communication with peripheral equipment
connected with serial buses.

FEATURES

• Compatible with general-purpose 8-bit microprocessor bus­ses

• TTL level input (one microcomputer side)

• Interrupt output

• Schmitt input (RESET, CS, SIN)

• Low power dissipation

• Wide operating temperature range (Ta = –20 to 75˚C)

APPLICATION

Microcomputer I/O port extension, etc.

M66011FP

SERIAL BUS CONTROLLER

SERIAL BUS CONTROLLER

PIN CONFIGURATION (TOP VIEW)

RESET INPUT
WRITE INPUT
CHIP SELECT

DATA BUS

RESET

INPUT

1
2

WR

3

CS

4

D0

5

D1

6

D2

7

D3

8

D4

9

D5

10

D6

11

D7

12

GND

Outline 24P2N-B

24
23
22
21

M66011FP

20
19
18
17
16
15
14
13

M66011FP

V

CC

RD

READ INPUT

A0

ADDRESS INPUT

A1
SCLK

SHIFT CLOCK OUTPUT

SOUT

SERIAL DATA OUTPUT

SIN

SERIAL DATA INPUT

OE

OUTPUT ENABLE OUTPUT

INT

INTERRUPT OUTPUT

Xin

CLOCK INPUT

Xout

CLOCK OUTPUT

CC

V

BLOCK DIAGRAM

RESET INPUT

CHIP SELECT INPUT

CLOCK INPUT

CLOCK OUTPUT

RESET

WRITE INPUT

READ INPUT

DATA BUS

CS

WR

RD

Xout

D0
D1
D2
D3
D4
D5
D6
D7

Xin

1
3
2

23

15

14

4
5
6
7
8

9
10
11

Oscillation

circuit

Af

21A122

Timing
control

circuit

8

X8

Shift register for lower

byte serial output (8 bits)

88

Read

register

L

SR

Acknowledge

bit (ACK)

CLK, LOADCLK, LOAD

Shift register for upper

byte serial output (8 bits)

SR

CLK

Shift register for serial

input (9 bits)

8

SHIFT CLOCK OUTPUT

20

SCLK

INTERRUPT OUTPUT

16

INT

17

OE

OUTPUT ENABLE OUTPUT

19

SOUT

SERIAL DATA OUTPUT

U

18

SIN

SERIAL DATA INPUT

1

MITSUBISHI 〈DIGITAL ASSP〉

M66011FP

SERIAL BUS CONTROLLER

FUNCTION

M66011 integrated circuit is a serial bus controller. It is
equipped with two 8-bit shift registers used to convert parallel
input data into serial for output, as well as with one 9-bit shift
register used to convert serial input data into parallel for out­put.
This IC receives and sends 8-bit parallel in communication
with microcomputer. In communication with serial bus, it out­puts 16-bit data and receives 9-bit data.

PIN DESCRIPTIONS

Pin
RESET
CS
WR

RD

D0~D7
SCLK

SOUT
SIN
OE

INT

A0, A1
Xin

Xout
VCC

GND

Name
Reset input
Chip select input
Write input

Read input

Data bus
Shift clock output

Serial date output
Serial data input
Output enable output

Interrupt output

Address input
Clock input

Clock output
Positive supply pin

Grounding pin

Input/Output

Input
Input
Input

Input

Input/Output

Output
Output

Input

Output
Output

Input
Input

Output

––
––

“L” level: M66011 is reset to initial state.
“L” level: M66011 becomes accessible.
“L” level: 8-bit parallel data is input from data bus and written on M66011.
“L” level: Serial-input 8-bit data or internal status data is output in parallel to

data bus.
Bi-directional 8-bit bus buffer . Used for communication with microcomputer

(data write and read).
Outputs clock to serial bus. Active (“H”) status normally.
Outputs serial data to serial bus. Active (“H”) status normally.
Inputs serial data from serial bus.
“L” when serial data communication is executed. Active (“H”) otherwise.
Outputs interrupt command signal to microcomputer when serial data

communication is finished.
Selects register on which data is written during write operation. Designates

data to be read during read operation.
Connected to ceramic resonator, generates M66011 activation clock and

SCLK output clock.
If clock is input from outside, use pin Xin and keep pin Xout open.

Connected positive supply (5V).
Used for grounding (0V).

Serial data input/output uses four signal lines: shift clock out­put SCLK, serial data output SOUT, serial data input SIN and
output enable output OE.
Serial data is output synchronously with shift clock fall edges,
while input of serial data is synchronous with shift clock rise
edges.
Serial communication data consists of one prefixed acknowl­edge bit and 8 data bits.

Functions

2

MITSUBISHI 〈DIGITAL ASSP〉

M66011FP

SERIAL BUS CONTROLLER

OPERATION

1. Write operation
(1)Serial output data setting

The M66011 has two built-in 8-bit shift registers. They are
used to set serial output data.
When the address setting is (A1, A0) = (0, 1), 8-bit data on
data bus is written on the upper byte serial output shift reg­ister (SR

U). When the address setting is (A1, A0) = (0, 0),

Write Operation Basic Functions (Note 1)

CS

Note 1: Figure “0” indicates “L” level, while “1” indicates “H” level.

Note 2:

A1

A0

RD

WR

0

0

0

0

0

1

0

1

1

1

1

1

D7 D6 D5 D4 D3 D2 D1 D0

Don’t care Don’t care

• Lower byte serial output shift register ← Data bus data

0

• Upper byte serial output shift register ← Data bus data

0

• Shift clock divider ratio register

0

• Interrupt output control register Data bus data

“0”: Interrupt output disable
(INT output is fixed to “L”.)
“1”: Interrupt output enable
(INT output shifts from “L” to “H” when serial communication is completed.)

the data is written on the lower byte serial output shift reg­ister (SR

L). In either case, data write starts when WR is on

the “L” level.

(2)Status register setting

When the address setting is (A1, A0) = (1, 1), written data
becomes the setting of status register in M66011. (Refer
to the table below.)

Functions

←

D1

D0

Divider ratio

0

0

0

1

1

0

1

1

1/2
1/4
1/8

1/16

(Note 2)

CS

WR

Data buses
D0~D7

OE

SOUT

SCLK

Write on SR

Write Operation Basic Timing (Serial Output Data Setting)

U Write on SRL

"L" or "H"

D0

U~D7U D0L~D7L

D7U~D0U D7L~D0L

3

MITSUBISHI 〈DIGITAL ASSP〉

M66011FP

SERIAL BUS CONTROLLER

2. Read operation
When a read access arrives, M6601 1 outputs data in par­allel to data bus. The data output at this moment may be
serial input data, or data on internal status resister.
When a read access arrives when the address setting is
(A1, A0) = (1, 0), 8-bits of 9-bit serial input data, excluding

Read Operation Basic Function

CS

A1
0
0

A0

RD

WR

1

0

0

1

1

0

Date bus ← Serial input shift register

1

Data bus ← Status register

1

Read Output Data Details

(1)When (A1, A0) is (1, 0):

Data bus

D7 D6 D5 D4 D3 D2 D1

the acknowledge bit, is output to data bus While RD is “L”.
When a read access arrives when the address setting is
(A1, A0) =(1, 1), interrupt control register, busy flag, serial­input acknowledge bit and clock dividing ratio register are
output to data bus while RD is “L”.

Functions

D0

Serial input data least significant bit (DI0)

Serial input data most significant bit (DI7)

(2)When (A1, A0) is (1, 1):

Data bus

D7 D6 D5 D4 D3 D2 D1 D0

Not specified

CS

RD

Divider ratio

D0

D1

0

0

1

Shift clock dividing ratio

Acknowledge bit

Busy flag (Refer to 3, Serial data input/output operation for details.)
“0”: Access possible
“1”: Serial communication in progress. Write access prohibited.

Interrupt control register data
“0”: Interrupt output disable
“1”: Interrupt output disable

0

0

1

1

1

1/2
1/4
1/8

1/16

Data buses
D0~D7

4

High impedance

VALID

High impedance

Read Operation Timing