Mitsubishi M65863FP Datasheet

Dolby Digital Decoder

M65863FP

Product Note

April 1998

MITSUBISHI ELECTRIC CORPORATION

M65863FP is a single device. The device decodes AC-3 bitstreams into PCM audio. Dolby Digital (AC-3) is a multi-channel audio coding algorithm developed by Dolby Laboratories, Inc.

• Decoding

1) 5.1 ch AC-3 bitstream

2) Dolby Pro Logic*1 encoded 2ch Dolby Digital (AC-3) bitstream

3) Dolby Pro Logic encoded 2ch PCM data

• All input combinations from 1 to 5.1 channels

• Output : mono 5.1 surround

• Sampling rates : 32kHz, 44.1 kHz, 48 kHz and 96 kHz (96 kHz is for linear PCM only)

• Supports a maximum bit rate of 640 kbps at a full service (up to 448 kbps when 32 kHz sampling rates)

• 2 DIR (Digital Audio Interface Receiver)/ADC input interfaces

• Serial input bitstream interface for DEMUX

• PCM output interface

Standard 3-wire DAC output interface (data,clock,LR clock), 16/18/20/24 bit DAC word size

• Supports IEC958 digital audio output for Dolby Digital (AC-3) data stream

• I2C*2 interface and clocked serial (4 line) interface for host microcontroller

• Generates audio test noise

• 2nd DSP I/F (twice higher PCM transfer rate)

• Controllable dynamic range compression

• Programmable center and surround channel delays

• Dialogue level control

• No external memory required (M65863FP doos not have memory space for surround delay)

Dolby, Dolby Digital (AC-3), and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corp. Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA 94111, USA, (415) 5580200, from whom licensing and application information must be obtained.

*2 Phillips Semiconductors, "I2C bus specification",January,1992

Product Note M65863FP

April 1998 Dolby Digital Decoder

Chapter 1

Features

This Audio Decoder for Dolby Digital (AC-3)

Analog

IEC958

ADC

DIR

M65863FP

IEC958

DAC

I C/Clocked serial

Figure 1.1 M65863FP Configuration Diagram (DIR I/F)

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MCU

DSP

Product Note M65863FP

April 1998 Dolby Digital Decoder

Video

Decoder

DEMUX

M65863FP

Audio

IEC958

I C/Clocked serial

MCU

Figure 1.2 M65963FP Configuration Diagram (DEMUX I/F)

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MCU Interface

Processor Clock

DAC/DSP Interface

Digital Audio Interface

Audio Master Clock Interface

Main/Sub Chip Interface

TOP VIEW

(package 68P6S-A)

VDD5V

DIRX

DOTX

GND

VDD3V

ACLK1

ADATA1

ALRCK1

GND

_AMUT

ACLKS

ADATA

ADVLDS

_ADREQ

SYNCRST

RSYCREQ

CCLK

CDATA

ASOUT

VDD5V

BCLK

LRCK

2LRCK

PLL3

PLL2

VDD3V

PLLGND

MCLKSI[1]

MCLKSI[0]

VDD5V

PLL1

PCLK

PVCO

VDD3V

PLLVCC

GND

2BCLK

DEMUX Interface

DIR/ADC Interface

Audio Master Clock Selection

GND

PIN1

PIN68

PIN34

PIN35

Product Note M65863FP

April 1998 Dolby Digital Decoder

Chapter 2

Device Overview

The figure 2.1 show the M65863FP I/O interface.

HSCL/SCK

GND

HSDA/SI

NC/_SS

NC/SO

MCUSEL

VDD5V

GND

DIRSTAT

DECSTAT

CHIPMOD

VDD5V

_RST

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GND

MCLKI

VDD5V

DEMPH

ACLK2

ALRCK2

ADATA2

VDD5V

MCLKO

HMCLKO

Figure 2.1 M65863FP I/O Interface

DOLR

DOCW

GND

DOSS

No.

Product Note M65863FP

April 1998 Dolby Digital Decoder

Chapter 3

Input/Output Pins

Table 3.1 shows input/output pins. "low active" pins are added "_" to tail of pin name (ex. _AERR).

Table 3.1 Input/Output Pins

Pin Name Pins I/O Out Voltage Description

1 VDD5V 7 - Voltage supply 5V (I/O)

2 ASOUT 1 I/O 2mA D5

3 CDATA 1 I/O 2mA D5

4 CCLK 1 I/O 2mA D5 5 RSYCREQ 1 O 2mA D5 Indication of sync word lock condition 6 SYNCRST 1 I D5 Sync world detection start signal 7 ADVLDS 1 I D5 Indication of valid data 8 ADATAS 1 I D5 Data input from DEMUX

9 ACLKS 1 I D5 Clock input from DEMUX 10 VDD3V 3 - Voltage supply 3.3V 11 GND 7 I GND 12 VDD5V 13 _ADREQ 1 O 2mA D5 Data Request for DEMUX 14 _AMUTE 1 I D5 15 DOTX 1 O 2mA D5 Digital audio interface IEC958 output 16 DIRX 1 I D5 Digital audio interface IEC958 input 17 ALRCK1 1 I D5 L/R clock from DIR/ADC 18 ACLK1 1 I D5 Data from DIR 19 ADATA1 1 I D5 Bit clock from DIR/ADC 20 GND 21 VDD5V 22 DEMPH 1 I D5 De-emphasis control 23 ALRCK2 1 I D5 L/R clock from DIR/ADC 24 ACLK2 1 I D5 Bit clock from DIR 25 ADATA2 1 I D5 Data from DIR 26 MCLKI 1 I D5 Audio master clock input 27 GND 28 VDD5V 29 MCLKO 1 I D5 Audio master clock output 30 HMCLKO 1 I D5 Audio master clock output (1/2MCLKI) 31 DOLR 1 O 2mA D5 PCM output for L ch and R ch 32 DOCW 1 O 2mA D5 PCM output for C channel SW ch 33 DOSS 1 O 2mA D5 PCM output for SL ch and SR ch

Indication of audio data output timing (main chip output / sub chip input)

Dynamic range compression data input from sub chip / output to main chip

Dynamic range compression data transfer clock input from sub chip / output to main chip

Mute sound0 (0 : Mute ON, 1 : Mute OFF)

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No.

Product Note M65863FP

April 1998 Dolby Digital Decoder

Pin Name Pins I/O Out Voltage Description

34 GND 35 VDD5V 36 BCLK 1 O 4mA D5 Bit clock for PCM output 37 LRCK 1 O 4mA D5 LR clock for PCM output 38 2LRCK 1 O 2mA D5 LR clock for 2nd DSP 39 2BCLK 1 O 2mA D5 Bit clock for 2nd DSP 40 VDD3V 41 PLLGND 1 - GND for PLL 42 PVCO 1 O P3.3 Processor clock output for crystal

43 PCLK 1 I P3.3 Processor clock input 44 PLL1 1 I/O

45 PLL2 1 I/O 46 PLL3 1 I/O 47 PLLVCC 1 - P3.3 VDD for PLL 48 GND 49 GND 50 GND 51 GND

52 MCLSI[0] 2 I D5

MCLSI[1]

53 54 VDD3V 55 VDD5V 56 _RST 1 I D5 Reset 57 CHIPMOD 1 I D5 Chip mode 58 DECSTAT 1 O 2mA D5 Decode status (Normal : 1, Error : 0) 59 GND 60 DIRSTAT 1 O 2mA D5 (AC-3 : 1, PCM : 0) 61 MCUSEL 1 I D5 MCU I/F Selection (Clocked serial : 0, I2C : 1) 62 VDD5V 63 _NC/SS 1 I D5 64 ADR/SO 1 O 4mA D5 65 HSDA/SI 1 I/O 4mA D5 66 HSCL/SCK 1 I/O 4mA D5 67 GND 68 GND

Selection of audio master clock ([0:1] = 00 : 512fs, 01 : 384fs, 10 : 256fs, 11 : Reserved)

Note) D5 : Degital 5V I/O

P3.3 : PLL oscillation I/O

ACLK1 Bit clock input for DIR/ADC input (Line 1). ADATA1 Data input for DIR/ADC interface (Line 1). Latched at the rising edge of ACLK1. ALRCK1 LR clock input for DIR/ADC interface (Line 1). ACLK2 Bit clock input for DIR/ADC input (Line 2). ADATA2 Data input for DIR/ADC interface (Line 2). Latched at the rising edge of ACLK2. ALRCK2 LR clock input for DIR/ADC interface (Line 2) ACLKS Clock for DEMUX interface.

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Data enable instruction for DEMUX interface. Data is input when this signal is enabled

(0). _ADREQ Used in the data transmission control of DEMUX interface. SYNCRST Synchronization lock cancel signal. M65863FP starts detecting sync word when this

signal is disabled. RSYCREQ SYNCRST request signal which is enabled when M65863FP comes out of

synchronization. _AMUTE Audio mute output signal. Output is muted when this signal is enabled (0). This signal is

valid for both DIR/ADC interface and DEMUX interface.

DOLR PCM output terminal. When control register dspif is 0, L and R channel data are output.

When dspif is 1, L, R, C and SW channel data are output. DOCW PCM output terminal. When control register dspif is 0, C and SW channel data are

output. When dspif is 1, SL and SR channel data are output. DOSS PCM output terminal. When control register dspif is 0, SL and SR channel data are

output. BCLK Bit clock output. LRCK LR clock output. 2BCLK Double-rate bit clock. Used in DSP interface. 2LRCK Double-rate LR clock. Used in DSP interface.

CHIPMOD Specifies the chip mode. Decodes the main service when 0, and decodes the associate

service when 1. Select decoding of main service when it is not necessary to decode dual

streams. CCLK Transmission clock used in data transmission between main and sub chips during dual-

stream decoding. Sub chip becomes the clock master. This is valid only when control

valid only when control register asmix is 1. ASOUT Synchronization signal for dual-stream output. CCLK, CDATA and ASOUT terminals

may be open when dual-stream decoding is not required (when control register asmix is

0).

MCUSEL Selects which of synchronized serial and I2C is to be used as MCU interface.

Synchronized serial is selected when this is 0, and I2C is selected when 1. HSCL/SCK Becomes data transmission clock input in either case of I2C or synchronized serial. HSDA/SI Becomes data input/output terminal in the case of I2C, and data input terminal in the case

of synchronized serial. ADR/SO Becomes chip address selection terminal in the case of I2C, and data output terminal in

the case of synchronized serial. _NC/SS Becomes enable signal in the case of synchronized serial. In the case of I2C, this may be

left open because it is not used.

MCLKI Audio master clock input. MCLSI [0:1] Indicates whether the audio master clock which is input from MCLKI is 512 fs, 384 fs or

256 fs. Only 384 fs or 256 fs can be selected when the sampling frequency is 96kHz. MCLKO Audio master clock output which gives MCLKI as through-output.

Product Note M65863FP

April 1998 Dolby Digital Decoder

ADATAS Data input for DEMUX interface. Latched at the rising edge of ACLKS. _AVLDS

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Enabled when control register demph is 10, turning de-emphasis ON when this is 0, and

de-emphasis OFF when 1. DECSTAT Indicates the current decoding status: 1 during normal decoding and 0 at a time of error. DIRSTAT Indicates the current DIR input stream: 1 in the case of Dolby Digital AC-3 input, 0 in the

case of PCM input.

Product Note M65863FP

April 1998 Dolby Digital Decoder

HMCLKO Audio master clock output which gives MCLKI at 1/2-divided frequency.

DIRX Digital audio interface IEC958 input. DOTX Digital audio interface IEC958 output.

DEMPH

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Dual stream (main effect and Associate service) can be decoded with 2 M65863FP. In the case, the register addresses for a main chip (which decodes main effect) and those for a sub chip (which decodes associate service) are different. In the following sections, only the register address for a main chip will be shown. For a sub chip you should add h'40 to the corresponding register address for a main chip. For a example, the address of the control register "synclock" is h'14 for a main chip and h'54 for a sub chip. In this may, the address range will be following.

Main chip : h'00~h'3f Sub chip : h'40~h'7f

Product Note M65863FP

April 1998 Dolby Digital Decoder

Chapter 4 Registers

Table 4.1 shows the registers overview.

Table 4.1 Registers Overview

Dolby Digital (AC-3) Bitstream Information 13 • Synchronization Information

• Bitstream Information IEC958 Burst Information 1 • IEC958 Burst Information Status 6 • CRC Result

• Synchronization Condition

• Pointer to the input buffer Control 36 • I/O Signals Control

• Decoding Status Control

• Channel delay control

• Dynamic Range Control

• Pro Logic Control

• Calibration Noise Control

• Mute Control

• IEC958 Category code input Test 1 • Monitor of overflow and underflow

• Register Address

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s field indicates nominal bit rate. This code is used along with the sample rate code to determine the

number of bytes per frame.

address h'01

Bitstream Identification (bsid) 5 bits This field contains the version number of the coder syntax. M65863FP only supports 0 to 8.

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April 1998 Dolby Digital Decoder

4.1 Dolby Digital (AC-3) Bitstream Information Registers

Table 4.2 shows Dolby Digital (AC-3) bitstream information registers.

Table 4.2 Dolby Digital (AC-3) Bitstream Information Registers

bit

Address 0 1 2 3 4 5 6 7 R/W

h'00 frmsizecod fscod R h'01 bsmod bsid R h'02 origbs copyrightb lfeon dsurmod acmod R h'03 compre dynrnge dialnorm R h'04 compr R h'05 langcod R h'06 dynrng R h'07 audprodie roomtyp mixlevel R h'08 compr2e dynrng2e dialnorm2 R

h'09 compr2 R h'0A langcod2 R h'0B dynrng2 R h'0C audprodi2e roomtyp2 mixlevel2 R

address h'00

Sample Rate Code (fscod) 2 bits This field indicates sampling rate according to the following table.

fscod Sampling Rate

0 0 48 kHz 0 1 44.1 kHz 1 0 32 kHz 1 1 Reserved

Frame Size Code(frmsizecod) 6 bits Thi

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When acmod is 010, these bits indicate whether or not the program has been encoded in Dolby Surround.

If this bit has a value of 1, the sub-woofer channel is on. If this bit has a value of 0, the sub-woofer channel is off.

Copyright Bit (copyrightb) 1 bit If this bit has a value of 1, the bitstream is protected by copyright. If this bit has a value of 0, the bitstream is not protected by copyright.

Original Bitstream (origbs) 1 bit If this bit has a value of 1, this bitstream is an original bitstream. If this bit has a value of 0, this bitstream is a copy of another bitstream.

Product Note M65863FP

April 1998 Dolby Digital Decoder

Bitstream Mode(bsmod) 3 bits This field indicates the type of service that the bitstream conveys as defined by the following table.

bsmod acmod Type of Service

0 0 0 any Main audio service : complete main (CM) 0 0 1 any Main audio service : music and effects (ME) 0 1 0 any Associated service : visually impaired (VI) 0 1 1 any Associated service : hearing impaired (HI) 1 0 0 any Associated service : dialogue (D) 1 0 1 any Associated service : commentary (C) 1 1 0 any Associated service : emergency (E) 1 1 1 0 0 1 Associated service : voice-over (VO) 1 1 1 0 1 0 ~ 1 1 1 Main audio service : karaoke

address h'02

Audio Coding Mode (acmod) 3 bits This field indicates channel array for audio service.

acmod Audio Coding Mode Channel Array Ordering

0 0 0 1+1 [Ch1,Ch2] 0 0 1 1/0 [C] 0 1 0 2/0 [L,R] 0 1 1 3/0 [L,C,R] 1 0 0 2/1 [L,R,S] 1 0 1 3/1 [L,C,R,S] 1 1 0 2/2 [L,R,SL,SR] 1 1 1 3/2 [L,C,R,SL,SR]

Dolby Surround Mode (dsurmod) 2 bits

dsurmod Indication

0 0 Not indicated 0 1 NOT Dolby Surround encoded 1 0 Dolby Surround encoded 1 1 Reserved

Low Frequency Effects ch On (lfeon) 1 bit

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If this bit is a 1, this bitstream has compression gain word which can use heavy dynamic range compression.

address h'04

Compression Gain Word (compr) 8 bits If compre is a 1, this field indicates scale for the reproduced audio level in order to reproduce a very narrow dynamic range.

address h'05

Language Code (langcod) 8 bits This field indicates the audio service language. If the language code doesn't exist in bitstream, this value indicates h'00.

address h'06

Dynamic Range Gain Word (dynrng) 8 bits If dynrnge is a 1, this field indicates the scale of the reproduced audio level in order to reproduce an ordinary dynamic range.

address h'07

Mixing Level (mixlevel) 5 bits This field contains the acoustic sound pressure level of the dialogue level of the final audio mixing session.

Room Type (roomtyp) 2 bits This field indicates the type of mixing room used for the final audio mixing session.

If this bit is a 1, this bitstream has a dynamic range gain word for ch2 when acmod indicates dual mono mode (acmod=000). Compression Gain Word Exists, Ch2 (compr2e) 1 bit If this bit is a 1,this bitstream has a compression gain word for ch2 when acmod indicates dual mono

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April 1998 Dolby Digital Decoder

address h'03

Dialogue Normalization (dialnorm) 5 bits This field contains how far the average dialogue level is below digital 100%.

Dynamic Range Gain Word Exists (dynrnge) 1 bit If this bit is a 1, this bitstream has dynamic range gain word which can use dynamic range compression.

Heavy dynamic range Compression Code Exists (compre) 1 bit

roomtyp Type of Mixing Room

0 0 Not indicated 0 1 Large room. X curve monitor 1 0 Small room. flat monitor 1 1 Reserved

Audio Production Information Exists (audprodie) 1 bit If this bit is a 1,this bitstream has mixing level data and room type data.

address h'08

Dialogue Normalization, Ch2 (dianorm2) 5 bits This field contains dialogue normalization for ch2 when acmod indicates dual mono mode (acmod=000).

Dynamic Range Gain Word Exists, Ch2 (dynrng2e) 1 bit

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This field indicates dynamic range gain word for ch2 when acmod indicates dual mono mode (acmod=000).

address h'0C

Mixing Level, Ch2 (mixlevel2) 5 bits This field contains mixing level for ch2 when acmod indicates dual mono mode (acmod=000).

Room Type, Ch2 (roomtyp2) 2 bits This field contains room type for ch2 when acmod indicates dual mono mode (acmod=000).

Audio Production Information Exists, Ch2 (audprodi2e) 1 bit This bit indicates audio production information for ch2 when acmod indicates dual mono mode (acmod=000).

Product Note M65863FP

April 1998 Dolby Digital Decoder

mode (acmod=000).

address h'09

Compression Gain Word, Ch2 (compr2) 8 bits This field indicates compression gain word for ch2 when acmod indicates dual mono mode (acmod=000).

address h'0A

Language Code, Ch2 (langcod2) 8 bits This field indicates language code for ch2 when acmod indicates dual mono mode (acmod=000).

address h'0B

Dynamic Range Gain Word , Ch2 (dynrng2) 8 bits

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3rd and 4th bit are reserved,and these values set '0'. If Data Type Code indicates Dolby Digital (AC-3) Data,other 3 bits field indicates same as bsmod code.

Product Note M65863FP

April 1998 Dolby Digital Decoder

4.2 IEC958 Burst Information Registers

IEC958 burst information registers are provided. Table 4.3 shows IEC958 burst information registers.

Table4.3 IEC958 Burst Information Registers

bit

Address 0 1 2 3 4 5 6 7 R/W

h'0D burste 0 ierrflg idtdep R

address h'0D

Data Type Dependent Code (idtdep) 5 bits

idtdep Type of Service 0 0 0 0 0 Main audio service : complete main (CM) 0 0 0 0 1 Main audio service : music and effects (ME) 0 0 0 1 0 Associated service : visually impaired (VI) 0 0 0 1 1 Associated service : hearing impaired (HI) 0 0 1 0 0 Associated service : dialogue (D) 0 0 1 0 1 Associated service : commentary (C) 0 0 1 1 0 Associated service : emergency (E) 0 0 1 1 1 Associated service : voice-over (VO) , or main audio service : karaoke

Error Flag (ierrflg) 1 bit This field indicates error condition for burst data , according to the following table.

ierrflg Status

0 No error 1 Error

Burst Data Exists (burste) 1 bit If this bit is a1, burst data which is assigned "istrnums" in control register exists.

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Product Note M65863FP

April 1998 Dolby Digital Decoder

4.3 Status Registers

The default values are described in the bit fields shown in table 4.4.

Table 4.4 Status Registers

bit

Address 0 1 2 3 4 5 6 7 R/W

h'0E synccon syncdet decode bserr R

1 1 0 0 0 0 0 1

h'0F crc1err crc2err R

0 0 0 0 0 0 0 0 h'10 readpointer R/W h'11 h'12 writepointer R h'13

address h'0E

Error Information (bserr) 1 bit This bit indicates error status.

bserr Description

0 The value of bsid is less than 8 and encode error doesn't exist 1 The value of bsid is more than 9, or encode error exists

Decoding Condition Information (decode) 1 bit

decode Description

0 Regular decode 1 Mute

Synchronous Detection Information (syncdet) 1 bit This bit indicates whether sync word was detected per frame or not.

syncdet Description

0 Sync word was detected 1 Sync word was not detected

Synchronous Lock Information (synccon) 1 bit This bit indicates whether sync word is locked or not.

synccon Description

0 Sync word is locked 1 Sync word is not locked

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Read pointer to the input data buffer. Read/Write operation are allowed when M65863FP is not decoding. Only read operation is allowed when M65863FP is decoding.

address h'12 address h'13

Write Pointer to the Input Data Buffer (writepointer) 16 bits Write pointer to the input data buffer. Only read operation is allowed.

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April 1998 Dolby Digital Decoder

address h'0F

CRC2 Checked Data (crc2err) 2 bits This field indicates the status of CRC error for CRC2.

crc2err Description

0 0 No error 0 1 One error 1 0 More than 2 sequential errors 1 1 Reserved

CRC1 Checked Data (crc1err) 2 bits This field indicates the status of CRC error for CRC1.

crc1err Description

0 0 No error 0 1 One error 1 0 More than 2 sequential errors 1 1 Reserved

address h'10 address h'11

Read Pointer to the Input Data Buffer (readpointer) 16 bits

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dirdatamode

0 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

Product Note M65863FP

April 1998 Dolby Digital Decoder

4.4 Control Registers

The default values are described in the bit fields shown in table 4.5.

Table 4.5 Control Registers

bit

Address 0 1 2 3 4 5 6 7 R/W

h'14 outbitlen dacform synclock R/W

0 0 0 0 0 0 1 0 h'15 dempha dirform dspif dacclkmode R/W

0 0 0 0 0 0 0 0 h'16 lnoise cnoise rnoise srnoise slnoise swnoise noisesel R/W

0 0 0 0 0 0 0 0

h'17 inbitlen pdecmode pfsmode inportsel R/W

0 0 0 0 0 0 0 0 h'18 narwid autobal R/W

0 0 0 0 0 0 0 0

h'19 asmix outchmod stereo compmod R/W

0 1 1 1 0 0 0 0

h'1A

0 0 0 0 0 0 0 0

h'1B hcompsc R/W

dirdatamode syncrsten R/W

h'1C lcompsc R/W

h'1D kcapdef kcapmod karaply R/W

0 0 0 0

h'1E dialevel R/W

h'1F h'20 istrnums copyrightb burstcont muteonoff attlevel R/W

0 0 0 0 0 0 1 0

h'21 catecode R/W

h'22 kcoeffa R/W

h'23 h'24 kcoeffb R/W

h'25 h'26 kcoeffc R/W

h'27 h'28 kcoeffd R/W

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h'29

0 0 0 0 0 0 0 0

Set the number of sync words required for entering the state where synchronization is established. Default value is 2 (b'010). Set the value only once when M65863FP is in the initial state.

Specify the output format. Default value is 000 (MSB first right-justified, when LRCK is 1, Lch output). This field can be changed at any time.

Product Note M65863FP

April 1998 Dolby Digital Decoder

bit

Address 0 1 2 3 4 5 6 7 R/W

h'2A kcoeffe R/W

h'2B h'2C kcoefff R/W

h'2D h'2E kcoeffg R/W

h'2F h'30 kcoeffh R/W

h'31 h'32 kcoeffi R/W

h'33 h'34 kcoeffj R/W

h'35 h'36 kcoeffk R/W

h'37

address h'14

Synchronous Lock Control (synclock) 3 bits

synclock Description

0 0 0 Reserved

0 0 1 ~ 1 1 1 Number of sync words which must be detected before mute is canceled

Output Format (dacform) 3 bits

dacform Description

0 0 0 MSB first right-justified format (when LRCK is 1, Lch output) 0 0 1 LSB first right-justified format (when LRCK is 1, Lch output) 0 1 0 I2S format (when LRCK is 1, Lch output) 0 1 1 Reserved 1 0 0 MSB first right-justified format (when LRCK is 0, Lch output) 1 0 1 LSB first right-justified format (when LRCK is 0, Lch output) 1 1 0 I2S format (when LRCK is 0, Lch output) 1 1 1 Reserved

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Specify the LR clock and bit clock to be used in the DAC/DSP interface. When dacclkmode=0, M65863FP becomes the clock master and divides the audio master clock to generate LR clock (LRCK)/bit clock (BCLK). When dacclkmode=1, M65863FP becomes the slave and uses the DIR/ADC input clocks (ALRCK, ACLK) as the LR clock and bit clock, respectively. In the default setting, M65863FP becomes the clock master. Set this value only once when M65863FP is in the initial status.

Specify the output interface mode. Default value is 0 (DAC interface). This field can be changed at any time.

Specify the format of data input from DIR/ADC. Default value is 000 (MSB first right-justified, when ALRCK is 1, Lch input). This field can be changed at any time.

Product Note M65863FP

April 1998 Dolby Digital Decoder

Number of PCM Output Bits (outbitlen) 2 bits Specify the output bit length. Default value is 00 (16 bits output). This field can be changed at any time.

outbitlen Description

0 0 16 bit 0 1 18 bit 1 0 20 bit 1 1 24 bit

address h'15

DSP/DAC Clock Mode (dacclkmode) 1 bit

dacclkmode Description

0 Clock master 1 Slave

Selection of DSP/DAC Interface (dspif) 1 bit

dspif Description

0 DAC/IF 1 DSP I/F

DIR/ADC Data Input Format (dirform) 3 bits

dirform Description

0 0 0 MSB first right-justified format (when ALRCK is 1, Lch input) 0 0 1 LSB first right-justified format (when ALRCK is 1, Lch input) 0 1 0 I2S format (when ALRCK is 1, Lch input) 0 1 1 Reserved 1 0 0 MSB first right-justified format (when ALRCK is 0, Lch input) 1 0 1 MSB first right-justified format (when ALRCK is 0, Lch input) 1 1 0 I2S first right-justified format (when ALRCK is 0, Lch input) 1 1 1 Reserved

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