Mitsubishi M65762FP Datasheet

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

DESCRIPTION

The M65762FP is a compression and decompression LSI
conforming to the high efficiency encoding system (QM-Coder) in
the International Standard, the JBIG/JPEG (ITU-T Recommenda­tions T.81 and T.82) for coding still images. It also conforms to the
International Standard (ITU-T Recommendation T.85) for facsimile.
The QM-Coder is an information dependent type which is capable
of completely restoring original image data, and is equipped with
the learning function to always optimize parameters according to
the statistical characteristics of images. The QM-Coder is therefore
superior in compression ratio compared with the existing binary
coding system (MH/MR/MMR) and can greatly improve the half
toning image (dithered half toning image) whose compression ratio

is especially poor.

FEATURES

• Completely conforms to the International Standard (ITU-T T.85)
for facsimile.

• Achieves encoding/decoding with the arithmetic coder (QM­Coder) conforming to the recommendation of the International
Standard JBIG/JPEG.

• Is expected to conform to the International Standard for color
facsimile (T.Pallete-colour).

• High speed processing that puts into effect coding and decoding
at 40 million pixels per sec maximum.

• Is possible data-through processing without coding and decodin.

• Can select context

• Provides 10 pixel template model for minimum resolution
conforming to JBIG and can select 2-line or 3-line template
model.

• Built-in typical prediction function

• Capable of coding and decoding by using the typical prediction.

• Since use of the typical prediction does not require the
processing of the line (TP line) which is matched the previous
line's data, is capable of reducing data and processing time.

• Built-in adaptive template (AT) function

• Is capable of setting AT pixels before 127 pixels on the coding

line.

• Since It is possible to change the position of AT pixel in a
specified line, is capable of improving compression
characteristics even when image characteristic is changed in
the middle of the screen.

• Supporting multi-stripe

• When a page consists of more than one stripe, is capable of
repeating encoding/decoding process in stripes.

• Built-in load/store function of line memory Supporting multiple
planes and multi-stripe function

• Is capable of loading image data for reference line from
outside to line memory of the LSI and storing image data from
line memory to outside.

• Number of processing lines

• Is capable of issuing the start of processing (temporary stop
command) several times to encode/decode any lines more
than or equal to 65535 lines.

• Supporting 3-bus interface

• An 8-bit host bus corresponds to the MPU is available to load
and store of context table RAM.

• For input/output of binary image data, is capable of performing

32-bit or 16-bit parallel or serial input/output.

• For input/output of coding data, is capable of selecting 32-

bit/16-bit/8-bit bus to perform DMA transfer of coding data.

• Is capable of making scale-down for coding and scale-up for
decoding.

• Is capable of setting marker code for coding and detecting
marker code for decoding.

• Built-in RAM for 4096 bytes for line memory, built-in context table
RAM and built-in probability estimation table ROM of 113 status

• +5V single power supply

APPLICATION

• OA equipment including facsimile, copier and printer

• Digital and amusement equipment for the purpose of reducing

memory

PIN CONFIGURATION (TOP VIEW)

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

CDAK
CDRD
CDWR
INTR
V

DD

GND
HD0
HD1
HD2
HD3
HD4
V

DD

GND
HD5
HD6
HD7
TEST0
TEST1
V

DD

GND
MCLK
V

DD

GND
RESET
HRD
HWR
HCS
VDD
GND
HA0
HA1
HA2
HA3
TOUT1
TOUT2
VDD

DD

CDRQ

V

CD31

106

105

CD30

104

GND

108

107

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

123456789

CD29

103

CD28

102

GND

101

100

DD

V

CD25

CD27

CD26

CD24

999897969594939291908988878685848382818079787776757473

101112131415161718

CD23

DD

V

GND

M65762FP

M65762FP

CD22

CD21

CD19

CD18

CD20

2021222324252627282930313233343536

19

GND

CD17

CD16

CD15

CD13

VDD

CD14

GND

VDD

CD12

CD11

CD10

CD9

CD8

GND

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

VDD
CD7
CD6
CD5
CD4
GND

DD

V
CD3
CD2
CD1
CD0
GND

DD

V
PXCKO
RVID
SVID
PXCK
PTIM
PRDY
GND
VDD
PDWR
PDRD
PDAK
PDRQ
GND
VDD
PD31
PD30
PD29
GND
VDD
PD28
PD27
PD26

25

PD

GND

PD0

PD1

PD2

PD3

PD4

PD5

GND

VDD

PD6

PD7

PD8

PD9

DD

GND

V

PD10

PD11

PD12

PD13

PD14

DD

PD15

PD16

GND

V

PD17

PD18

PD19

DD

GND

V

PD20

PD21

PD22

PD23

PD24

VDD

GND

Outline144P6Q-A

BLOCK DIAGRAM

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

PD0-31
PDRQ
PDAK*
PDRD*
PDWR*

PRDY*
PTIM*
PXCK*
PXCKO*
SVID*
RVID*

48
49
50
51

54
55
56
59
57
58

Parallel I/F

Image data I/F

Serial I/F

Line memory

Pixel data

Description on Block Functions

(1) Host bus I/F block

This bus is used to set command parameters and load the
status between the MPU and this block. It is 8-bit bus, This
block is also available to load and store of context table RAM
via the host bus.

(2) Code data I/F block

Bus for input/output of coding data. For the bus width, 32­bits, 16-bits or 8-bits can be selected.

Image data can also be transferred (in through mode)
between the Image data I/F and this block via built-in line
memory. FIFO buffer for 16 bytes are provided in the code
data I/F block.

(3) Image data I/F block

The Image data I/F is used for input/output of binary image
data. The 32-/16-bit parallel I/F or serial I/F can be selected.
Selection of the serial I/F transfers data in units of 1 pixel in
synchronization with the line, using the handshake signal
(PRDY*, PTIM*).

Selection of parallel I/F uses an external DMA controller for
DMA transfer (in units of stripe).
The image data I/F provides a function for scale-down of
length and breadth by 1/2 in coding and a function for scale­up of length and breadth by twice in decoding.

Context generation

Typical prediction

108

109

110

111

132

135

134

133

112

129

Context table RAM

Encoding/decoding

Probability Estimation Table ROM

(Asterisk "*" indicates negative logic.)

Code data I/F

Host bus I/F

(5) Typical prediction block

In the typical prediction mode,comparesthe encoding/
decoding process line agree with the immediately preceding
line and generates pseudo-pixel (SLNTP).

(6) Context generator

By using the 10 pixel template of 2-lines or 3-lines.(including
AT pixel) the standard context minimum of JBIG is generated
with the resolution.

(7) Context table RAM block

Corresponds to the 10-bit standard context. This block can
initialize, load and store the context table RAM.

(8) Coding/decoding block

This block performs arithmetic coding and decoding.
It contains a ROM which contains a table capable of
estimating 113 states and is capable of byte stuffing function
('OO' byte insertion/rejection) and is capable of end marker
code control (Marker insertion/detection).

CD0-31
CDRQ

CDAK*
CDRD*
CDWR*

RESET*
HCS*
HA0-3
HWR*

HRD*
HD0-7
INTR
MCLK

(4) Line memory block

4K-byte memory. This block can be set to a maximum of
8192 pixels/line for 3-line template and can be set to a
maximum of 10240 pixels/line for 2-line template. A line is
used for input/output processing of image data to/from
outside and the other lines (2 or 3 lines) are used for
encoding/decoding processing. These two processes can be
independently carried out in synchronization with each line.

The contents of line memory can be loaded or stored via

the image data I/F or coding data I/F.

DESCRIPTION PIN

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

Pin No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

I/O Pin name

Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O

Power supply
Power supply

O

I
I

GND
PD0
PD1
PD2
PD3
PD4
VDD
GND
PD5
PD6
PD7
PD8
PD9
VDD
GND
PD10
PD11
PD12
PD13
PD14
VDD
GND
PD15
PD16
PD17
PD18
PD19
VDD
GND
PD20
PD21
PD22
PD23
PD24
VDD
GND
PD25
PD26
PD27
PD28
VDD
GND
PD29
PD30
PD31
VDD
GND
PDRQ
PDAK
PDRD

Pin No.

51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

I/O

I

Power supply
Power supply

O

I
I

I
O
O

Power supply
Power supply

I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply

Pin name Pin name

PDWR
VDD
GND
PRDY
PTIM
PXCK
SVID
RVID
PXCKO
VDD
GND
CD0
CD1
CD2
CD3
VDD
GND
CD4
CD5
CD6
CD7
VDD
GND
CD8
CD9
CD10
CD11
CD12
VDD
GND
CD13
CD14
CD15
CD16
CD17
VDD
GND
CD18
CD19
CD20
CD21
CD22
VDD
GND

Pin No.

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

I/O

Power supply

I/O
I/O
I/O
I/O

Power supply
Power supply

O

I
I
I

O

Power supply
Power supply

I/O
I/O
I/O
I/O
I/O

Power supply
Power supply

I/O
I/O
I/O

I
I

Power supply
Power supply

I

Power supply
Power supply

I
I
I
I

Power supply
Power supply

I
I
I

I
O
O

Power supply

GND
CD28
CD29
CD30
CD31
VDD
GND
CDRQ
CDAK
CDRD
CDWR
INTR
VDD
GND
HD0
HD1
HD2
HD3
HD4
VDD
GND
HD5
HD6
HD7
TEST0
TEST1
VDD
GND
MCLK
VDD
GND
RESET
HRD
HWR
HCS
VDD
GND
HA0
HA1
HA2
HA3
TOUT1
TOUT2

VDD
CD23
CD24
CD25
CD26
CD27
VDD

(Notes) • Directly connect the input pin having pull-up (see Section 3.3.2 "Pin Function") to Vcc when the pin is not used.

• Directly connect the input pin having pull-down (see Section 3.3.2 "Pin Function" to GND when the pin is not used.

• Connect test input pin TEST 0/1 to GND.

• Leave test output pin TOUT 1/2 open.

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

Descriptionon Pin Functions

I/F Pin name I/O BUF Function

Host bus I/F

Code data I/F

Parallel

RESET*
HCS*
HA0-3
HWR*
HRD*
HD0-7
INTR

CD0-31

CDRQ
CDAK*
CDRD*
CDWR

PD0-31
PDRQ
PDAK*
PDRD*
PDWR*

O

I/O

O

I/O

O

I
I
I
I
I
I

UR8

I

US

I

US

I

US

UR8

I

US

I

US

I

US

H/W reset signal

S

Chip select signal
Address select signal of internal register
Write strobe signal

S

Read strobe signal

S

Input/output data bus signal

R8

Interrupt request signal

4

Coding data input/output bus signal

(CD0-15 is used in 16-bit bus and CD0-7 is used in 8-bit bus.)

DMA request signal for coding data (image data)

4

DMA acknowledge signal for coding data (image data)
Read strobe signal for coding data (image data)
Write strobe signal for coding data (image data)

Parallel image data input/output bus (PD0-15 is used in 16-bit bus.)
DMA request signal for image data

4

DMA acknowledge signal for image data
Read strobe signal for image data
Strobe signal for image data

(Asterisk "*" in signal name indicates negative logic.)

PRDY*
PTIM*

Image data I/F

PXCK*
PXCKO*

Serial

SVID*
RVID*

MCLK
TEST0, 1

Others

VDD
GND

• Input buffer for the input pins ("I" and "IO") are set at the TTL level and the options are as follows.

• Numbers (4, 8) in the BUF column for the output pins ('O' and 'IO') indicate Io (= 4 or 8 mA).

O

I

US

I

US

O

I

U

O

I
I

DS

–
–

(U: Having pull-up resistance, D: Having pull-down resistance, S: Schmitt trigger, R: Through rate control)

1-line input/output start ready signal for image data

4

1-line transfer sector signal for image data
Transfer clock signal for image data
Transfer clock signal for image data (LSI internal loopback output signal of PXCK*)

4

Image data input signal
Image data output signal

4

Master clock input signal
Test input signal 0/1 (Should be connected to GND when used normally.)

Power supply (+5V)

–

Ground

–

Specificatio ns

(1) Package

Plastic QFP 144 pins (20 mm*20 mm)

(2) Power consumption

5V 120mA (600mW)

(3) Maximum clock frequency

40MHz

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

Specifications of Coding Functions

(1) Coding algorithm

• QM-Coder (JBIG standard arithmetic coding system)

(2) Context

a) Template model

• 2- or 3-line of 10 pixel template (See Figure 1.)
(Conforming to the template for JBIG minimum resolution)
(Note) The coding efficiency of the 3-line template is better

than that of 2-line template by several %.

b) Adaptive template (AT)

• It is possible to move up to 127 pixels on the coding line.
(AT position is indicated by MPU.)
(Note) AT is available to improve the coding efficiency for

• Even in the middle of coding/decoding , the position of AT

(3) Typical Prediction

dither image.

line can be changed for a line (ATmove)
(Note) When the position the AT pixel of is changed, the

template model cannot be changed concurrently.

X X

X
X X X
X X

X X X X

X

X X

Figure 1 Template (X, A)

A

A X X

X X

(Upper: 3 lines, Lower: 2 lines)

MAX127

X

MAX127

Figure 2. Adaptive Template (A)

X A

?

A

?

X X X
X X X X
X X

X X X X
X X

?

?

• Agreement with the typical prediction of the minimum
resolution of JBIG.

The psedo-pixel (SLNTP) is generated by the symbol LNTP
which shows whether the coding/decoding process lines
agree with the immediately preceding line. If they agree, the
pesudo-pixel only is coded. This makes it possible to shorten
the time of process and rejection of the code data.

SLNTPy = !(LNTPy LNTPy-1) (where: y indicates a line
No., y = 1 indicates that lines do not match each other, and
initial value LNTP for head line is given with y - 1 = 1)

(4) Coding data format

• The stripe data entity (SDE = stripe coded data with byte
stuffing (PSCD) + end marker (SDNORM/SDRST)).
Performs coding and decoding of one stripe (See Attached
Figure A.1.)

In the case of multi-striped (multi-stripes), can be supported

by activation for each stripe.

(5) Marker code

• Supports the SDE end marker (During coding, the marker
code previously set in the register is outputted. During
decoding, the marker code byte detected by requesting on
interrupt to MPU when the maker is detected is read out of
the register.)

(6) Estimation of coding/decoding speed

Figure 3 compares the estimation of coding/decoding speed
between the M65762FP and the existing product type
(M65760/1FP). Polygonal lines in the diagram are processing
speeds of images theoretically generated assuming the
unmatched estimation ratio as a parameter. In addition, ,

indicate processing speeds of real image (without TP

function).

As shown in this diagram, the M65762FP has been largely

improved in the processing speed compared with existing
product types. If the compression ratio is reduced, the
reduction ratio of processing speed is moderated.

When a theoretical image is used to compare processing
speeds in the worst case, the processing speed of existing
product type is about 9.4M pixels/sec (1/compression ratio is
about 1), while the processing speed of the M65762FP is
about 27.5M pixels/sec (1/compression ratio 0.9) for coding
and is about 31.2M pixels/sec (1/compression ratio 0.75) for
decoding.

+

40

g

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

35

30

25

Baud rate and dither images

Average of test charts 1 to 8 of former CCITT

20

15

Processing speed (M pixels/sec.)

10

(Legend)

5

Decoding of M65762FP
Coding of M65762FP

Coding/decoding of existing

0

product type

0.25

0

Decoding of M65762FP

Coding of
M65762FP

Cafeteria and dither images

Coding/decoding of
existing product
type (M65760/1FP)

Theoretical

ima

e

0.5

Actual
image

Baud rate, error diffusion image

Cafeteria, error diffusion image

0.75

1.0

1.2

1/compression ratio

Figure 3 Estimated Processing Speed

Register Configuration

g

1. List of Registers
Table 1 List of Registers

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

Address

1 Parameter setting W/R

2 Command W

2 Status R

Register name

0 System setting W/R

R/W

Content

- LSI H/W reset

- Selects bit width of code data bus (32 bits/16 bits/8 bits).

- Selects coding (image) data byte swap on code data bus.

- Selects coding (image) data bit swap on code data bus.

- Selects image data bit swap on image data bus.

- Selects image data I/F (parallel I/F and serial I/F).

- Selects bit width of image data bus (32 bits/16 bits).

- Template selection (3-line template/2-line template).

- Sets up the AT pixel position (127 max).
(When set to 0, selects non-AT (default position).)

- Context table RAM initializing processing command

- Start/stop command
(Coding/decoding, image data through, load/store of the line memory)

- Start/stop command of load/store of context table RAM

- Selects temporary stop/termination end mode.

- Processing status (in process/end of process)

- Ready for reading/writing coding (image) data on code data bus

- Detects marker code (SDNORM, SDRST, ABORT, etc.).

- Interrupt request status

- SC counter overflow error

- Processing mode (temporary stop/end of termination)

Interrupt enable

3

setting
Setting number of

4, 5

pixels
Setting number of

6, 7

lines
Number of

8, 9

processin

Load/store bufferA

Operation mode

B

setting

C

Marker code setting

C Marker code reading R

Scale-up/

D

scale-down setting

lines

W/R

W/R

W/R

R

W/R

W/R

W

W/R

- Interrupt enable setting corresponding to each bit position of status register

- Indicates pause/restart with marker code detected (at time of decoding)

- Sets the number of pixels per line.

(a maximum of 10240 pixels with 2-line template selected)

- Sets the number of lines to be coded/decoded (1 line or more, a maximum of 65535
lines)

- Number of setting the coded/decoded lines (a maximum of 65535 lines)

- Buffer register that loads/stores context table RAM data from the MPU.

(RAM address is automatically incremented each time data is written/read.)

- Sets the operation mode.
(Coding/decoding, image data through, and load/store of line memory)

- Selects read-through of head coding data in decoding (0 ~ 3 bytes).

- Selects the typical prediction function.

- Selects prohibition of line memory initialization.

- Sets the terminal marker code in encoding (SDNORM/SDRST)

- Reads a marker code in decoding.

(SDNORM, SDRST, ABORT, others)

- Scale down in coding (1/2 scale-down of horizontal and vertical, horizontal OR
processing)

- Scale-up at time of decoding (scale-up of horizontal and vertical by twice)

2. Description on Register

(

(1) System setting register (W/R)
(Address: 0)

SYS_REG: PB PI BX BS DS CB HR

d0 (HR): H/W reset (0: Active status, 1: Reset status)

d1-2 (CB): Selects the bit width of code data bus (d2 = 0, d1 = 0:

d7(MSB)

To reset H/W, set this bit to 1 then to 0. The entire LSI
including register group and line memory is initialized
by writing in this reset. However, context table RAM is
not initialized.

8-bit bus (CD0-7), d2 = 0, d1 = 1: 16-bit bus (CD0-15),
d2 = 1, d1 = 0: 32-bit bus (CD0-31))
(Note1)Prohibition of setting for d2 = 1, d1 = 1
(Note2)For encoding in 16-/32-bit bus, the last

encoding data is output followed by bit byte of
'00' (3 bytes maximum) for word alignment of
encoding data at the end.

d0(LSB)

MITSUBISHI SEMICONDUCTOR (LSI)

M65762FP

QM-CODER

d4 (BS): Selection of data bit swap of code data bus (0: MSB

first, 1: LSB first) See Table 2.

d5 (BX): Selection of data byte swap of code data bus (0: low

order byte first, 1: high order byte first) See Table 2.
(Note) BX is effective only when the host bus selects

16-bit/32-bit bus.

d6 (PI): Selection of image data input/output I/F (0: serial I/F, 1:

parallel IF)

d7 (PB): Selection of bit width of image data bus (0: 32-bit bus

(PD0-31), 1: 16-bit bus (PD0-15) See Table 3.

Note) PB and DS are effective only when PI = 1.

d3 (DS): Selects data bit swap of image data bus (0: MSB first, 1:

LSB first) See Table 3.

Table 2 Line up of Coded Data/Image Data in Code Data Bus

Bus width (CB)

d2 d1 d5 d4

01

(32-bits)

01

(16-bits)

00

(8-bits)

Note) b0 is image data, given in time series, on the left side of the first encoding data/screen. b31 is image data, given in time series, on the right side of the last encoding data/screen.

Swap (BX, BS)

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

–

0

–

1

CD31 • • CD24 CD23 • • CD16 CD15 • • CD8 CD7 • • CD0

b24 • • b31
b31 • • b24
b0 • • b7
b7 • • b0

–
–
–
–

–
–

Order of data in code data bus (CD)

b16 • • b23
b23 • • b16
b8 • • b15
b15 • • b8

–
–
–
–

–
–

b8 • • b15
b15 • • b8
b16 • • b23
b23 • • b16

b8 • • b15
b15 • • b8
b0 • • b7
b7 • • b0

–
–

b0 • • b7
b7 • • b0
b24 • • b31
b31 • • b24

b0 • • b7
b7 • • b0
b8 • • b15
b15 • • b8

b0 • • b7
b7 • • b0

Table 3 Order of Image Data on Image Data Parallel Bus

Bit width

PB=0

PB=1

p0 is image data on the left side of the screen. p31 is image data on the right side of the screen.

(2) Parameter setting register (W/R)

Swap

DS=0
DS=1

DS=0
DS=1

PD31 • • • • PD16

p0 • • • • p15

p31 • • • • p16

–

PD15 • • • • PD0

p16 • • • • p31
p15 • • • • p0

p0 • • • • p15
p15 • • • • p0

(Address: 1)

PARA_REG :

d7 d4

d0-4 (AT<0>-AT<4>): Low order 5-bits of AT pixel position (See

Figure 2.)

d5 (TM): Selection of template (0: 3-line template, 1:

2-line template)

d6-7 (AT<5>-AT<6>): High-order 2-bits of AT pixel position

(6th/7th bit)

(Example) 3-line template, AT = 4

2-line template, AT = 48

(Note) AT pixel position is set (0 to 127) with AT <6:0>.
At the default position (AT pixel is not used), set AT = 0.
The 2-line template, prohibits AT = 1 to 4 from being set. The 3­line template prohibits AT = 1 to 2 from being set.

d5d6

AT TM AT

d7 d4

0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0

d0

d0