Mitsubishi M65675FP, M65676FP Datasheet

MITSUBISHI ICs (TV)

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

DESCRIPTION

The M65675FP/M65676FP is a NTSC/PAL encoder LSI that converts CCIR 601 or CCIR 656 (SMPTE125M) format digital video signals into analog component and composite video signals in accordance with either NTSC or B/G-PAL standards. The 10-bit digital luma (Y) and analog chroma (U/V) signals are available in Y/U/V output mode. In addition it performs the closed caption capability (TV line 21/

NTSC), CGMS line 23/PAL), Macrovision copy protection

encoding (TV line 20/NTSC), WSS

function (Rev. 7.01) and on-screen display. The OSD function can be directly accessed by the OSD microprocessor via built-in interface.

FEATURES

•

NTSC and B/G-PAL Outputs

•

Component Y/C (S-Video), Composite (CVBS) or Y Outputs

•

Supporting CCIR601, CCIR656 (SMPTE125M) Format Data

•

Processing Y/Cb/Cr and Y/U/V Pixel Data

•

27MHz Clock Frequency (Two-times Oversampling)

•

Macrovision Copy Protection

•

Close Captioning Supporting (line 21/NTSC) (ODD Parity Operation)

•

V-Code Supporting (line 21/NTSC) (ODD Parity Operation)

•

CGMS

Data Insertion (line 20/NTSC) (CRCC Error Correction

Code Operation)

WSS

Supporting (line23/PAL)

OSD Insertion Interface and 3¥8¥4-bit Color Look-up Table

Processing (Revision 7.01)

encoding (TV

/U/V

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

•

Controllable Picture Processing Functions Color, TINT and Brightness

•

Built-in Analog Functions Y/C Mixing

Two 10-bit DACs Three 6-dB Ampliﬁers

Built-in 27 MHz System Clock Generator

•

Single 3.3V Supply

•

64-pin PQFP Package

•

Note *1: Copy Generation Management System-A (IEC1880)

*2: Wide Screen Signaling (ETS300 294) *3: This applies to M65675FP only.

This device is protected by U.S. patent number 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intend for home and other limited pay-par-view use only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.

*4: Y output is 10bit digital signal.

APPLICATION

DVD Players, Digital Satellite & Cable System (Set Top Boxes/ IRDs), Video CD, Multimedia Terminals, Video Games, Digital VCR & Camcoder etc.

PIN CONFIGURATION (TOP VIEW)

Yref

Ycomp

49 50

N.C.

DD1

DVSS1

DVSS2

DD2

53 54 55 56

57 58 59

60 61 62 63

SS2

X out

X in

PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0

Cref

DAY

PXCLK

DVASEL

SS1

AVDD1

454443

DAC

C in

Ccomp

N.C

403938

M65675FP M65676FP

VD8

VD7

VD6

VD9

Outline 64P6N-A

Y in

DD2

101112

VD5

VD4

VD3

CVBS

SS2

363534

131415

VD2

VD1

N.C.

VD0

SS2

32 31 30 29 28

27 26 25 24

23 22 21 20 19 18 17

N.C. N.C. DV

DD1

TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK

SS1

DVDD1 DVDD2

NC : NO CONNECTION

MITSUBISHI ICs (TV)

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

BLOCK DIAGRAM

AVSS2

AVDD2

Yin

Cin

LPF

BPF

DAC

DAY AVSS1 AVDD1

Y ref C ref

Clamp

bias

DAC

10bit

Interpolation

6dB

Y/U

filter

6dB

10bit

DAC

C/V

6dB

MIX

Y/C

Chroma

Encoder

CVBS

Analog

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

TEST RESET

DVSS2(X2) DVSS1(X2)

DD2(X2)

DD1(X2)

OSD2 OSD1 OSD0

OSDCK

Encoder

Closed Caption

Y/U/V

Y/Cb/Cr

Video signal generator

OSD

Interface

Input

Interface

Manager

CGMS/WSS

adder

C-sync

Burst

adder

OSD

controller

control

Blanking

Demulti Plexer

Manager

Video Anti Copy

signal adder (1)

Video Anti Copy

OSD mixer

Cb/Cr

Interpolation

filter

signal adder (2)

generator

sub carrier

Converter

Cb/Cr to U/V

Cb/U

Cr/V

8-color

Look-up

table RAM

Cb/U

Cr/V

CLK

generator

Oscillator

∗1

signal

generator

Anti Copy

Processing

control

pulse

Timing

Sync Processing

HD/VD

generator

C-sync

generator

∗1: This function bloc is M65675FP only

SCL

slave

receiver

serial interface

Commands

SDA ACK

PXD [7:0]

VD [9:0]

PXCLK

Xout

Xin

/Slave

Muster

± 15 µ

MITSUBISHI ICs (TV)

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter

stg

RECOMMENDED OPERATING CONDITION

DC supply voltage -0.3 4.5 V Digital input voltage -0.3 Digital output voltage -0.3 Operating temperature -20 +25 +75 ° C Storage temperature -40 +125 ° C

(Ta=25 ∞ C, DV

Symbol Parameter Test conditions

Supply

DDX

DV AV DI AI

DDX DD DD

Digital supply voltage 3.0 3.3 3.6 V Analog supply voltage 3.15 3.3 3.45 V Digital current consumption 0 45 mA Analog current consumption 0 55 mA

Digital input

Input voltage Input leakage current DV

Input capacitance f=1MHz, V

DV DV

Digital output

C bus

Output voltage DV Output capacitance f=1MHz, V

Output current DV

Output leakage current (off) DV D/A converter Res Resolution 10 Bit INL Integral non-linearity error Rref=2.2k Ω , R DNL Differential non-linearity error Rref=2.2k Ω , R Vf

SMAX

Maximum output amplitude 000 to 3FF 1.5 V 6-dB ampliﬁer R G G DR DR

bias V_YC V_CV

in out

Bias resistor 7.5 10 11.5 k Ω

Voltage gain (Y/C) 5.50 6.00 6.50 dB

Voltage gain (CVBS) 5.10 6.00 6.85 dB

Input dynamic range 0.8 V

Output dynamic range 1.6 V

Limits

Min. Typ. Max.

V V

=AV

+0.3 +0.3

=3.3V, DV

Unit

V V

=AV

=0V, unless otherwise noted)

Limits

Min. Typ. Max.

=3.0V 0 0.8 V

=3.6V 2.5 3.6 V

DD DD

=3.0V , V

=0V or V

=0V 7 15 pF

=3.3V, | IO | <1 µ A

=0V 7 15 pF

=3.0V , V

=3.6V , V

=0V or V

L L

=3.6V

3.25 V

=0.4V 4.0 mA

=3.6V

=300 Ω± =300 Ω±

0.05 V

± 15 µ A

2.0 LSB

1.0 LSB

Unit

P-P

P-P P-P

MITSUBISHI ICs (TV)

◊

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

M65675FP/M65676FP System Architecture

Block Diagram of M65675FP/M65676FP

The M65675FP/M65676FP block diagram is shown in Fig. 3.1. The M65675FP/M65676FP consists of 4 functional blocks: a video signal processing, a synchronization control, a serial interface and an analog signal processing blocks. The video signal processing block includes an input interface, OSD interface, YCbCr to YUV converter/encoder and copy protection signal generator (This function block is M65675FP only). A sync generator and timing pulse generator are in the synchronization control block. The serial interface block has an I slave register and command register. The analog signal processing block includes two 10-bit DACs, a Y/C mixing circuit and three 6-dB ampliﬁers.

General Description of Each Functional Blocks

Video Signal Processing Block

The Y/Cb/Cr or Y/U/V are converted into digital Y/C signals in accordance with either NTSC and B/G-PAL standards. In addition the closed caption, CGMS/WSS and copy protection signals will be inserted in that digital Y/C signals.

[Input Interface] The multiplexed Y/Cb/Cr or Y/U/V pixel data are divided by the individual components, then the Cb/Cr or U/V data rate is increased from 6.75 Mbps up to 13.5Mbps.

[OSD Interface] The digital video signal in the CLT (Color Look-up Table) is overlaid with OSD data according to the external instructions.

[Y/Cb/Cr to Y/U/V Converter] It converts the Y/Cb/Cr into Y/U/V, and then c-sync and burst signals are inserted on the converted Y and U/V signals, respectively. However, the burst insertion is not done in the Y/U/V output mode.

[Encoder] The closed caption, CGMS/WSS and copy protection signals are inserted into the Y signal and C signal is modulated into the appropriate standards. After that processing, both Y and C signals will be oversampled.

[Copy Protection Processing] According to the copy protection setting, VBI pulse (AGC and backporch pulse) and Advanced Split Burst are generated in accordance with Macrovision Rev 7.01.

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

Synchronization Control Block C-sync and several timing control signals for internal use are generated with 3 different H/V sync signals as reference. 1st reference H/V sync signal is external input, 2nd is internally generated one and 3rd is decoded one in digital blanking code (SAV, EAV etc.)

Serial Interface Block The registers can be read and written according to I The data transport to the internal blocks is performed on the trailing edge of V-sync, except for some set-up registers.

◊ Analog Signal Processing Block The output of the 10-bit DAC is 1.2VP-P at the sampling frequency of 27.0MHz. The inputs of Yin and Cin are set up to 0.6VP-P (Typ) and the component outputs will be ampliﬁed by 6-dB up to 1.2VP-P (Typ). The analog composite signal from the mixing circuit is also ampliﬁed up to 1.2VP-P (Typ)

Functional Description Video Signal processing Input Interface Input Format

The video encoder accepts 16/8-bit CCIR601 and CCIR656 format. The speciﬁcations of these format are described as follows; ◊ 16-bit CCIR601 Interface

PXCLK=13.5MHz

Y=8-bit/13.5Mbps

16-235 straight-binary-data

Cb/Cr=8-bit/13.5 Mbps (Cb=Cr=8-bit/6.75 Mbps)

16-240 128 offset-binary-data

Active video area525/60=720-pixel¥480 line/frame

(22/284 line-263/525 line)

625/50=720-pixel¥576 line/frame

(23/336 line-310/623 line)

◊ 8-bit CCIR601 Interface

PXCLK=27.0MHz Cb/Y/Cr=8-bit/27.0Mbps

Y= 8-bit/13.5Mbps

16-235 straight-binary-data

Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75Mbps)

16-240 128 offset-binary-data

Active video area525/60=720-pixel¥480 line/frame

(22/284 line-263/525 line)

625/50=720-pixel¥576 line/frame

(23/336 line-310/623 line)

C bus format.

MITSUBISHI ICs (TV)

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

◊ CCIR656 Interface

PXCLK=27.0MHz Cb/Y/Cr=8-bit/27.0Mbps

Y=8-bit/27.0Mbps

16-235 straight-binary-data

Cb/Cr=8-bit/13.5Mbps (Cb=Cr=8-bit/6.75 Mbps)

16-240 128 offset-binary-data

Active video area525/60=720-pixel¥480 line/frame

(22/284 line-263/525 line)

625/50=720-pixel¥576 line/frame

(23/336 line-310/623 line)

Vertical blanking Interval 525/60=1/264-9/272

Digital ﬁeld 1 (ODD)=4-265 Digital ﬁeld 2 (EVEN)=266-3

625/50=624/311-22/335

Digital ﬁeld 1 (ODD)=1-312 Digital ﬁeld 2 (EVEN)=313-625

Horizontal blanking Interval525/60=276CLK (0H=32CLK)

EAV=1-4CLK/SAV=273-276CLK

625/50=288CLK (0H=24CLK)

EAV=1-4CLK/SAV=285-288CLK

The input data (X), except the active data in the above support format, are clipped as shown below; ◊ 8/16-bit CCIR601 Interface

Y : X£16 Æ 16

X≥235Æ235 (Whole period) Cb/Cr : X£16 Æ 16 (U/V) X≥240Æ240 (Whole period)

◊ CCIR656 Interface

Y : X£16 Æ 16

X≥235Æ235 (Active video period)

X Æ 16 (Blanking period) Cb/Cr : X£16 Æ 16 (U/V) X≥240Æ240 (Active video period)

X Æ 128 (Blanking period)

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

OSD Interface Color Look-up Table (CLT)

The built-in CLT can be equivalent to 4bit¥8 colors, so that the reproduced colors are 8/4096. The setting ranges and the signal levels in the overlaying of Y, Cb and Cr each are shown below;

Y :Setting range=1 (h) to F (h) : straight-binary data

Signal Level=10 (h) to F0 (h) : straight-binary data

Cb/Cr : Setting range=1 (h) to F (h) : 8 offset-binary data

Signal level=10 (h) to F0 (h) : 128 offset-binary data

OSD Control

Overlaying the appointed data on the video signal from MPEG is possible by inputting the address data to the CLT in synchronization with OSDCLK, H-sync and V-sync. The overlaying is prohibited in case CLT address is set to 7 (h). The OSD control speciﬁcations are shown below; ◊ OSDCLK= selectable 13.5MHz or 6.75MHz

selectable continuous or discontinuous (pausing during H-sync) clock

◊ Color Signal Blend=Maximum 3 colors are allowed to be set.

The data of CLT addresses 0 (h) to 2 (h) are dedicated to color blending. The blend ratio is ﬁxed by 1:1 and blend mode is selectable between Y/Cmix and Ymix mode.

Y/Cb/Cr to Y/U/V Converter C-sync Addition

The sync signal, set up in the register, is added to Y signal according to C-sync timing generated from H-sync/V-sync. Typical sync height, set up in the register, is calculated by the following equations; Sync level={(White peak input level-16)¥2.5¥Xsync (IRE)}/100 In the case ofNTSC: {(235-16)¥2.5¥40}/100=219 (DBH)

PAL : {(235-16)¥2.5¥43}/100=235.4 (EBH)

Note: Xsync=Output sync level (IRE)

Digital Multiplexing

The input pixel data described in 4.1.1.1 are de-multiplexed, then Y, Cb,Cr and Y, U, V signals will be converted to each 8-bit parallel data. After the above conversion, 6.75Mbps Cb, Cr/U, V data are interpolated at a double clock rate of 13.5Mbps.

PXCLK Processing

PXCLK is generated from the 27.0MHz system clock according to the appropriate selected format and the clock signal for Y, Cb, Cr/Y, U, V data de-multiplexing is also generated.

Set-up Control (NTSC)

In the NTSC signal generation mode, three set-up modes are possible according to the register. Selectable set-up modes are;

Mode 0 : Set-upÆ0 IRE Mode 1 : Set-upÆ+7.5 IRE Mode 2 : Set-upÆ-7.5 IRE

Cb/Cr to U/V Conversion

The Cb/Cr data are converted into the U/V data by the following equations;

U=0.493¥Cb/0.564 V=0.877¥Cr/0.713

MITSUBISHI ICs (TV)

PRELIMINARY

Notice:This is not a final specification. Some parametric limits are subject to change.

Burst Insertion

The burst signal, set up in the corresponding register, is inserted to Cb/Cr according to the burst timing signal. The burst signal is derived from the following equations;

NTSC=ABS (Burst level-128)¥5/5.47 (IRE)

Ex. 40IRE=54H

PAL={ABS (Burst level-128)¥5/5.47}¥÷2 (IRE)

Ex. 43IRE=5EH

Video Anticopy Signal Addition [1] (VBI Amplitude/CSP)

This applies to M65675FP only. Sync-amplitude function and Color StripeTM control function are carried out according to the corresponding register, in accordance with Macrovision Video Anti Copy Process Rev. 7.0 dated September 6 1996.

M65675FP/M65676FP

DIGITAL NTSC/PAL ENCODER

Encoder Closed Caption Encoding

In the NTSC (525/60) mode, 8-bit¥2byte data, including parity bit, set in the register are converted into the format shown in ﬁg. 1 and then will be inserted in the video signal according to the register data of the closed captions control speciﬁcation (closed caption on/ off and caption data insertion mode). After the completion of transmission, the new data are loaded in the register by setting the close caption ﬂag to "1", then the transferred data are loaded in the register on the trailing edge of V-sync pulse by setting that ﬂag to "0". (In case the closed caption ﬂag is "1", the new data loading is halted and the caption data are not inserted in the video signals).

20(283) line

Color Burst

10.500±0.5µs

7 cycles of 503kHz

(Clock Run-in ) 1st. byte 2nd. byte

CCD00

START BIT

12.910µs

3.972+0.2/-0.0µs

51.268+0.2/-0.0µs

61.331±0.5µs

63.556µs

21(284) line

Parity Bit Parity Bit

CCD03

CCD04

CCD05

CCD06

CCD07

CCD01

CCD02

CCD10

33.764µs

CCD11

CCD12

Fig. 1 CLOSED CAPTION WAVEFORM

CCD13

CCD14

CCD15

CCD16

CCD17

22(285) line

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