Mitsubishi M65669SP, M65669FP Datasheet
M65669SP/FP
PRELIMINARY
NTSC, PAL-M, PAL-N color TV
*1 : Include pin capacitance ( 7 pF )
PIN CONFIGURATION (TOP VIEW)
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
V3.1
MITSUBISHI DIGITAL TV ICs
PICTURE-IN-PICTURE
SIGNAL PROCESSING
DESCRIPTION
The M65669SP/FP is a PIP (Picture in Picture) signal
processing LSI, whose sub-picture input is composite
signal for NTSC, PAL-M, and PAL-N. The built-in field
memory (144k-bit RAM) , V-chip data slicer and analog
circuitries lead the high quality PIP system low cost and
small size.
FEATURES
* Built-in 144k-bit field memory ( sub-picture data storage)
* Internal V-chip data slicer (for sub-picture)
* Vertical filter for sub-picture ( Y signal )
* Single sub-picture ( selectable picture size : 1/9 , 1/16 )
* Sub-picture processing specification ( 1/9 , 1/16 size) :
Quantization bits Y, B-Y, R-Y : 6 bits
Horizontal sampling 229 pixels ( Y ) , 57 pixels ( B-Y, R-Y )
Vertical lines 69/ 52 lines
* Frame ( sub-picture ) on/off
* Built-in analog circuits :
One 8-bit A/D converter ( for sub-picture signal)
Three 8-bit D/A converters ( for Y, U and V of sub-picture )
Sync-tip-clamp, VCXO ... etc..
* IIC BUS control ( parallel/serial control) :
PIP on/off , Frame on/off ( programmable luma level),
Sub-picture size ( 1/9, 1/16 ),
PIP position ( free position ), Picture freeze ,
Y delay adjustment, Chroma level, Tint, Black level,
Contrast ...etc..
APPLICATION
RECOMMENDED OPERATING CONDITIONS
Supply voltage range ---------------------------------- 3.1 ~ 3.5 V
Operating frequency --------------------------------- 14.32 MHz
Operating temperature --------------------------------- -10 ~ 70 deg.
Input voltage (CMOS interface) "H" ----- VDD x 0.7 ~ VDD V
"L" ----- 0 ~ VDD x 0.3 V
Output current ( output buffer ) ------------------- 4 mA ( MAX )
Output load capacitance --------------------------- 20 pF ( MAX ) *1
Circuit current ---------------------------------------- - mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins.
Block diagram & Application examples
Shown next pages
SWM
ACK
SDATA
SCLK
DVdd
DVss
BGPS
SCK
BGPM
FSC
TEST5
TEST6
SWMG
RESET
DVdd
DVss
MCK
CSYNCS
AVss(ad)
Vrb
Vrt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
AVss(ana)
41
ADJ_Usub
40
Vdd(da)
YOUT
39
ADJ_Ysub
38
37
UOUT
36
ADJ_Vsub
35
VOUT
34
TESTEN
33
VD
32
HD
31
AVss(vcxo)
30
X'tal(P-N)
29
X'tal(P-M)
28
X'tal(NT)
27
BIAS
26
Filter
25
AVdd(vcxo)
24
AVdd(ad)
23
Vin(Sync sepa.)
22
Vin(ad)
Outline 42 Pin SDIP Package (M65669SP)
Outline 0.8mm pitch 42 Pin SOP Package (M65669FP)
( / )
15
1
M65669SP/FP
PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
BLOCK DIAGRAM
V3.1
MITSUBISHI DIGITAL TV ICs
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Y OUTPUT
U OUTPUT
V OUTPUT
PIP SW
Sub picture
Main HD
Main VD
( / )
2
15
SCL
SDA
M65669SP/FP
PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
V3.1
MITSUBISHI DIGITAL TV ICs
PICTURE-IN-PICTURE
SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions
VDD3
VI
VO
IO
PD
Topr
Tstg
(*1) Output current per output terminal. But Pd limits all current.
TYPICAL CHARACTERISTICS
Supply voltage (3.3V)
Input voltage
Output voltage
Output current (*1)
Power dissipation
Operating temperature
Storage temperature
Limits
Min. Max.
-0.3 4.6
-0.3 VDD3+0.3
-0.3 VDD3+0.3
IOH = -4
-
-10
-50
IOL = 4
1200
70
125
(VSS=0V)
Unit
V
V
V
mA
mW
deg.
deg.
THERMAL DERATING (MAXIMUM RATING)
2000
1600
1200
800
400
0
0 25 50 75 100 125
AMBIENT TEMPERATURE Ta (deg.)
70
( / )
15
3
M65669SP/FP
PRELIMINARY
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
DC CHARACTERISTICS
V3.1
MITSUBISHI DIGITAL TV ICs
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Symbol
VIL Input voltage
VIH
VT-
VT+ (CMOS interface)
VH
VOL
VOH
IOL
IOH
IIH
IIL
IOZL
IOZH
CI
CO
CIO
IDD
(CMOS interface)
Input voltage schmitt trigger -
CMOS output voltage
CMOS output current
Input current
Output leakage current
Input pin capacitance
Output pin capacitance f = 1MHz, VDD = 0V
Bidirectional pin capacitance
Operating current 3.3V supply
Parameter
(Ta = 25 deg. unless otherwise noted)
Condition
VDD = 2.7V
L
H VDD = 3.6V
+
VDD = 3.3V 1.4
Hysteresis
L
VDD = 3.3V, |IO| = 1µA
H
L
VDD = 3.0V, VOL = 0.4V
H VDD = 3.0V, VOH = 2.6V
L
VDD = 3.6V, VI = 0V
VDD = 3.6V, VI = 3.6V
H
L
VDD = 3.6V, VO = 0V
H
VDD = 3.6V, VO = 3.6V
Limits
Min. Typ. Max.
0
2.52
0.5 -
0.3
-
3.25
4
-
-1 -
-1
-1
-1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
180
0.81
3.6
1.65
2.4
1.2
0.05
-
-
-4
1
1
1
1
7
7
7
15
15
15
-
(VSS=0V)
Unit
V
V
V
mA
µA
µA
pF
mA
( / )
15
4
M65669SP/FP
PRELIMINARY
No.
Notice ; This is not the final specification.
Some of information in this document are
subject to changes.
PIN DESCRIPTION
V3.1
MITSUBISHI DIGITAL TV ICs
PICTURE-IN-PICTURE
SIGNAL PROCESSING
Pin
SWM
1
ACK
2
SDATA
3
SCLK
4
DVdd1
5
DVss1
6
BGPS
7
SCK
8
BGPM
9
FSC
10
11
TEST5
TEST6
12
SWMG
13
RESET
14
DVdd2
15
16
DVss2
17
MCK
CSYNCS
18
19
AVss (ADC)
20
VRB
21
VRT
22
VIN (ADC)
23
VIN (Sync Sep.)
24
AVdd (ADC)
25
AVdd (VCXO)
26
FILTER
27
BIAS
X'tal (NTSC)
28
29
X'tal (PAL-M)
X'tal (PAL-N)
30
31
AVss (VCXO)
32
HD
33
VD
34
TESTEN
35
VOUT
36
ADJ_Vsub
37
UOUT
38
ADJ_Ysub
39
YOUT
40
AVdd (DAC)
41
ADJ_Usub
42
AVss (sub)
Name I/O Function
CMOS output
CMOS output
CMOS I/O (5V)*1
CMOS input (5V)*1
Digital Vdd
Digital Vss
CMOS output
CMOS input
CMOS output
CMOS input
CMOS input
CMOS input
CMOS input
CMOS input
Digital Vdd
Digital Vss
CMOS input
CMOS input
Analog Vss
Analog
Analog
Analog
Analog
Analog Vdd
Analog Vdd
Analog
Analog
Analog
Analog
Analog
Analog Vss
CMOS input (5V)*1
CMOS input (5V)*1
CMOS input
Analog
Analog
Analog
Analog
Analog
Analog Vdd
Analog
Analog Vss
PIP switch output
I2C SDA output (for high load SDA line use only)
I2C SDA input/output
I2C SCL input
Vdd for digital part
Vss for digital part
Test output
Test input
Test output
Test input
Test input
Test input
Power on reset input
Vdd for digital part
Vss for digital part
Test input
Sub picture external C-sync input
Vss for internal ADC
Low level reference voltage output of ADC
High level reference voltage output of ADC
Sub picture input of ADC
Sub picture input of sync sep. for sub picture
Vdd for internal ADC
Vdd for VCXO
VCXO filter voltage connection
VXCO bias voltage connection
X'tal of NTSC connection
X'tal of PAL-M connection
X'tal of PAL-N connection
Vss for VCXO
Main picture HD input
MAIN picture VD input
Test input
Sub picture V or B output
Referece voltage connection of DAC of V
Sub picture U or G output
Referece voltage connection of DAC of Y
Sub picture Y or R output
Vdd for DAC
Referece voltage connection of DAC of U
Vss for substrate
Remarks
connect to GND
connect to GND
connect to GND
connect to GND
connect to Vdd
connect to GND
connect to GND
5
( / )
15
*1 ) (5V)means 5V I/F torelant
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