Mitsubishi M65580MAP-XXXFP Datasheet

Mitsubishi Semiconductor

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Digital Video/Chroma/Deflection

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MCU

Preliminary

Some of information in this document are subject to changes.

TSC TV with a closed caption

Note : This is not a final specification.

Description

The M65580MAP-XXXFP are semiconductor integrated circuits designed with CMOS silicon gate technology for NTSC television
system, include 8bit MCU( M37272MA core) with a closed caption decoder and circuits needed for TV baseband signals(Video and
Chroma) processor and Deflection in a chip. PCB area and EMI noise can be reduced by one chip and 80QFP, and internal
connection of OSD signals. And it can realize a adjustment free system by built-in MCU and get a high performance adaptive YC
separation by 1 line memory. The above technology makes its performance more stable and better.

Feature

• Y/C processor : 8bit Input, 10bit Output digital processing

• Deflection processor : optimized system by conventional analog and digital mixed solution

• ADC&DAC : 8bit high speed video ADC & 10bit high speed video DAC
[MCU Block]
MCU(single microcomputer) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass-production.
And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O.
It has a OSD, data slicer , and I
decoder.
[ASIC Block]
ASIC block consists of the following blocks.
(1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal, 2 channels 8 bit high speed video ADCs,
and ACC amplifiers
(2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including sharpness,
YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit.
(3) Deflection block ; A high performance sync separation by analog and digital mixed solution
(4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit.

2

C-BUS interface. So it is very useful for a channel selection system for N

M65580MAP-XXXFP

Application

NTSC TV with a closed caption decoder

PIN CONFIGURATION (TOP VIEW)

P00/PWM0

P13/SDA1

P14/SDA2

64

62

63

HLF

CV IN

X IN

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

1

3

2

P01/PWM1
P02/PWM2
P03/PWM3
P04/PWM4

P05/AD3

P06/INT2/AD4

P07/INT1
P23/TIM3
P24/TIM2

P25/AD5

VHOLD

CN VSS

X OUT

P12/SCL2

59

60

61

55

56

57

58

53

54

OSD(R) IN

V-PULSE OUT

51

52

P50/HSYNC IN/OUT

P51/VSYNC

P52/R

P53/OUT1

P30/G

P31/B

P10/OUT2

P11/SCL1

M65580MAP-XXXFP

9

8

7

6

5

4

12

11

10

14

13

OSD(B) IN

OSD(G) IN

FAST BLK

48

49

50

17

16

15

SCL

HALF TONE

H OUT

SDA

46

47

44

45

19

18

21

20

VDD(DEF)

FBP IN

42

43

23

22

VSS(DEF)

41

40

NECK PROTECTOR

39

HVCO F/B

38

V-RAMP OUT

37

AFC1 FILTER

36

X-RAY PROTECT

35

X-TAL

34

CHROMA APC FILTER

33

VDD(VCXO)

32

B OUT

31

VSS(OUTPUT)

30

G OUT

29

VDD(OUTPUT)

28

R OUT

27

VZ OUT

26

TV IN

25

VRB

24

VSS

FILT

VCC

P27/XCOUT

RESETB

P22/SIN/AD8

P20/SCLK/AD6

P21/SOUT/AD7

P26/FSCIN/XCIN

P16/AD2/TIM2

P15/AD1/INT3/FSCIN

CLK OUT

OSD CLK

VSS(DIGITAL)

VDD(DIGITAL)

RESETB(ASIC)

MITSUBISHI

EXT IN

Y SW OUT

VDD(INPUT)

SYNC SEP IN

Y IN

C IN

VRT

VSS(INPUT)

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Note : This is not a final specification.

Block Diagram(Whole)

Vss(Input)

Vdd(Input)

Vdd(VCXO)

19 21 25 23 42 41 37 44 43 40 35 34 38 3933

Vrb

Vrt

Vss(DEF)

Vdd(DEF)

AFC1 Filter

H OUT

Neck Protector

FBP IN

Chroma APC Filter

XTAL

M65580MAP-XXXFP

V-RAMP OUT

HVCO F/B

VZ OUT

Vss(OUTPUT)

Vdd(OUTPUT)

Vcc 3

To TV IN of ASIC

27
31
29

1713SYNC SEP IN
18 Y SW OUT

CLK-2 OUT

46

SCL

45 SDA

OSD(B) IN

48

OSD(G) IN

49

OSD(R) IN

51

FAST BLK

50

OSD H-SYNC

53

FAST BLK

56

OSD(R) OUT

58

OSD(G) OUT

57

OSD(B) OUT

55

1Vss

77

75

CV IN

HLF

CCD

76

VHOLD

SIGNAL PROCESSOR

3bit Digital OSD

FAST BLK

OSD

FAST BLK

HD

HD

HALF TONE

VD

VD

HALF TONE

MCU CORE

M37272MA

Intelligent Monitor

HALF TONE
OSD V-SYNC
OSD V-SYNC

HALF TONE

36
12
14
16
26
24
22
20

32
30
28
15

11
59
52
54
47

78 CNVss

79
80

5
6
2 FILT

FSC IN
RESET

X-ray Protect
Vss(Digital)
Vdd(Digital)
RESET

TV IN
C IN
Y IN
EXT IN

B OUT
G OUT
R OUT

CLK(fsc) OUT

INTELLIGENT
MONITOR

RESET

CVBS/YC input

RGB OUT

X IN
X OUT

SCL
SDA

2in1 Tuner

P12/SCL2

60
62
61

EEPROM

63 64 65 66 67 68 69 71 72 73 74 4 770

P14/SDA2

P00/PWM0

I/O PORT

P05/AD3

P07/INT1

P24/TIM2

P02/PWM2

P01/PWM1

P04/PWM4

P03/PWM3

P23/TIM3

P06/INT2/AD4

MITSUBISHI

P25/AD5

P27/XCOUT

P22/S IN/AD8

10

9
8

P15/AD1/INT3
P20/SCLK/AD6
P21/S OUT/AD7

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Note : This is not a final specification.

Absolute maximum ratings

M65580MAP-XXXFP

Symbol Parameter Ratings Unit

VDD (MCU)
VDD (ASIC5V)
VDD (ASIC3.3V)
VI (MCU)
VO (MCU)
IOH (MCU)
IOL1 (MCU)

IOL2 (MCU)
VID (ASIC)
IOUT (ASIC)
Pd
Kt
Topr
Tstg

Supply voltage (MCU)
Supply voltage (ASIC5V)

Supply voltage (ASIC3.3V)
Input Voltage (MCU)
Output Voltage (MCU)
Circuit current (MCU)
Circuit current (P00-P07, P10, P15,

P16, P20-P27, P30, P31, P52, P53)
Circuit current (P11-P14)

Digital input voltage
Analog output current -30
Power dissipation
Thermal derating
Operating temperature
Storage temperature

All voltage are based on
Vss.Output transistors are
cut off.

Conditions

-0.3 to 6.0

-0.3 to 6.0

-0.3 to 4.0

-0.3 to Vcc+0.3

-0.3 to Vcc+0.3
0 to 1 (See note 1)
0 to 2 (See note 2)

0 to 6 (See note 2)

-0.3 to Vcc+0.3

1460

14.6

-20 to 65

-40 to 125

V
V
V

V
V

mA
mA

mA

V

mA

mW

mW/ ˚C

˚C
˚C

Recommended operating condition

(Ta=-20 to 65 ˚C, unless otherwise noted)

Limits

Symbol Parameter

VDD (MCU)
VDD (Digital)
VDD (Input)
VDD (Output)
VDD (VCXO)
VDD (DEF)

VIH1 (MCU)

VIH2 (MCU)

VIH3 (ASIC)

VIL1 (MCU)
VIL2 (MCU)

VIL3 (MCU) Low Input voltage (See note 4) P50, P51, RESETB,

VIL4 (ASIC) Low Input voltage RESETB, FBP IN, HALF TONE, 0.2Vcc

IOH (MCU)

Supply voltage (MCU) (See note 3)
Supply voltage (Digital) 4.75 5.0 5.25
Supply voltage (Input) 3.13 3.3 3.47
Supply voltage (Output)
Supply voltage (VCXO)
Supply voltage (DEF)

High Input voltage P00-P07, P10-P16, P20-P27, P50,

P51, RESETB, XIN

High Input voltage SCL1, SCL2, SDA1, SDA2
(When using I2C-Bus)

High Input voltage RESETB, FBP IN, HALF TONE,

OSD(R/G/B) IN, FAST BLK
Low Input voltage P00-P07, P10-P16, P20-P27
Low Input voltage SCL1, SCL2, SDA1, SDA2 0.3Vcc

(When using I2C-Bus)

XIN, TIM2, TIM3, INT1, INT2, INT3, SIN, SCLK

OSD(R/G/B) IN, FAST BLK

High average output current (See note 1)

P10-P16, P20-P27, P30, P31, P52, P53

Min. Typ. Max.

4.75 5.0 5.25 V

3.13 3.3 3.47

4.75 5.0 5.25

4.75 5.0 5.25

0.8Vcc

0.7Vcc

0.8Vcc

0
0

0

0

Vcc

Vcc

Vcc

0.4Vcc

0.2Vcc

1

Unit

V
V

V
V
V

V

V

V

V
V

V

V

mA

3

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Preliminary

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Note : This is not a final specification.

Limits

Symbol Parameter

IOL1 (MCU) 2

Low average output current (See note 2)

P00-P07, P10, P15, P16, P20-P27, P30, P31, P52, P53

Min. Typ. Max.

M65580MAP-XXXFP

Unit

mA

IOL2 (MCU) Low average output current (See note 2) P11-P14 6
f(XIN) (MCU)

fhs1 (MCU)
fhs2 (MCU) Input frequency SCLK MHz1

VI (MCU) Input amplitude video signal CVIN

Note

1: The total current that flows out the MCU must be 20mA or less.

2: The total input current to MCU (IOL1+IOL2) must be 30mA or less.
3: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data
slicer, use 8MHz.
4: Pin name in each parameter is described pin names.
(1) Dedicated pins: dedicated pin name.
(2) Double-/Triple-function ports.
When the same limits: I/O port name.
When the limits of function except ports are different from I/O port limits; function pin name.
5: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer pins.
P11-P14 have the hysteresis when these pins are used as multi-master I2C-Bus interface ports.
P20-P22 have the hysteresis when these pins are used as serial I/O pins.

Oscillation frequency (for CPU operation) XIN 7.9 8.0 8.1

(See note 5)

Input frequency TIM2, TIM3, INT1, INT2, INT3 100 kHz

Input frequency SCL1, SCL2 kHzfhs3 (MCU)

1.5

2.0

400

2.5

mA

MHz

kHzOscillation frequency (for sub-clock operation) XCIN 29 32 35f(XCIN) (MCU)
MHzOscillation frequency (for OSD standard clock) FSCIN 3.58FSCIN (MCU)

V

Thermal derating

THERMAL DERATING (MAXIMUM RATING)

2.0

1.5

1.46

1.0

0.88

0.5

POWER DISSIPATION Pd (W)

65 7550250 100 125 150

AMBIENT TEMPERATURE Ta (˚C)

4

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Preliminary

Some of information in this document are subject to changes.

Note : This is not a final specification.

[MCU Block(M37272MA)]

Description

MCU(single microcomputers) in this IC has almost same function and performance as M37272MA-XXXSP/FP in mass­production. And it is operated by simple instruction in the same memory space as that of built-in ROM, RAM, I/O.
It has a OSD, data slicer , and I
closed caption decoder.

2

C-BUS interface, so it is very useful for a channel selection system for NTSC TV with a

Features

• Number of basic instructions -------- 71

• Memory size
ROM -------- 40Kbytes
RAM -------- 1152bytes
(ROM correction memory:64bytes included)

• minimum instruction execution time --------- 0.5µs
(at 8 MHz oscillation frequency)

• Power source voltage -------- 5V±10%

• Subroutine nesting -------- 128 levels(max.)

• Interrupts -------- 17bytes 16vector

• 8-bit timers -------- 6

• Programmable I/O ports(Ports P0,P1,P2) -------- 23

• Input ports(Ports P50,P51) -------- 2

• Output ports(Ports P30,P31,P52,P53) -------- 4

• Serial I/O -------- 8-bit x 1channel

• Multi-master I

• A-D comparator (7-bit resolution) -------- 8 channels

• PWM output circuit -------- 8-bit x 5

• ROM correction function -------- 32 bytes x 2
Power dissipation -------- 165mW
(at Vcc=5.5V, 8MHz oscillation frequency, OSD on, and Data slicer on)

• Closed caption data slicer

• OSD function
Display characters -------- 32 characters x 2 lines(possible to display 3 lines or more by software)
Kinds of characters 254 kinds
Character display area CC mode : 16x26 dots
OSD mode : 16x20 dots
Kinds of character sizes CC mode : 1 kind
OSD mode : 8 kinds
Kinds of character colors 8 colors(R,G,B) (coloring unit: a character)
Kinds of background colors CC mode : 1 kind(black)
OSD mode : 8 kinds(possible to select color in character unit)
Display position horizontal : 128 levels Vertical : 512 levels
Attribute CC mode : smooth italic, underline, flash, automatic solid space
OSD mode : border(black)
Kinds of raster colors 8 kinds
Smooth roll-up
Window function

2

C-BUS interface -------- 1(2 systems)

M65580MAP-XXXFP

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(1) Analog frontend block ; Analog SW(2 CVBS(TV&EXT) inputs, Y/C signals to one signal), 2 channels 8 bit high speed video

• Deflection Block : H-Phase, V-size,

V

-shift, V-Linearity

Note : This is not a final specification.

[ASIC Block]

Description

CVBS(TV/EXT) signals or Y/C signals input to this IC are converted to 8 bit digital signal by 2 channels high speed video
ADCs. These signals are input to digital section to obtain high performance R/G/B signals. First, CVBS signals are separated
to high quality Y/C signals by 2 dimensional adaptive YC separation circuit, and then Y/C signals are converted to R-Y&B-Y
signals by digital chroma decoder, after that, to R/G/B signals by RGB matrix circuit. These signals are mixed with OSD
signals come from MCU block, are converted to analog R/G/B signals by 3 channel 10 bit high speed video DACs. In
deflection block, to get a better Horizontal & Vertical signals, a conventional analog solution by analog CMOS technology is
used.
ASIC block consists of the followings blocks.

ADCs , and ACC amplifiers
(2) Video and Chroma block ; A high performance 2 line adaptive YC separation by 1 line memory, Video blocks including
sharpness, YNR, a high performance blackstretch circuits, Chroma decoder, and RGB matrix including OSD mixing circuit.
(3) Deflection block ; A high performance sync separation by analog and digital mixed solution
(4) Analog backend block ; 3 channels 10 bit high speed video DACs for Cutoff & Drive, and Mute circuit.

Features

[Video/Chroma Block]

• Built-in 1 Video SW for TV/EXT signal input

• 2 additional pins for S(Y/C) input

• YUV input signal available ( T.B.D )

• 2 channel 8 bit Video ADCs for CVBS(TV&EXT) or Y/C signal inputs

• Built-in adaptive 2 line comb filter(2DYCS) => Few dot crawl&crosscolor, and clear color transition

• Built-in a high performance Blackstretch => Dynamic & detailed picture

• Digital Luminance delay circuit => stable Y/C timing adjustment

• Built-in VCXO circuit(4fsc)

• High resolution R/G/B output => Built-in 10bit high speed Video DACs

• Internal connection of 8 color digital OSD ( R/G/B, F.B, H.T )

• Reference CLK output for tuner (fsc or 4MHz)

• Built-in YNR ( about fsc±1MHz)

• Gamma correction(for R/G/B signals)

M65580MAP-XXXFP

[Deflection Block]

• Analog(conventional) sync separation => Better performance by abundant experience

• Double AFC Circuit => Stable Horizontal scanning

• Built-in Horizontal reference Oscillator => No ceramic resonator and Adjustment free

• HD and VD pulse by Countdown => Stable HD&VD

• Built-in digital Vramp generator

[List of main I

• Chip : Power-down mode

• Analog Input Stage : CVBS/Y&C Input SW

• Luminance Processing : Sharpness, Blackstretch

• Chroma Processing : Color, Tint, Killer level

• RGB Matrix : ACL, OSD Input Level, Contrast, Brightness

• Analog Output Stage : Drive adj.(R/G/B), Cutoff adj.(R/G/B)

2

C bus controllable Items]

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Note : This is not a final specification.

ASIC Block Detailed Diagram

M65580MAP-XXXFP

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Linearity : 0 to 30 % by 7bit

Note : This is not a final specification.

Function and Outline of ASIC Block

Chip

Power down mode : 3 modes [ PD0 & PD1 & PD2 ]
Service SW : stop of Vertical(Vramp) output ( For cutoff adjustment )

Analog Block

• Input stage => CVBS&Y/C input signals
Input level (CVBS) : 1.23Vp-p (173IRE) @max. / 1.0Vp-p @typ.
Input level (Y/C) : Y:1.00Vp-p (140IRE) @typ./ C:0.7Vp-p @typ.

• Output stage => RGB output signals
Output level : 0.7 Vp-p (typ.)
Drive(R&G&B) : -3 to +4 dB by 7bit (White Balance)
Cutoff(R&G&B) : 0.5 V by 9bit (Start lighting point)

Digital Block

• 2DYCS
Adaptive YC separation by using of 1H line memory and original algorithm

• Luminance processing
Contrast : 0 to 200 LSB by 7bit
Brightness : -20 to 20 LSB by 8bit (Pedestal DC level)
Sharpness : 0 to 3 dB by 5bit (by 0, 70, 140, 210ns)
Delay adjustment : 0 to 210 ns by 2bit(70ns step) to Chroma signal
Blackstretch : 3 selectable stretch point
[ Stretch areas ( 0 to 25/30/40IRE ), Through areas ( 25/30/40IRE ~ ) ]
4 selectable blackstretch curves ( 1/4, 2/4, 3/4, 4/4)

• Chroma processing
Tint : -45 to 45 degree by 7bit => about 0.7 degree
: Variable demodulator (R-Y) axis
(-22.5 to +22.5 degree by 6bit => about 0.7 degree)
Color : 0 to 200 % by 7bit

M65580MAP-XXXFP

• RGB matrix
: Matrix(R-Y signal) ratio selectable (12/8, 13/8, 14/8)
ACL : Automatic Contrast Limiter by MCU port(ADC) and I
EXT/RGB : clip to 7LSB @ data < 0Fh
BlueBack : ON/OFF selectable
Mute : ON/OFF of R/G/B output
Neck Protector : R/G/B output to zero( no signal)

Deflection Block

• Horizontal Output
AFC2 phase : +5 to -5µs by 5bit
Hold => Shut down : fh@Hold-down : in about 16.5KHz => fh@Shutdown : H-STOP
AFC1 gain : Normal/High selectable for VTR skew

• Vertical Output
V position : 0 to 16 H by 3 bit => 2H unit(connected with BLK)
V size : 1.4 to 2.6 V by 7bit

2

C bus

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0.1u

0.1u

0.1u

0.1u

0.1u

1M

560

0.1u

2K

+200V

0.1u

0.1u

10K

10K

510157480

1211131476777879234

678919

18171612024232221656965666768707172736425

29

282726

30

35363433323140

3938373940

45495459535251414243444647485055565758

60616263CLK-2 Out

CLK(fsc) Out

Vdd(Dig)

Vss(Dig)

Sync Sep. In

CVBS(x2) Out

Vdd(Input)

TV in

Reset In

P22/Sin/AD8

P21/Sout/AD7

P20/SCLK/AD6

P15/AD1/INT3

Reset In

P26/FSCin

P27/Xcout

VCC

Vss(Input)

EXT in

Vrt

Vss

FILT

P16/AD2/TIM2 (Int. Mon. In/Out)

R(OSD) in

F.B in

SDA

SCL

G(OSD) in

B(OSD) in

P51/Vsync

Vdd(Def)

Vss(Def.)

P52/Rout

P53/OUT1

P30/Gout

P31/Bout

VD out

P10/OUT2

P11/SCL1

P12/SCL2

P13/SDA1

P14/SDA2

H.T in

P50/Hsync In/out

H OUT

P00/PWM0

Yin

FBP IN

NECK PRO65647475

5V5V3.3V

5V

3.3V

5V

9V

3.3V

5V

15p

15p

470p

0.1u

0.1u

470p

0.01u

470p

0.1u

0.01u

Note : This is not a final specification.

Application Examples

M65580MAP-XXXFP

SW REG

REG

ACL In

FBT

SDA

Reset

SCL

MCU

POWER ON H

Digital Block

REG

REG

Video det out
(1.23Vp-p)

EXT In
(1.23Vp-p)

Y In
(1.00Vp-p)

C In
(0.70Vp-p)

150V

REG

1.5K

1.5K

ASIC

Analog Block

H-Pulse Out

FBP in

-

DY

to H DRIVE

FBT

1.5K

9

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