Datasheet M64895FP Datasheet (Mitsubishi)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

DESCRIPTION

The M64895 is a semiconductor integrated circuit consisting of PLL
frequency synthesizer for TV/VCR using I
contains the prescaler with operating up to1.3GHz, 4 band drivers
and tuning Amplifier for direct tuning. Built-in 4 band drivers.

FEATURES

•

4 integrated PNP band drivers
(Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V)

•

Built-in high-withstanding voltage tuning Amplifier

•

Low power dissipation (Icc=20mA, Vcc=5V)

•

Built-in prescaler with input amplifier (Fmax=1.3GHz)

•

PLL lock/unlock status display out put

•

(Built-in pull up resistor )

2

•

I

C bus control (write mode only)

•

X’tal 4MHz is used to realize 3 type of tuning steps
(Division ratio 1/512, 1/640, 1/1024)

•

Programmable chip address

•

Small package (16Pin SOP/SSOP)

APPLICATION

TV , VCR tuners

2

C BUS control. It

MITSUBISHI IC

(TV)

S

M64895FP/GP

2

I

C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

PIN CONFIGURATION (TOP VIEW)

PRESCALER
INPUT

GND
SUPPLY

VOLTAGE 1
SUPPLY
VOLTAGE 2

BAND
SWITCHING
OUTPUTS

fin

GND

CC1

V

CC2

V

BS4
BS3
BS2
BS1

1
2

3
4

16
15

M64895FP/GP

14
13
125
116
107

98

Outline 16P2S-A/16P2Z-A

RECOMMENDED OPERATING CONDITION

Supply voltage range..............................................V

Rated supply voltage...........................................................V

Xin
ADS
SDA
SCL
LD/ftest
V

CC3

Vtu
Vin

V

CC2

CRYSTAL

OSCILLATOR

CHIP ADDRESS
INPUT

DATAINPUT
CLOCK INPUT

LD/ftest
OUTPUT
SUPPLY
VOLTAGE 3
TUNING
OUTPUT

FILTER INPUT

=4.5 to 5.5V

CC1

=V

CC1

V

CC3

=28 to 35V

V
V

to 13.2V

=5V

CC1

=12V

CC2

CC3

=33V

BLOCK DIAGRAM

Xin ADS SDA SCL

16 15 14 13 12 11 10 9

OSC

DIV

fin GND VCC1 VCC2 BS4 BS3 BS2 BS1

2

1/32,1/33

1/8

AMP

I2C BUS RECIEVER

MAIN COUNTER

SWALLOW COUNTER

P.O
RESET

BIAS

LOCK

10

5

4

V

CC3 Vtu Vin

LOCK
DETECTOR

PHASE
DETECTOR

BAND DRIVER

AMP

CHARGE
PUMP

87654321

1

MITSUBISHI ICS (TV)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

I2C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

M64895FP/GP

DESCRIPTION OF PIN

Pin No. Symbol Pin name Function

1 f in Prescaler input Input for the VCO frequency.
2 GND GND Ground to 0V.
3VCC1 Power supply voltage 1 Power supply voltage terminal. 5.0V±0.5V
4VCC2 Power supply voltage 2 Power supply for band switching, Vcc1 to 13.2V
5

BS4

6

BS3

7

BS2

8

BS1

9 Vin

10 Vtu Tuning output This supplies the tuning voltage.
11 VCC3 Power supply voltage 3 Power supply voltage for tuning voltage 28 to 35V

12 LD/ftest Lock detectt/ Test port

13 SCL Clock input Data is read into the shift register when the clock signal falls
14 SDA Data input Input for band SW and programmable freq. divider set up.
15 ADS Address switching input Chip address sets it up with the input condition of terminal.

16 Xin

Band switching
outputs

Filter input
(Charge pump output)

This is connected to
the crystal oscillator.

PNP open collector method is used.
When the band switching data is "H",the output is ON.
When it is "L",the output is OFF.

This is the output terminal for the LPF input and charge pump output.
When the phase of the programmable divider output (f1/N) is ahead compared to

the reference frequency (f
If it is behind, the "sink" current becomes active.
If the phases are the same, the high impedance state becomes active.

Lock detector is output.
Programmabule freq. Divider output and reference freq. output is selected by the

test mode.

4.0MHz crystal oscillator is connected.

REF), the "source" current state becomes active.

ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted)

Symbol Parameter Conditions Ratings Unit
VCC1 Super voltage 1 Pin3 6.0 V
VCC2 Super voltage 2 Pin4 14.4 V
VCC3 Super voltage 3 Pin11 36.0 V
VI Input voltage Not to exceed VCC1 6.0 V
VO Output voltage Pin16 6.0 V

VBSOFF
IBSON Band output current circuit 50.0 mA

tBSON ON the time when the band output is ON 3circuits are pn at same time 10 sec
Pd Power dissipation Ta=75°C 470 mW
Topr Operating temperature -20 to +75 °C
Tstg Storage temperature -40 to +125 °C

Voltage applied when the band output is
OFF

per 1 band output circuit
50mA per 1 band output

14.4 V

RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted)

Symbol Parameter Conditions Ratings Unit

CC1 Super voltage 1 Pin3 4.5 to 5.5 V

V
VCC2 Super voltage 2 Pin4 VCC1 to 13.2 V
VCC3 Super voltage 3 Pin11 28 to 35 V
fopr1 Operating frequency (1) Crystal oscillation circuit 4.0 MHz
fopr2 Operating frequency (2) 80 to 1300 MHz

IBDL Band output current 5 to 8

Normally 1 circuit is on. 2 circuits on at the
same time is max. It is prohibited to have 3 or
more circuits turned on at the same time.

0 to 40 mA

2

MITSUBISHI ICS (TV)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

I2C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

M64895FP/GP

ELECTRICAL CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, Vcc1=5.0V, Vcc2=12V , Vcc3=33V)

Symbol Parameter Test pin Test conditions
VIH

VIL “L” input voltage 13 to 14 −− 1.5 V
IIH “H” input current 13 to 14 VCC1=5.5V , Vi=4.0V −− 10 µA

Input
terminals

“H” input voltage 13 to 14 3.0 −

IIL “L” input current 13/14 VCC1=5.5V , Vi=0.4V − -4/-14 -10/-30 µA
VOL

LO Leak current 14 VCC1=5.5V, V o=5.5V −− 10 µA

I
VBS

IOLK1 Leak current 5 to 8
VtoH

VtoL Output voltage “L” 10 VCC3=33V − 0.2 0.4 V
IOH
IOL “L” output current 9 VCC1=5.0V , Vo=2.5V − ±70 ±110 µA
ICPLK Leak current 9 VCC1=5.0V , V o=2.5V −− ±50 nA

SDA
output

Band
SW

Tuning
output

Charge
pump

“L” output voltage 14 VCC1=5.5V, Io=3mA −− 0.4 µA

Output voltage 5 to 8 VCC2=12V, Io=-40mA 11.6 11.8 − V

VCC2=12V band SW is OFF
Vo=0V

Output voltage “H” 10 VCC3=33V 32.5 −−V

“H” output current 9 VCC1=5.0V , Vo=2.5V −±270 ±370 µA

ICC1 Supply current 1 3 VCC1=5.5V − 20 30 mA
ICC2A

ICC2B

Supply
current 2

4 circuits: OFF 4 VCC2=12V −− 0.3 mA
1 circuits: ON,

Output: OPEN

4VCC2=12V − 6.0 8.0 mA

ICC2C Output current 40mA 4 VCC2=12V Io=-40mA − 46.0 48.0 mA
ICC3 Supply current 3 11 VCC3=33V Output ON − 3.0 4.0 mA

The typical values are at VCC1=5.0V VCC2=12V VCC3=33V, Ta=+25°C.

Limits

Min. Typ. Max.

VCC1+0.3

−− -10 µA

Unit

V

SWITCHING CHARACTERISTICS (Ta=-20°C to +75°C, unless otherwise noted, VCC1=5.0V, VCC2=12V, VCC3=33V)

Symbol Parameter Test pin Test conditions

fopr

Vin

Prescaler operating
frequency

Operating input
voltage

VCC1=4.5 to 5.5V

1

Vin=Vinmin to Vinmax
VCC1=4.5

to 5.5V

1

80 to 100MHz -24 − 4
100 to 200MHz -27 − 4
200 to 800MHz -30 − 4
800 to 1000MHz -27 − 4

1000 to 1300MHz -18 − 4
fSCL Clock pulse frequency 13 VCC1=4.5 to 5.5V 0 − 100 kHz
tBUF Bus free time 14 VCC1=4.5 to 5.5V 4.7 −−µs
tHD

STA

t

LOW SCL low hold time 13 VCC1=4.5 to 5.5V 4.7 −−µs

Data hold time 13 VCC1=4.5 to 5.5V 4 −−µs

tHIGH SCL high hold time 13 VCC1=4.5 to 5.5V 4 −−µs
tSU

STA

t

HD

DAT

t

SU

DAT

t

r Rise time 13, 14 VCC1=4.5 to 5.5V −−1000 ns

Set up time 13, 14 VCC1=4.5 to 5.5V 4.7 −−µs
Data hold time 13, 14 VCC1=4.5 to 5.5V 0 −−s
Data set up time 13, 14 VCC1=4.5 to 5.5V 250 −−ns

tf Fall time 13, 14 VCC1=4.5 to 5.5V −− 300 ns
tSU

STO

Set up time 13, 14 VCC1=4.5 to 5.5V 4 −−µs

Limits

Min. Typ. Max.

80 − 1300

Unit

MHz

dBm

3

MITSUBISHI ICS (TV)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

METHOD OF SETTING DATA

The input information to consit of 2 or data of 4bytes to lead to Chip
Address is received in I
protocol admitted in the following.
1_STA CA CB BB STO
2_STA CA D1 D2 STO
3_STA CA CB BB D1 D2 STO
4_STA CA D1 D2 CB BB STO
STA : Start condition
STO : Stop condition
CA : Chip address
CB : Control data byte
BB : BandS.W. data byte
D1 : Divider data byte
D2 : Divider data byte

2

Cbus receiver. It shows a definition of bus

M64895FP/GP

I2C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

The information of 5 bytes necessary for circuit operation is chip
address and control data, bandS.W . data of 2 bytes and divider byte
of 2 bytes. After the chip address input, 2 or data of 4 bytes are
received.
Function bit is contained the first and the third data byte to
distinguish between divider data and control data, band data, and
"0" goes ahead of divider data, and "1" goes ahead of control data,
bandS.W. data.

SDA

SCL

S

STA

Write mode format

Address Byte 11000MA1MA00A
Devider Byte1 0 N14 N13 N12 N11 N10 N9 N8 A
Devider Byte2 N7 N6 N5 N4 N3 N2 N1 N0 A
Control Byte1 1 CP T2 T1 T0 RSa RSb OS A
Band SW Byte XXXXBS4BS3BS2BS1A

1-7 8 9 1-7 8 9 1-7 8 9

ADDRESS

CA

Byte MSB LSB

0 ACK DATA ACK DATA ACK

P

STO

4

MITSUBISHI ICS (TV)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

TEST MODE DATA SET UP METHOD

Test Mode Bit Set Up

X : Random, 0 or 1. normal "0"
MA1 ,MA0 : Programmabule Address Bit

Address input voltage MA1 MA0
0 to 0.1∗V
Always valid 0 1

0.4∗VCC1 to 0.6*VCC1 10

0.9∗VCC1 to VCC1 11

N14 to N0 : How to set dividing ratio of the programable the divider

Dividing ratio=N14(2
Therefore, the range of division N is 1,024 to 32,768

Example) fvco=fREF×8×N

CP: Setting up the charge pump current of the phase
comparator

CC1 00

14

=16384)+ ⋅⋅⋅ +N0(20=1)

=3.90625×8×N
=31.25×N (kHz)

CP Charge pump current Mode

070µA Test
1 270µA Normal

I2C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

M64895FP/GP

T2,T1,T0 : Setting up for the test mode

T2 T1 T0 Charge pump Pin 12 condition Mode
0 0 X Normal operation Lock output Normal operation
0 1 X High impedance Lock output Test mode

1 1 0 Sink Lock output Test mode
1 1 1 Source Lock output Test mode
1 0 0 High impedance fREF output Test mode
1 0 1 High impedance f1/N output Test mode

RSa, RSb : Set up for the reference frequency division ratio

RSa RSb Division ratio

1 1 1/512
0 1 1/1024
X 0 1/640

OS : Set up the tuning amplifier

OS Tuning voltage output Mode

0 ON Normal
1 OFF Test

Power on reset operation (Initial state the power is turned ON)
BS4 to BS1 : OFF
Charge pump : High impedance
Tuning amplifier : OFF
Charge pump current : 270µA
Frequency division ratio : 1/1024
Lock detector : High

TIMING DIAGRAM

START condition

SDA

BUF

t

SCL

tHD

STA

STOP condition START condition STOP condition

LOW

trt

tHD

DAT

tf

tHIGH tSU

DAT

tSU

STA

tHD

STA

CRYSTAL OSCILLATOR CONNECTION DIAGRAM

16

18pF

4MHz

Crystal oscillator characteristics
Actual resistance : less then 300 Ω
Load capacitance : 20pF

tSU

STO

5

MITSUBISHI ICS (TV)

PRELIMINARY

Notice:This is not a final specification.
Some parametric limits are subject to change.

APPLICATION EXAMPLE

1nF

1nF

M64895FP/GP

I2C BUS FREQUENCY SYNTHESIZER FOR TV/VCR

BUILT-IN PLL TUNER

+5V

10µF

-

ADS

15

SDA

14

3

1

Vcc

M64895

Vcc

BS4

BS3

BS2

BS1

2

4

5

6

7

8

fin

1000pF

1

+B

BS4

BS3

BS2

BS1

Lo

UHF VHFVcc1 to 12V

4-BAND
TUNER

IF

IF

MCU

1nF

SCL

13

LOCK

12

16 11

18pF
4MHz

1.5nF

0.1µF

Vin

9

Vtu

10

Vcc3GNDXin

2

+33V

BT

56k

56k

∗100pF

VT

2.2nF

Note) Filter constant is

for reference.

∗ Add a capacitor to stabilize

the filter circuit.

AFT

AGC

Units Resistance : Ω

Capacitance : F

AGC

6