Mitsubishi M64811AGP Datasheet
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M64811AGP is a 1.1GHz/500MHz band two-system
one-chip PLL frequency synthesizer .
Using a high performance Bi-CMOS process , the product
contains one two-modulus (1/32 and 1/33) prescaler that
accepts inputs up to 1.1GHz and another two-modulus
(1/16 and 1/17) prescaler that accepts inputs up to
500MHz ,thus helping make the equipment compact .
FEATURES
• Operating supply voltage : 2.7V~3.6V
• Operating temperature : -30°C~+85°C
• 2 PLL systems (1.1GHz and 500MHz) are on one chip .
PLL1 : 700MHz~1.1GHz PLL2 : 100MHz~500MHz
• Low power consumption (Icc=8mA Typ at Vcc=3V) .
• Dividing ratio setting ranges :
FIN1 for 1.1GHz VCO• • • • • N(VCO1)=1,024~131,071
FIN2 for 500MHz VCO• • • • • N(VCO2)=256~131,071
OSC for Fref • • • • • • • • • • • • • N(Fref)=5~2,047
• Each loop has input pin for sleep mode .
Power supplies to 2 loops can be independently turned ON/OFF .
Also can be controlled by the serial data . (When SLEEP1 and SLEEP2 is "H" . )
• The PLL standard oscillation circuit can adopt a B-E Colpitts type oscillation circuit to from a stable
oscillation circuit.
• Current controlled charge pump . (Icp=±2mA const.)
• Locked condition detecting output
If a phase difference smaller than 3 times (∆t) of the OSC period continues for 15 periods or
longer , the condition is judged as locked, and the LOCK terminal goes to "L" .
(When , for example , fosc=19.2 MHz , ∆t=156 ns)
• PLL lock/unlock status indicate function .
(Judged in the system turned on if the other system is turned off . )
• Small package (16pin SSOP, lead pitch : 0.65mm)
FIN1
GND
CPS
LE
SLEEP1
SLEEP2
FIN2
SI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
PD1
Vcc
XIN
XOUT
XBo
LOCK
GND
PD2
9
APPLICATION
• Digital cordless phone (CT2)
• Digital cellular phone (PDC)
1
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
BLOCK DIAGRAM
LPF VCO
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
LPF VCO
GND
PD2
9
CHARGE
PUMP
LOCK
PHASE
2
DETECTOR
DETECTOR
VCC
15
DATA LATCH
PROGRAMMABLE
SWALLOW / PROGRAMMABLE
COUNTER
REFERENCE COUNTER
PD1
16
CHARGE
LOCK
PHASE
DETECTOR
DATA LATCH
SWALLOW / PROGRAMMABLE
COUNTER
PUMP
DETECTOR
DATA LATCH
LATCH
SELECT
11
LOCK
5
LE
10
GND
ON/OFF
PLL1
(1/16, 1/17)
500MHz 2-MODULUS
PRESCALER
8
6
FIN2
SLEEP1
ON/OFF
PLL2
7
XIN
SLEEP2
TCXO
OSC
XOUT
131412
XBo
1.1GHz 2-MODULUS
PRESCALER
(1/32, 1/33)
SLEEP Control
1
FIN1
RESISTER
SHIFT
4
SI
3
CPS
2
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
FUNCTION DESCRIPTION OF PINS
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Identification Description
FIN1
GND
CPS
SI Shift register data input pin
LE
SLEEP1
SLEEP2
FIN2
PD2
GND
LOCK
XBo
XOUT
XIN
Input from the VCO , Fmax = 1.1GHz .
Ground .
Clock pulse input .
Binary serial data input .
Load enable input . When LE is HIGH , data stored in the shift registers is loaded into the
appropriate latch .
PLL1 power control . "H" = normal operation , "L"=power down .
PLL2 power control . "H" = normal operation , "L"=power down .
Input from the VCO , Fmax = 500MHz .
Charge pump2 output . Tristate output . High Z when PLL2 power is off .
Ground .
When loops are locked ••••••••"L" , When one of loops is unlocked••••••••"High Z" .
If one loop is sleep mode , the status of the other loop is checked for judgment .
Buffer output of oscillator .
Crystal Oscillator input .
Shift register clock input pin .
15
16
Vcc
PD1
Power supply . Vcc = 2.7~3.6V .
Charge pump1 output . Tristate output . High Z when PLL1 power is off .
3
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