Mitsubishi M62361FP Datasheet
MITSUBISHI<Dig.Ana.INTERFACE>
output(0 scale)when power is turned ON or drops.
COMPARATOR
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62361FP is a Bi-CMOS semiconductor IC,containing 6
channels of 8-bit D-A converters(DAC),with a buffer operational
amplifier provided in the output of each channel.It is easy to use
due to serial data input, and three-pin(DT,CK,ST)connection with
microcomputer.
This IC is designed to be operable when chip select data
contained in the 15-bit data conforms to the state of the CS
terminal.Accordingly,the IC can process data by strobe signals
common with other devices connected to the bus of
microcomputer, and does not involve an microcomputer port to
drive the IC.The inputs are connected to a level shift circuit so
that the input threshold level does not depend on supply
voltage.The IC also contains an initialization function to reset
FEATURES
•Output buffer operational amplifier provided in each channel
•15-bit serial data input
•6 channels of R-2R and segment type 8-bit DAC
•Chip select terminal
•Power-on reset function
APPLICATION
Digital-analog conversion in industrial or home-use electric
equipment.
Automatic control in combination with EEROM and
microcomputer(Substitute for conventional semi-fixed
resistor)
Signal gain setting of display monitor and CTV.
PIN CONFIGURATION (TOP VIEW)
DK
CK
ST
CS
NC
D.G
A.G
Vss
1
2
3
4
Outline 16P2N-A
16
VDD
15
Ao1
14
Ao2
13
Ao3
125
Ao4
Ao5
116
Ao6
107
98
VREF
NC:NO CONNECTION
BLOCK DIAGRAM
DT
CK
ST
CS
VDD
1
2
3
4
LEVEL
SHIFT
RESET
CIRCUIT
8-BIT
LATCH
8-BIT DAC
15
Ao1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8-BIT
LATCH
8-BIT DAC
14
Ao2
15-BIT SHIFT RESISTER
4
DECODER
8-BIT
LATCH
8-BIT DAC
13
Ao3
8-BIT
LATCH
8-BIT DAC
12
Ao4
8
6
8-BIT
LATCH
8-BIT DAC
11
Ao5
8-BIT
LATCH
8-BIT DAC
10
Ao6
16
6
D.G
9
VREF
VSS
8
7
A.G
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EXPLANATION OF TERMINALS
Pin No. Symbol
1
2
3
4
16
6
7
9
8
15
14
13
12
11
10
5
DT
CK
ST
CS
VDD
D•G
A•G
VREF
Vss
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
NC
MITSUBISHI<Dig.Ana.INTERFACE>
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Function
Serial data input terminal
Shift clock input terminal to input data at rise of clock pulse
Strobe input terminal to latch data in the register when H-level signal is input
Chip select terminal
Power supply terminal for input level shift circuit and buffer amplifier
GND terminal for digital line
GND terminal for analog line
8-bit D-A converter power supply terminal
8-bit D-A converter minimum power supply terminal
8-bit D-A converter output terminal
Not used
TIMING CHART (MODEL)
DT
CK
ST
AO
LSB
D01 D02
D03
D04
D02
D03
D04
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ELECTRIC
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MITSUBISHI<Dig.Ana.INTERFACE>
M62361FP
8-BIT 6CH D-A CONVERTER WITH BUFFER AMPLIFIERS
ABSOLUTE MAXIMUM RATINGS(Ta=25°C, unless otherwise noted)
Symbol Ratings
VDD
VREF
VIN
Ao
Pd
K
Topr
Tstg
Supply voltage
Reference voltage
Input voltage
Output voltage
Power dissipation
Thermal derating
Operating temperature
Storage temperature
Parameter
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS( Ta=25°C,VDD=8.0V,VREF=5.0V,Vss=0V,RL=2kΩ unless otherwise noted)
Symbol
VDD
IDD
VREF
Vss
IREF
RSL
EZR
EFS
DNL
ECH
VIH
VIL
IIH
IIL
VAO
Isink
Current dissipation
Voltage range at VREF
Voltage range at Vss
Maximum sink current at VREF
Resolution
Zero point error
Full scale error
Differential nonlinearity error
Error between channels
Input voltage
Input current
Output voltage range
Output sink current
H-level
L-level
H-level
L-level
Ta=-25 ~ +85°C
Set at
VREF=VDD-2V
Set at
Vss≥0.3V
Monotony assured
VDD=6.0 ~ 10V
VDD=6.0 ~ 10V
VDD=6.0 ~ 10V
VDD=6.0 ~ 10V
Set at
Conditions
Test conditions
128
for all channels. RL=∞
256
107
for all channels.
256
15
min. for all channels.
256
-0.3~+15
-0.3~+8
-0.3~VDD
-0.3~VDD
-20~+85
-55~+125
Min.
6.0 8.0 14.0
4.0
-0.2
-1.5
-1.5
-1.0
-3
3.5
0
0.3
0
550
5.5
Limits
Typ.
5 10
0.0
1.5
0
-1.5
Max.
7.5
1.0
3
8
1.5
1.5
1
3
VDD
1.0
10
10
VREF
-2LSB
100
Unit
V
V
V
V
mW
mW/°C
°C
°C
Unit Parameter
VOperating supply voltage
mA
V
V
mA
bit
LSB
LSB
LSB
LSB
V
V
µA
µA
V
µA
Isource
SR
VS1
∆VS1
VS2
∆VS2
(*Full scale range = maximum output voltage setting)
Output source current
Output through rate
Reset detection voltage 1
Hysteresis voltage 1
Reset detection voltage 2
Hysteresis voltage 2
For FSR*,Ao≥FSR-2LSB
Detection of VDD power
Detection of VDD power
Detection of VREF power
Detection of VREF power
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-5
0.3
4.25
0.05
2.85
0.03
4.45
0.1
3.0
0.06
0
4.65
0.2
3.15
0.15
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3
mA
V/µs
V
V
V
V
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