Mitsubishi M62353P, M62353GP, M62353FP Datasheet
MITSUBISHI<Dig.Ana.INTERFACE>
input/output.
display.
D0D7123456D8
9
10
M62353P,FP,GP
8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62353 is an integrated circuit semiconductor of CMOS
structure with 8 channels of built-in D-A converters with output
buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer
format mum wiring.
It is able to cascading serial use with Do terminal.
The output buffer operational amplifier operates in the whole
voltage range from power supply to ground for both
FEATURES
•12bit serial data input(3-wire serial data transfer method)
•Highly stable output buffer operational amplifier allow operation
in the all voltage range from power supply to ground.
APPLICATION
Adjustment/control of industrial or home-use electronic
equipment,such as VTR camera,VTR set,TV,and CRT
PIN CONFIGURATION (TOP VIEW)
Vss
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
VDD
1
2
3
4
(VrefL)
(VrefU)
Outline 16P4(P)
16P2N-A(FP)
16P2E-A(GP)
16
15
14
13
125
116
107
98
GND
Ao1
DI
CLK
LD
DO
Ao8
Vcc
BLOCK DIAGRAM
GND
16
BUFFER
OP AMP
1
Vss
(VrefL)
Ao1
15
-
8-BIT
R-2R D-A
Ch1
8-BIT
LATCH
.....
(8)
8-BIT
LATCH
Ch2
8-BIT
R-2R D-A
-
2
Ao2
DI
CLK
14 13 12
12-BIT SHIFT REGISTER
(8)
(8)
4
L
5
D-A
--
4
L
3
D-A
3
Ao3 Ao4
LD Do
D11
ADDRESS
DECODER
....
L
6
D-A
5
Ao5
11
L
D-A
--
6
Ao6
Ao8
10
-
D-A
8
L
(8)
L
7
D-A
-
7
Ao7
Vcc
9
8
VDD
(VrefU)
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EXPLANATION OF TERMINALS
(VrefL)
Pin No. Symbol
14
11
13
12
15
2
3
4
5
6
7
10
9
16
8
1
DI
DO
CLK
LD
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
Vcc
GND
VDD
Vss
MITSUBISHI<Dig.Ana.INTERFACE>
M62353P,FP,GP
8-BIT 8CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
LD terminal input high level than latch circuit data load
8-bit D-A converter output terminal
Power supply terminal
Digital and analog common GND
D-A converter upper reference voltage input terminal
D-A converter lower reference voltage input terminal
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
Vcc
9
DI
14
CLK
13
D0
D1
8
............
D0
1
8-BIT
LATCH
8-BIT
R-2R D-A
D2
8
D7
...................................................................................................
12-BIT SHIFT REGISTER
D4
D3
.............................................8
..............................................
D5
D6 D7
D8
D9
D10 D11
ADDRESS DECODER
21
3
5 6 7
4
............
D0
8-BIT
LATCH
8-BIT
R-2R D-A
--
GND
16
D0
11
LD
12
8
D7
8
VDD
(VrefU)
15
Ao1
MITSUBISHI
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10
Ao8
1
VSS
2
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