Mitsubishi M62352P, M62352GP, M62352FP Datasheet
MITSUBISHI<Dig.Ana.INTERFACE>
input/output.
display.
D0D7123456D8
9
10
-
M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
DESCRIPTION
The M62352 is an integrated circuit semiconductor of CMOS
structure with 12 channels of built-in D-A converters with
output buffer operational amplifiers.
The 3-wire serial interface method is used for the transfer
format mum wiring.
It is able to cascading serial use with Do terminal.
The output buffer operational amplifier operates in the whole
voltage range from power supply to ground for both
FEATURES
•12bit serial data input(3-wire serial data transfer method)
•Highly stable output buffer operational amplifier allow operation
in the all voltage range from power supply to ground.
APPLICATION
Adjustment/control of industrial or home-use electronic
equipment,such as VTR camera,VTR set,TV,and CRT
PIN CONFIGURATION (TOP VIEW)
Vss
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
Ao9
VDD
1
2
3
4
5
7
(VrefL)
Ao10
(VrefU)
Outline 20P4B(P)
20P2N-A(FP)
20P2E-A(GP)
20
GND
19
Ao2
18
Ao1
17
DI
16
CLK
156
LD
14
DO
Ao12
138
Ao11
129
1110
Vcc
BLOCK DIAGRAM
GND
20
8-BIT
R-2R D-A
Ch2
8-BIT
LATCH
.....
(12)
8-BIT
LATCH
Ch3
8-BIT
R-2R D-A
BUFFER
OP AMP
1
Vss
(VrefL)
Ao2
Ao1
19
-
-
-
D-A
1
4
2
Ao3 Ao4
18
L
L
D-A
-
3
DI
CLK
17 16
12-BIT SHIFT REGISTER
(8)
L
5
D-A
-
4
Ao5
L
6
D-A
-
5
Ao6
LD Do Ao12 Ao11
15
ADDRESS
DECODER
(12)
L
7
D-A
-
6
Ao7 Ao8 Ao9
14 13 12
D11
.....
L
8
D-A
-
12 11
9
7
D-A
L
L
D-A
-
8
-
D-A
L
(12)
L
10
D-A
-
9
Ao10 VDD
Vcc
11
10
(VrefU)
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1
EXPLANATION OF TERMINALS
(VrefL)
Pin No. Symbol
17
14
16
15
18
19
2
3
4
5
6
7
8
9
12
13
11
20
10
1
DI
DO
CLK
LD
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
Ao9
Ao10
Ao11
Ao12
Vcc
GND
VDD
Vss
MITSUBISHI<Dig.Ana.INTERFACE>
M62352P,FP,GP
8-BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS
Function
Serial data input terminal
Serial data output terminal
Serial clock input terminal
LD terminal input high level than latch circuit data load
8-bit D-A converter output terminal
Power supply terminal
Digital and analog common GND
D-A converter upper reference voltage input terminal
D-A converter lower reference voltage input terminal
BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS
Vcc
11
DI
17
CLK
18
D0
D1
D2
8
............
D0
8-BIT
LATCH
8-BIT
R-2R D-A
-
12
D7
...................................................................................................
12-BIT SHIFT REGISTER
D4
D3
..............................................12
..............................................
D5
D6 D7
D8
D9
D10 D11
ADDRESS DECODER
...............
3
21
............
D0
8-BIT
LATCH
8-BIT
R-2R D-A
-
GND
20
124
D7
14
15
D0
LD
10
VDD
(VrefU)
18
Ao10
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13
Ao12
1
VSS
2
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