Mitsubishi M56693GP, M56693FP Datasheet
MITSUBISHI <CONTROL / DRIVER IC>
)
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M56693 is a semiconductor integrated circuit that has a builtin, 32-bit shift register and a latch of CMOS structure with serial
input and serial/parallel output, and a 32-bit totem-pole-type
parallel output driver of high pressure proof DMOS structure.
Employed are BI-CMOS and high pressure proof DMOS
processing technology.
FEATURES
● Serial input–serial/parallel output
● Cascade connections possible through serial output
● Latch circuit included for each stage
● Driver supply voltage: VH=120V
● Operating temperature: -20 – 75°C
APPLICATION
Vacuum Fluorescent Display ANODE DRIVER
FUNCTION
The M56693 comprises a 32-bit D type flip-flop with a 32 latches
connected to its output.
In accordance with truth table 1, inputting data to SIN and clock
pulse to CLK allows SIN signal to be put into the internal shift
register when the clock changes from “H” to “L”, and
simultaneously shift register data to be shifted sequentially.
Serial output SOUT is used by connecting to the next stage
M56693 SIN when more than one M56693 is used to expand bits
in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT is turned to “L”. Driver output HVOn allows data
from the latch to be output if BLK input is turned to “L”, and “L” to
be output if BLK input is turned to “H”, irrespective of data from the
latch.
PIN CONFIGURATION(TOP VIEW
HVO22
HVO21
HVO20
HVO19
HVO18
HVO17
HVO16
HVO15
HVO14
HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO
PGND
N.C
N.C
HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO32
3332313029282726252423
34
35
36
37
38
39
40
41
42
32
43
44
M56693FP
123456789
VH
VDD
N.C
LGND
SOUT
Outline 44P6N-A (FP)
HVO19
HVO18
HVO20
HVO21
HVO22
35
34
36
37
38
39
40
41
42
43
44
45
46
47
48
1
PGND
333231302928272625
M56693GP
2345678
H
V
VDD
LGND
SOUT
CLK
HVO17
CLK
LAT
HVO16
LAT
BLK
HVO15
BLK
SIN
HVO14
9
SIN
HVO13
10
VH
HVO13
10
H
V
HVO12
22
21
20
19
18
17
16
15
14
13
12
11
PGND
HVO12
N.C
11
12
1
HVO
PGND
HVO11
HVO10
HVO 9
HVO 8
HVO 7
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
HVO 1
24
23
22
21
20
19
18
17
16
15
14
13
N.C
HVO11
HVO10
HVO 9
HVO 8
HVO
N.C
HVO 6
HVO 5
HVO 4
HVO 3
HVO 2
7
Outline 48P6D-A (GP)
N.C: no connection
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
↓
BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56693GP)
14
Q
VDD
BLK
(4)
(8)
12
(12) (13) (14)
Output
protect
circuit
3
8
Q
13
Q
MITSUBISHI <CONTROL / DRIVER IC>
M56693FP/GP
32HVO31HVO30HVO 3HVO 2HVO 1
HVO
42 4341
(46) (47)
Q
(48)
1
10
11
44
Q
Q
VH
(2)(10)
PGND
(1)(11)
LAT
SIN
CLK
(7)
(9)
(6)
L
7
9
D
T
6
L
D
Q
D
T
TRUTH TABLE
Truth table 1. Shift register section
CLK
H or L
Shift register operation
Truth table 2. Latch and driver sections
L
D
Q
D
Q
D
T
DATA is shifted.
No changes.
L
D
T
L
D
Q
D
T
L
D
Q
D
LGND
5
(5)
Q
D
2
SOUT
(3)
T
N.C
4
(18)(24)(25)
(37)(38)
HVOnDn LAT BLK
X
H
L
X
X
H
H
L
H
L
L
L
Output all “L”
H
L
Latch’s data output.
Dn=nth bit DFF retention data
HVOn=nth bit driver output
L=“L” level
H=“H” level
X=“L” level or “H” level
Loading...