Mitsubishi M54974P Datasheet
MITSUBISHI <CONTROL / DRIVER IC>
)
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M54974P is a semiconductor integrated circuit consisting of 12
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 12 bipolar drivers at the parallel outputs.
FEATURES
● Serial input and serial or parallel output
● Serial output enables cascade connection
● Built-in latch for each stage
● Enable input provides output control
● Low supply current (standby current ICC≤10µA)
● Serial I/O level is compatible with typical CMOS devices
● Driver features: High withstand voltage (BVCEO≥30V)
Capable of large drive currents (IO(max)=300mA)
● Wide operating temperature range Ta=-20 – +75°C
APPLICATION
Dot drivers for thermal print heads. Serial/parallel conversion.
Drivers for relay and solenoids.
FUNCTION
The M54974P consists of 12 stages of D-type flip flops connected
to 12 latches.
Data is input to serial input S-IN, and clock pulses are applied to
clock input T. When the clock changes from low to high, the input
data enters the first shift register and data already in the shift
PIN CONFIGURATION(TOP VIEW
Serial output
Latch input
Enable input
Parallel outputs
Driver GND
Parallel outputs
S-OUT
LATCH
EN
O12
O11
P-GND
O10
O9
O8
O7
O6
←
1
→
2
→
3
←
4
←
7
8
←
←
←
12
←
13
←
14
M54974P
28
27
←
26
←
25
245
236
22
21
209
→
1910
→
1811
→
17
→
16
→ O5
15
Outline 28P4B
registers is shifted sequentially.
The serial output S-OUT is used to connect multiple M54974Ps to
expand the number of parallel outputs. S-OUT is connected to S-IN
of the next stage.
When the clock pulse changes from low to high, latch input
(LATCH) is high and output enable input (EN) is low the serial input
data at S-IN appears at output O1 and the other data already
CC
L-V
L-GND
S-IN
T
CC
P-V
P-GND
O1
O2
O3
O4
Logic power
supply
Logic GND
Serial input
Clock
Output power
supply
Driver GND
Parallel outputs
BLOCK DIAGRAM
6
EN
LATCH
S-IN
Clock
7
8
9
L-VCC
3
L-V
2
26
T
25
P-GND
Driver GND
Enable input
Latch input
Serial input
Parallel outputs
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
19
18 17 16 15 14 13 12 11 10 5 4
20
21
P-GND
Driver GND
22
23
P-VCC
24
Output power supply
CC
L-V
23
CC
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
L D
L D
L D
L D
L D
L D
L D
L D
L D
L D
L D
L D
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
Logic power supply
L-GND
27
Logic GND
S-OUT
1
Serial output
MITSUBISHI <CONTROL / DRIVER IC>
M54974P
Bi-CMOS 12-BIT SERIAL-INPUT LATCHED DRIVER
present is shifted sequentially to outputs O2 through O12.
The parallel outputs are inverted.
When the latch input is held low, the latch retains the stored data.
When the EN input is high, outputs O1 through O12 all turn off. As
the internal logic is unstable when the power is turned on, the EN
TIMING CHART
Serial input
S-IN
TClock
LATCHLatch input
ENEnable input
O1
O2
O3
O4
O5
input should be kept high (setting the outputs O1 through O12 off)
until input data is set and the internal logic is initialized.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
output driver circuits O1 through O12 which employ bipolar
transistors capable of large drive currents.
Parallel outputs
O6
O7
O8
O9
O10
O11
O12
S-OUTSerial output
* The shaded area shows the unstable state.
Loading...