The M54972 is a semiconductor integrated circuit consisting of 8
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 8 bipolar drivers at the parallel outputs.
FEATURES
●Serial input and serial or parallel output
●Serial output enables cascade connection
●Built-in latch for each stage
●Enable input provides output control
●Low supply current (standby current ICC ≤ 10µA)
●Serial I/O level is compatible with typical CMOS devices
●Driver features: High withstand voltage (BVCEO ≥ 30V)
Capable of large drive currents (IO(max)=300mA)
Low output saturation voltage VOL < 0.6V at lo=300mA
●Wide operating temperature range Ta=-20 – +75°C
APPLICATION
Dot drivers for thermal print heads. Serial/parallel conversion.
Drivers for relays and solenoids.
FUNCTION
The M54972 consists of 8 stages of D-type flip flops connected to
8 latches.
Data is input to serial input S-IN, and clock pulses are input to
clock input T. When the clock changes from low to high, the input
data enters the first shift register and data already in the shift
registers is shifted sequentially.
The serial output S-OUT is used to connect multiple M54972 to
expand the number of parallel outputs. S-OUT is connected to S-IN
of the next stage.
PIN CONFIGURATION (TOP VIEW)
S-IN
L-GND
V
S-OUT
LATCH
EN
P-GND
T
→
1
→
2
M54972P/FP
3
CC
4
←
→
→
Outline
16P4(P)
Clock
Serial input
Logic GND
Power supply
Serial output
Latch input
Enable input
Driver GND
16P2N-A(FP)
For parallel output. When the clock pulse changes from low to
high, latch input (LATCH) is high and output enable input (EN) is
low the serial input data at S-IN appears at output O1 and the other
data already present is shifted sequentially to outputs O2 through
O8.
The parallel outputs are inverted.
When the latch input is held low, the latch retains the stored data.
When the EN input is high, outputs O1 through O8 all turn off. As
the internal logic is unstable when the power is turned on, the EN
input should be kept high (setting outputs O1 through O8 off) until
input data is set and the internal logic is initialized.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
output driver circuits O1 through O8 which employ bipolar
transistors capable of large drive currents.
O1
→
16
O2
→
15
O3
→
14
→
O4
13
→
125
→
116
→
107
→
98
Parallel outputs
O5
O6
O7
O8
BLOCK DIAGRAM
Power supply
CC
V
ENEnable input
LATCHLatch input
S-INSerial input
Parallel outputs
O1
O2
O3
O4
O5
O6
O7
O8
161514131211109
4
7
Q
Q
Q
Q
Q
Q
Q
Q
L D
L D
L D
L D
L D
L D
L D
L D
6
2
1
TClock
3
L-GND
Logic GND
QTD
QTD
QTD
QTD
QTD
QTD
QTD
QTD
8
5
Driver GNDP-GND
Serial outputS-OUT
M54972P/FP
TIMING CHART
MITSUBISHI <CONTROL / DRIVER IC>
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
Serial input
Parallel outputs
LATCHLatch input
S-OUTSerial output
S-IN
TClock
ENEnable input
O1
O2
O3
O4
O5
O6
O7
O8
∗
The shaded area shows the unstable state.
INPUT/OUTPUT CIRCUIT DIAGRAM
1
3
Inputs with pullup resistors
(EN, LATCH)
RIN
Serial output
(S-OUT)
VCC
L-GND
VCC
2
4
Inputs with pulldown resistors
(T, S-IN)
RIN
Parallel outputs
(O1 – O8)
V
CC
VCC
L-GND
L-GND
P-GND
L-GND
M54972P/FP
MITSUBISHI <CONTROL / DRIVER IC>
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
ABSOLUTE MAXIMUM RATINGS (Ta=-20 to 75°C, unless otherwise noted)
SymbolRatingsUnitParameterConditions
VCC
VI
VO
IO
Pd
Topr
Tstg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
S-OUT
O1 – O8 : OFF
O1 – O8 : ON
T
a=25°C
M54972P
M54972FP
RECOMMENDED OPERATING CONDITION
Symbol
VCC
VO
IO
Parameter
Supply voltage
Applied output voltage
Output current (per circuit)
O1 – O8 : OFF
O1 – O8 : ON, Duty cycle < 35%
O1 – O8 : ON, Duty cycle < 70%
O1 – O8 : ON, Duty cycle < 15%
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input resistance
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
Low-level output voltage
Output leak current
Supply current
T, S-IN
EN, LATCH
S-OUT
S-OUT
S-OUT
S-OUT
O1 – O8
O1 – O8
T
a=-20 – 75°C, VCC=4 – 6V
VIH=5V
V
IL=0V
|IO|≤1µA
OH=4.5V
V
VOL=0.4V
I
OL=200mA
I
OL=300mA
V
O=30V (O1 – O8: OFF)
Input: open, All driver outputs: OFF
One driver output is ON.
Test conditionsUnitParameter
-0.5 – +8
-0.5 – V
CC+0.5
-0.5 – V
CC+0.5
-0.5 – +30
300
1.25
0.8
-20 – 75
-55 – 125
Limits
Min.Typ.Max.
456
30
300
200
200
Limits
Min.Typ.Max.
0.7V
CC
0
V
CC
0.3VCC
100
-100
50
4.9
0.1
-100
400
0.5
0.6
50
10
7.5
V
V
V
mA
W
°C
°C
Unit
V
V
mA
V
V
µA
µA
kΩ
V
V
µA
µA
V
V
µA
µA
mA
TIMING REQUIREMENTS (Ta=-20 to 75°C, unless otherwise noted)
Symbol
f(T)
tw(T)
tw(L)
tsu
th
td(T-L)
tr(T)
tf(T)
Parameter
Clock frequency
Clock pulse width
Latch pulse width
Data setup time
Data hold time
Clock-latch time
Clock pulse rise time
Clock pulse fall time
Low-to-high-level output propagation time
From input T to output S-OUT
High-to-low-level output propagation time
From input T to output S-OUT
Low-to-high-level output propagation time
From input T to output O
High-to-low-level output propagation time
From input T to output ON
Low-to-high-level output propagation time
From input EN to output ON
High-to-low-level output propagation time
From input EN to output ON
Parameter
N
VIH=5V
VIL=0V
RL(S-OUT)=∞
RL(ON)=100Ω
(N=1–8)
CL=15pF
90%
90%
10%
tf(T)
Limits
Min.Typ.Max.
0.3
0.3
10
5
10
5
Unit
µs
µs
µs
µs
µs
µs
TEST CIRCUIT
PG
TIMING CHART
Serial output
Enable input
Output
Clock
Input
50Ω
S-OUT
T
EN
ON
CC
V
M54972P/FP
2.5V
tPLH
The input waveform:
tr ≤ 20ns, tf ≤ 20ns
RL
Output
CL
2.5V
tPHL
2.5V
t
PLH
2.5V
2.5V
The capacitance C
wiring capacitance and probe input
capacitance.