The M52342SP is IF signal-processing IC for VCRs and TVs. It
enable the PLL detection system despite size as small as that of
conventional quasi-synchronous VIF/SIF detector, IF/RF AGC, SIF
limiter, FM detector, QIF AGC and EQ AMP.
FEATURES
Video detection output is 2V
•
The package is a 20-pin shrink-DIP, suitable for space saving.
•
The video detector uses PLL for full synchronous detection
•
circuit. It produces excellent characteristics of DG, DP, 920kHz
beat, and cross color.
•
Dynamic AGC realizes high speed response with only single
filter.
•
Video IF and sound IF signal processings are separated from
each other. VCO output is used to obtain intercarrier. This PLL-
SPLIT method and built-in QIF AGC provide good sound
sensitivity and reduces buzz.
•
As AFT output voltage uses the APC output voltage, VCO coil is
not used.
Audio FM demodulation uses PLL system, so it has wide
•
frequency range with no external parts and no adjustment.
. It has built-in EQ AMP.
P-P
APPLICATION
TV sets, VCR tuners
PIN CONFIGURATION (TOP VIEW)
RF AGC DELAYEQ F/B
AFT OUT
RF AGC OUT
QIF DET IN
IF AGC FILTER
AUDIO OUT
VIF IN
VIF IN
GND
NFB
1
2
3
4
Outline 20P2N-A
20
19
18
M52342SP
17
165
156
147
138
129
1110
APC FILTER
VIDEO OUT
Vreg. OUT
VCO COIL
VCO COIL
Vcc
QIF OUT
AFT SW/NPSW
LIMITER IN
RECOMMENDED OPERATING CONDITION
In case of V
Supply voltage range....................................................4.75 to 5.25V
VosSIF detection output 1TP13 VIF IN SG15 0−5 SW7=2 94100 106dBµ
V1AF output DC voltage1TP10 SIF IN SG20−−5 1.6 2.2 2.8V
VoAF1AF output (4.5MHz)1TP10 SIF IN SG16−−5 320560 800mVrms
VoAF2AF output (5.5MHz)1TP10 SIF IN SG21 −−0 255450 645mVrms
THD AF1
THD AF2
LIM1
LIM2
AF output distortion
(4.5MHz)
AF output distortion
(5.5MHz)
Limiting sensitivity
(4.5MHz)
Limiting sensitivity
(5.5MHz)
1TP10 SIF IN SG16 −−5− 0.2 0.9%
1TP10 SIF IN SG21 −−0− 0.2 0.9%
1TP10 SIF IN
1TP10 SIF IN
SG17
−−5− 42 55dBµ
SG19
SG22
−−0− 42 55dBµ
SG24
AMR1AM rejection (4.5MHz)1TP10 SIF IN SG18 −−5 55 62−dB
AMR2AM rejection (5.5MHz)1TP10 SIF IN SG23 −−0 55 64−dB
AF S/N 1 AF S/N (4.5MHz)1TP10 SIF IN SG20 −−5 55 62−dB
AF S/N 2 AF S/N (5.5MHz)1TP10 SIF IN SG25 −−0 55 64−dB
RINSSIF input resistance2TP7− 1.5−kΩ
CINSSIF input capacitance2TP7− 4−pF
Control section
QIFQIF control1TP7−−
C
Vari
able
−−
SW7=2
− 0.7 1.0V
PIN12 VOL TAGE CONTROL
Pin12 voltage (V)AFAFT
0 to 2.3
2.7 to 5.0
3
0 to 0.6
1.0 to 2.3DEFEAT
2.7 to 4.0
4.4 to 5.0DEFEAT
PAL
NTSC
NORMAL
NORMAL
MITSUBISHI ICs (TV)
M52342SP
PLL-SPLIT VIF/SIF IC
ELECTRICAL CHARACTERISTICS TEST METHOD
Video S/N
Input SG2 into VIF IN and measure the video out (Pin 18) noise in
r.m.s at TP18B through a 5MHz (-3dB) L.P.F.
S/N=20 log
0.7×Vo det
NOISE
BW Video band width
1. Measure the 1MHz component level of EQ output TP18A with a
spectrum analyzer when SG3 (f2=57.75MHz) is input into VIF
IN. At that time, measure the voltage at TP8 with SW8, set to
position 2, and then fix V8 at that voltage.
2. Reduce f2 and measure the value of (f2-f0) when the (f2-f0)
component level reaches -3dB from the 1MHz component level
as shown below.
TP18
-3dB
(dB)
V3 RF AGC operating voltage
Input SG8 into VIF IN, and gradually reduce Vi and then measure
the input level when RF AGC output TP3 reaches 1/2 V
CC, as
shown below.
TP3
Voltage
3H
V
1/2VCC
V
3L
Vi
Vi (dBµ)
CL-U Capture range
1. Increase the frequency of SG9 until the VCO is out of lockedoscillation.
2. Decrease the frequency of SG9 and measure the frequency fU
when the VCO locks.
CL-U=fU-58.75 (MHz)
1MHz
BW
( f2 - f0 )
VIN MIN Input sensitivity
Input SG4 (Vi=90dBµ) into VIF IN, and then gradually reduce Vi and
measure the input level when the 20kHz component of EQ output
TP18A reaches -3dB from Vo det level.
VIN MAX Maximum allowable input
1. Input SG5 (Vi=90dBµ) into VIF IN, and measure the level of the
20kHz component of EQ output.
2. Gradually increase the Vi of SG and measure the input level
when the output reaches -3dB.
GR AGC control range
GR=VIN MAX-VIN MIN (dB)
CL-L Capture range
1. Decrease the frequency of SG9 until the VCO is out of lockedoscillation.
2. Increase the frequency of SG9 and measure the frequency fL
when the VCO locks.
CL-L=58.75-fL (MHz)
CL-T Capture range
CL-T=CL-U+CL-L (MHz)
µ AFT sensitivity, V
2H Maximum AFT voltage, V2L Minimum AFT
voltage
1. Input SG10 into VIF IN , and set the frequency of SG10 so that
the voltage of AFT output TP2 is 3V. This frequency is named
f(3).
2. Set the frequency of SG10 so that the AFT output voltage is 2V.
This frequency is named f (2)
4
MITSUBISHI ICs (TV)
M52342SP
PLL-SPLIT VIF/SIF IC
3. IN the graph, maximum and minimum DC voltage are V2H and
V2L, respectively.
TP2
Voltage
3V
V2H
2V
V2L
f (3)f (2)f (MHz)
1000 (mV)
µ =
f (2) - f (3) (kHz)
(mV/kHz)
IM Intermodulation
1. Input SG11 into VIF IN, and measure EQ output TP18A with an
oscilloscope.
2. Adjust AGC filter voltage V8 so that the minimum DC level of the
output waveform is 1.0V.
3. At this time, measure, TP18A with a spectrum analyzer.
The intermodulation is defined as a difference between 920kHz
and 3.58MHz frequency components.
LIM Limiting sensitivity
1. Input SG17 (SG22) into SIF input, and measure the 400Hz
component level of AF output TP10.
2. Input SG19 (SG24) into SIF input, and measure the 400Hz
component level of AF output TP10.
3. The input limiting sensitivity is defined as the input level when a
difference between each 400Hz components of audio output
(TP10) is 30dB, as shown below.
AF S/N
1. Input SG20 (SG25) into SIF input, and measure the output noise
level of AF output TP1. This level is named VN.
2. S/N is;
C
QIF QIF control
S/N=20log
VoAF (mVr.m.s)
VN (mVr.m.s)
(dB)
Lower the voltage of V7, and measure the voltage of V7 when DC
voltage of TP13 begins to change.
THE NOTE IN THE SYSTEM SETUP
M52342SP has 2 power supply pins of Vcc (pin 14) and Vreg. OUT
(pin 17). Pin 14 is for AFT output, RF AGC output circuits and 5V
regulated power circuit and Pin 17 is for the other circuit blocks.
In case M52342SP is used together with other ICs like VIF
operating at more than 5V, the same supply voltage as that of
connected ICs is applied to VCC and Vreg. Out is opened. The other
circuit blocks, connected to Vreg. OUT are powered by internal 5V
regulated power supply.
In case the connecting ICs are operated at 5V, 5V is supplied to
both VCC and Vreg.OUT.
LOGIC T ABLE
AFAFT
10k “H”
10k “L”
20k “H”
20k “L”NORMAL
20k “H”
20k “L”NORMAL
NTSC
PAL
DEFEAT
DEFEAT
Audio output
(mVrms)
30dB
Audio output while
SG17 (SG22) is input
Audio output while
SG19 (SG24) is input
SIF input
(dBµ)
AMR AM Rejection
1. Input SG18 (SG23) into SIF input, and measure the output level
of AF output TP10. This level is named VAM.
2. AMR is;
AMR=20log
VoAF (mVr.m.s)
VAM (mVr.m.s)
(dB)
5
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