Mitsubishi M38C37ECAFP, M38C37ECMFS, M38C37ECMFP, M38C37ECAFS Datasheet

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 38C3 group is the 8-bit microcomputer based on the 740 family core technology. The 38C3 group has a LCD drive control circuit, a 10-channel A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C3 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 38C3 group, refer to the section on group expansion.

FEATURES

●Basic machine-language instructions ....................................... 71

●The minimum instruction execution time............................. 0.5 µs

(at 8MHz oscillation frequency)

●Memory size

ROM ..................................................................4 K to 48 K bytes

RAM ................................................................. 192 to 1024 bytes

●Programmable input/output ports ............................................. 57

●Software pull-up/pull-down resistors

..................................................... (Ports P0–P8 except Port P5

●Interrupts................................................... 16 sources, 16 vectors

(includes key input interrupt)

●Timers ............................................................8-bit ✕ 6, 16-bit ✕ 1

●A-D converter.................................................10-bit ✕ 8 channels

●Serial I/O ....................................... 8-bit ✕ 1 (Clock-synchronized)

●LCD drive control circuit

Bias ............................................................................ 1/1, 1/2, 1/3

Duty .................................................................... 1/1, 1/2, 1/3, 1/4

Common output .......................................................................... 4

Segment output ........................................................................ 32

●2 Clock generating circuit (connect to external ceramic resonator or quartz-crystal oscillator)

●Power source voltage

In high-speed mode ....................................................4.0 to 5.5 V

In middle-speed mode ................................................2.5 to 5.5 V

In low-speed mode...................................................... 2.5 to 5.5 V

●Power dissipation

In high-speed mode ...........................................................32 mW

(at 8 MHz oscillation frequency)

In low-speed mode..............................................................45 µW

(at 32 kHz oscillation frequency , at 3 V power source voltage)

●Operating temperature range.................................... – 20 to 85°C

APPLICATIONS

Camera, household appliances, consumer electronics, etc.

1)

PIN CONFIGURATION (TOP VIEW)

P20/SEG0

P21/SEG1

64

63

P47/SRDY P46/SCLK1 P45/SOUT

P44/SIN

P43/φ P42/T3OUT P41/T1OUT P40/SCLK2

AV

VREF P67/AN7 P66/AN6 P65/AN5 P64/AN4 P63/AN3 P62/AN2

SS

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

2

1

P60/AN0

P61/AN1

P22/SEG2

P23/SEG3

62

61

P27/SEG7

P25/SEG5

58

60

57

59

P03/SEG11

P00/SEG8

P02/SEG10

54

53

56

55

P07/SEG15

P10/SEG16

P06/SEG14

50

49

52

51

48

47

P05/SEG13

P04/SEG12

P01/SEG9

P26/SEG6

P24/SEG4

M38C34M6AXXXFP

4

3

P56/INT1

P57/INT2

8

5

P55/INT0

9

6

7

P52/PWM1

P54/CNTR1

P53/CNTR0

P51

10

11

RESET

P71/XcOUT

12

P70/XcIN

16

15

XOUT

18

17

VCC

13

14

XIN

VSS

P50/TAOUT

Package type : 80P6N-A

80-pin plastic-molded QFP

P11/SEG17

P12/SEG18

46

19

P87

P86

P16/SEG22

P13/SEG19

P15/SEG21

P17/SEG23

P14/SEG20

45

44

43

42

41

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

22

24

21

23

20

P85

P82

P84

P83

P81

P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 COM0 COM1 COM2 COM3 VL1 VL2 VL3 P80

Fig. 1 M38C34M6AXXXFP pin configuration

Key-on wake-up

INT0–INT

2

CNTR

0

,CNTR

1

T1

OUT,

T3

OUT

φ

Data bus

C P U

AXY

S

PC

H

PCLPS

RESET

V

CC

V

SS

Reset input ( 5 V ) ( 0 V )

R O M

R A M

LCD display

RAM

(16 bytes)

10 16

13

I/O port P5

P4(8)

I/O port P4

I/O port P2

P2(8)

I/O port P1

P1(8)

P6(8)

Output port P3

I/O port P6

P5(8)

I/O port P7

P7(2)

2827263231

30

29

I/O port P0

P0(8)

49

50 51

52 53 54

55

5641 42 43 44 45

46 47

48

57

58

59

60

61

62 63

6467 68 69 70 71 7265

66

12

11

1

2

75 76

77

78

79

80 7374

456789

17

3

Clock generating

circuit

Main

clock

input

X

IN

Main

clock

output

X

OUT

X

COUT

Sub-

clock

output

X

CIN

Sub-

clock

input

SI/O(8)

V

REF

AV

SS

( 0 V )

A-D converter(10)

Timer 1(8) Timer 2(8)

LCD

drive control

circuit

VL1VL2V

L3

COM0COM1COM

2

COM

3

φ

X

CIN

X

COUT

14

15

Timer 3(8) Timer 4(8)

Timer 5(8) Timer 6(8)

P3(8)

33 34

35

36

37

38 39

40

R O M

corrective

circuit

ROM corrective

RAM

(8 bytes)

I/O port P8

P8(8)

18 19 20 21 22 23 24 25

PWM

0,

PWM

1

Timer A(16)

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM

Fig. 2 Functional block diagram

2

PIN DESCRIPTION

Table 1 Pin description (1)

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CC, VSS

V VREF

AVSS

RESET XIN

XOUT

VL1 – VL3

COM0 – COM3

P00/SEG9 – P07/SEG15

P10/SEG16 – P17/SEG23

P20/SEG0 – P27/SEG7

P30/SEG24 – P37/SEG31

P40/SCLK2 P41/T1OUT P42/T3OUT P43/φ P44/SIN,

P45/SOUT, P46/SCLK1, P47/SRDY

Name

Power source Analog reference

voltage Analog power

source Reset input Clock input

Clock output

LCD power source

Common output

I/O port P0

I/O port P1

I/O port P2

Output port P3

I/O port P4

Function

• Apply voltage of 2.5 V to 5.5 V to VCC, and 0 V to VSS.

• Reference voltage input pin for A-D converter .

• GND input pin for A-D converter.

• Connect to VSS.

• Reset input pin for active “L.”

• Input and output pins for the main clock generating circuit.

• Feedback resistor is built in between XIN pin and XOUT pin.

• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.

• Input 0 – VL3 voltage to LCD.

• LCD common output pins.

• COM1, COM2, and COM3 are not used at 1/1 duty ratio.

• COM2 and COM3 are not used at 1/2 duty ratio.

• COM3 is not used at 1/3 duty ratio.

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each port to be individually programmed as either input or output.

• Pull-down control is enabled.

• 8-bit output port.

• CMOS state output.

• Pull-down control is enabled.

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually programmed as either input or output.

• Pull-up control is enabled.

Function except a port function

• LCD segment pins

• Serial I/O function pin

• Timer output pin

• φ output pin

• Serial I/O function pins

3

Table 2 Pin description (2)

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P51

P50/TAOUT P52/PWM1 P53/CNTR0,

P54/CNTR1 P55/INT0,

P56/INT1, P57/INT2

P60/AN0 – P67/AN7

P70/XCOUT, P71/XCIN

P80 – P87

Name

Input port P5

I/O port P5

I/O port P6

I/O port P7

I/O port P8

Function

• 1-bit input pin.

• CMOS compatible input level.

• 7-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually programmed as either input or output.

• Pull-up control is enabled.

• 8-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually programmed as either input or output.

• Pull-up control is enabled.

• 2-bit I/O port.

• CMOS compatible input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually programmed as either input or output.

• Pull-up control is enabled.

• 8-bit I/O port.

• TTL input level.

• CMOS 3-state output structure.

• I/O direction register allows each pin to be individually programmed as either input or output.

• Pull-up control is enabled.

Function except a port function

• Timer A output pin

• PWM1 output (timer output) pin

• External count I/O pins

• External interrupt input pins

• A-D conversion input pins

• Sub-clock generating circuit I/O pins

• Key input (Key-on wake-up) interrupt input pins

4

P ART NUMBERING

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M38C3 4 M 6 A XXX FPProduct

Package type

: 80P6N-A package

FP

: 80D0 package

FS

ROM number Omitted in some types.

A : Standard(Note)

M : M version

ROM/PROM size 1

: 4096 bytes

2

: 8192 bytes

3

: 12288 bytes

4

: 16384 bytes

5

: 20480 bytes

6

: 24576 bytes

7

: 28672 bytes

8

: 32768 bytes

The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.

Memory type ME : Mask ROM version

: EPROM or One Time PROM version

RAM size 0

: 192 bytes

1

: 256 bytes

2

: 384 bytes

3

: 512 bytes

4

: 640 bytes

5

: 768 bytes

6

: 896 bytes

7

: 1024 bytes

9

: 36864 bytes

A

: 40960 bytes

B

: 45056 bytes

C

: 49152 bytes

Fig. 3 Part numbering

Note : Difference between standard and M version

• Standard :

• M version :

Port P50/TA register is set to the output mode during reset and after reset.

Port P5 the direction register is set to the input mode during reset and after reset.

OUT

pin remains set to the input mode until the direction

0

/TA

OUT

pin remains set to the output mode (“L” output) until

5

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 38C3 group as follows.

Memory T ype

Support for mask ROM, One Time PROM, and EPROM versions

Memory Size

ROM/PROM size ................................................ 16 K to 48 K bytes

RAM size............................................................. 512 to 1024 bytes

Memory Expansion Plan

ROM size (bytes)

48K 44K 40K 36K 32K 28K 24K 20K 16K 12K

8K 4K

Planning

Packages

80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP

80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version)

Under development

M38C37ECA/ECM

Under development

M38C34M6A/M6M

M38C33M4

192

Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped the development.

Fig. 4 Memory expansion plan

Currently planning products are listed below.

Table 3 Support products

Product name

M38C34M6AXXXFP M38C37ECAXXXFP M38C37ECAFP M38C37ECAFS M38C34M6MXXXFP M38C37ECMXXXFP M38C37ECMFP M38C37ECMFS

(P) ROM size (bytes)

ROM size for User in ( )

24576 (24446)

49152 (49022)

24576 (24446)

49152 (49022)

256 384 512 640 768 896

RAM size (bytes)

RAM size

(bytes)

640

1024

640

1024

Package

80P6N-A

80D0

80P6N-A

80D0

Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version

1024

As of April 1998

Remarks

6

FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)

The 38C3 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used.

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B

16.

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7 b0

Fig. 5 Structure of CPU mode register

CPU mode register (CPUM (CM) : address 003B

Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns “1” when read) (Do not write “0” to this bit.) Port X 0 : I/O port 1 : X Main clock ( X 0 : Operating 1 : Stopped Main clock division ratio selection bit 0 : f(X 1 : f(X Internal system clock selection bit 0 : X 1 : X

Not available

C

switch bit

CIN

, X

COUT

IN–XOUT

IN

)/2 (high-speed mode)

IN

)/8 (middle-speed mode)

IN-XOUT

selected (middle-/high-speed mode)

CIN-XCOUT

16

)

) stop bit

selected (low-speed mode)

7

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area

The Special Function Register area in the zero page contains control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM size

(bytes)

192 256 384 512 640 768 896 1024

Address

XXXX

00FF 013F 01BF 023F 02BF 033F 03BF 043F

16

16 16 16 16 16 16 16 16

Zero Page

Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special Page

Access to this area with only 2 bytes is possible in the special page addressing mode.

0000

16

SFR area 1

0040

16

RAM

0050 0058

0100

XXXX

LCD display RAM area

16

ROM corrective RAM area

16

(Note 1)

Reserved area

Zero page

ROM area

ROM size

(bytes)

Address YYYY

4096

8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152

Note 1 : This is valid only in mask ROM version.

Fig. 6 Memory map diagram

F000 E000 D000 C000 B000 A000 9000 8000 7000 6000 5000 4000

0440

16

0F00

0FFF

16

16 16

16

16 16 16 16 16 16 16 16 16

Address

ZZZZ

F080 E080 D080 C080 B080 A080 9080 8080 7080 6080 5080 4080

16

16 16

16

16 16 16 16 16 16 16 16 16

ROM

YYYY

ZZZZ

FF00

FFDC

FFFE FFFF

16 16

16

Not used

SFR area 2 (Note 1)

Reserved ROM area

(128 bytes)

Interrupt vector area

Reserved ROM area

Special page

8

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

0000

16

Port P0 direction register (P0D)

0001

16

Port P1 (P1)

0002

16

Port P1 direction register (P1D)

0003

16

Port P2 (P2)

0004

16

Port P2 direction register (P2D)

0005

16

Port P3 (P3)

0006

16

0007

16

Port P4 (P4)

0008

16

Port P4 direction register (P4D)

0009

16

Port P5 (P5)

000A

16

Port P5 direction register (P5D)

000B

16

Port P6 (P6)

000C

16

Port P6 direction register (P6D)

000D

16

Port P7 (P7)

000E

16

Port P7 direction register (P7D)

000F

16

0010

16

Port P8 (P8) Port P8 direction register (P8D)

0011

16

0012

16

0013

16

0014

16

0015

16

PULL register A (PULLA)

0016

16

PULL register B (PULLB)

0017

16

Port P8 output selection register (P8SEL)

0018

16

Serial I/O control register 1 (SIOCON1)

0019

16

Serial I/O control register 2 (SIOCON2)

001A

16

Serial I/O register (SIO)

001B

16

001C

16

001D

16

001E

16

001F

16

0020

Timer 1 (T1) Timer 2 (T2)

0021

16

Timer 3 (T3)

0022

16

Timer 4 (T4)

0023

16

0024

16

Timer 5 (T5) Timer 6 (T6)

0025

16

0026

16

Timer 6 PWM register (T6PWM)

0027

16

Timer 12 mode register (T12M)

0028

16

Timer 34 mode register (T34M)

0029

16

Timer 56 mode register (T56M)

002A

16

φ output control register (CKOUT)

002B

16

Timer A register (low) (TAL)

002C

16

Timer A register (high) (TAH)

002D

16

Compare register (low) (CONAL)

002E

16

Compare register (high) (CONAH)

002F

16

Timer A mode register (TAM)

0030

16

Timer A control register (TACON)

0031

16

A-D control register (ADCON)

0032

16

0033

16

A-D conversion register (low) (ADL) A-D conversion register (high) (ADH)

0034

16

0035

16

0036

16

0037

16

Segment output enable register (SEG)

0038

16

LCD mode register (LM)

0039

16

Interrupt edge selection register (INTEDGE)

003A

16

CPU mode register (CPUM)

003B

16

Interrupt request register 1 (IREQ1)

003C

16

Interrupt request register 2 (IREQ2)

003D

16

Interrupt control register 1 (ICON1)

003E

16

Interrupt control register 2 (ICON2)

003F

16

ROM correct enable register 1 (Note)

0F01

16

ROM correct high-order address register 1 (Note)

0F02

16

ROM correct low-order address register 1 (Note)

0F03

16

ROM correct high-order address register 2 (Note)

0F04

16

0F05

16

ROM correct low-order address register 2 (Note) ROM correct high-order address register 3 (Note)

0F06

16

ROM correct low-order address register 3 (Note)

0F07

16

ROM correct high-order address register 4 (Note)

0F08

16

ROM correct low-order address register 4 (Note)

0F09

16

Note: This register is valid only in mask ROM version.

Fig. 7 Memory map of special function register (SFR)

0F0A

16

ROM correct high-order address register 5 (Note)

0F0B

16

ROM correct low-order address register 5 (Note)

0F0C

16

ROM correct high-order address register 6 (Note)

0F0D

16

ROM correct low-order address register 6 (Note)

0F0E

16

ROM correct high-order address register 7 (Note) ROM correct low-order address register 7 (Note)

0F0F

16

0F10

16

ROM correct high-order address register 8 (Note) ROM correct low-order address register 8 (Note)

0F11

16

9

I/O PORTS [Direction Registers (ports P2, P4, P5

0, P52–P57,

and P6–P8)]

The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

[Direction Registers (ports P0 and P1)]

Ports P0 and P1 have direction registers which determine the input/ output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port becomes an input port. When “1” is written to that port, that port becomes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used.

Pull-up/Pull-down Control

By setting the PULL register A (address 001616) or the PULL register B (address 0017

16), ports except for ports P3 and P51 can control

either pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports.

Port P8 Output Selection

Ports P80 to P87 can be switched to N-channel open-drain output by setting “1” to the port P8 output selection register.

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7 b0

Note : The contents of PULL register A and PULL register B

do not affect ports programmed as the output ports.

Fig. 8 Structure of PULL register A and PULL register B

b7 b0

Fig. 9 Structure of port P8 output selection register

PULL register A (PULLA : address 0016

P00–P07 pull-down P1

0

–P17 pull-down

0

–P27 pull-down

P2 Not used P7

0

, P71 pull-up

P8

0

–P87 pull-up

Not used (return “0” when read)

PULL register B (PULLB : address 0017

P40–P43 pull-up P4

4

–P47 pull-up

P5

0

, P52, P53 pull-up

4

–P57 pull-up

P5 P6

0

, P63 pull-up

P6

4

–P67 pull-up

Not used (return “0” when read)

0 : Disable 1 : Enable

Port P8 output selection register (P8SEL : address 0018

0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)

16

)

16

)

16)

Table 4 List of I/O port function (1)

P00/SEG8 –

Name

Port P0

Input/Output

Input/Output,

P07/SEG15

P10/SEG16 –

Port P1

Input/Output,

P17/SEG23

P20/SEG0 – P27/SEG7

P30/SEG24 – P37/SEG31

Port P2

Port P3

Input/Output,

individual bits

10

port unit

Output,

I/O format

CMOS compatible input level CMOS 3-state output

CMOS compatible input CMOS 3-state output

CMOS 3-state output

Non-port function

LCD segment output

Related SFRs

PULL register A Segment output enable register

Segment output enable register

Ref. No.

(1)

(2)

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 5 List of I/O port function (2)

P40/SCLK2

P41/T1OUT

P42/T3OUT

P43/φ

P44/SIN P45/SOUT P46/SCLK1 P47/SRDY

P50/TAOUT

P51

P52/PWM1

P53/CNTR0 P54/CNTR1

P55/INT0 P56/INT1 P57/INT2

P60/AN0 – P67/AN7

P70/XCIN P71/XCOUT

P80 – P87

COM0 – COM

Notes 1: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from V

2: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double function ports as function I/O ports, refer to the

applicable sections.

3

Name

Port P4

Port P5

Port P6

Port P7

Port P8

Common

Input/Output

Input/Output, individual bits

Input

Input/Output, individual bits

Output

I/O format

CMOS compatible input level CMOS 3-state output

CMOS compatible input level

CMOS compatible input level CMOS 3-state output

LCD common output

Non-port function

Serial I/O function I/O

Timer output

φ clock output

Serial I/O function I/O

Timer A output

PWM output

External count I/O

External interrupt input

A-D converter input

Sub-clock generating circuit I/O

Key input (key-on wake-up) interrupt input

CC to VSS through the input-stage gate.

Serial I/O control registers 1, 2 PULL register B

Timer 12 mode register PULL register B

Timer 34 mode register PULL register B

φ output control register PULL register B

Serial I/O control registers 1, 2 PULL register B

Timer A mode register Timer A control reigster PULL register B

Timer 56 mode register PULL register B

Interrupt edge selection register PULL register B

A-D control register PULL register B

CPU mode register PULL register A

Interrupt control register 2 PULL register A

LCD mode register

Related SFRs

Ref. No.

(3)

(4)

(5)

(6) (7) (8) (9)

(10)

(11)

(4)

(12)

(13)

(14) (15)

(17)

(16)

11

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1)Ports P0, P1, P2

VL2/V

Segment output enable bit

Direction register

Data bus

Note : Port P0, P1 direction registers are only bit 0.

(3)Port P4

P-channel output disable bit

Serial I/O mode selection bit

Port latch

0

Direction register

VL1/V

(Note)

Segment output enable bit

L3

SS

Pull-down control

Pull-up control

(2)Port P3

Segment output enable bit

Data bus Port latch

(4)Ports P41, P42, P5

Timer 1 output selection bit Timer 3 output selection bit Timer 6 output selection bit

Direction register

VL2/V

L3

VL1/V

SS

Pull-down control

Segment output enable bit

2

Pull-up control

Data bus

(5)Port P4

Data bus

Port latch

Serial I/O clock output

3

Direction register

Port latch

φ output control bit

Fig. 10 Port block diagram (1)

Data bus

(6)Port P4

Pull-up control

Data bus

φ

Port latch

Timer 1 output Timer 3 output Timer 6 output

4

Direction register

Port latch

Pull-up control

Serial I/O input

12

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(7)Port P4

Data bus

(9)Port P4

Data bus

5

P-channel output disable bit

Serial I/O port selection bit

Serial I/O output

7

S

RDY

output enable bit

Direction register

Port latch

Direction register

Port latch

Pull-up control

(8)Port P4

Data bus

(10)Port P5

Data bus

6

P-channel output disable bit

Serial I/O mode selection bit

Direction register

Serial I/O clock output

0

Timer A output enable bit

Direction register

Pull-up control

Port latch

Serial I/O clock input

Pull-up control

(Note)

Port latch

Serial I/O ready output

(11)Port P5

1

Data bus

Note: The initihal value of M version becomes “1” (output).

Fig. 11 Port block diagram (2)

Timer A output

(12)Ports P53–P5

Data bus

7

Direction register

Port latch

INT0–INT2 interrupt input

0

,CNTR1 interrupt input

CNTR

Pull-up control

13

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(13)Port P6

Data bus

(15)Port P7

Data bus

Direction register

Port latch

1

Port Xc switch bit

Direction register

Port latch

Pull-up control

A-D conversion input

Analog input pin selection bit

Port selection • pull-up control

(14)Port P7

Data bus

(16)COM0–COM

0

Port selection • pull-up control

Port Xc switch bit

Direction register

Port latch

Sub-clock generating circuit input

3

V

L3

V

L2

V

L1

The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value.

(17)Port P8

P-channel output disable bit

Direction register

Data bus

Key input (key-on wake-up) interrupt input

Port latch

Fig. 12 Port block diagram (3)

Port P7

Port Xc switch bit

Pull-up control

Oscillator

0

14

INTERRUPTS

Interrupts occur by sixteen sources: six external, nine internal, and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt Operation

By acceptance of an interrupt, the following operations are automatically performed:

1.The processing being executed is stopped.

2.The contents of the program counter and processor status register are automatically pushed onto the stack.

3.The interrupt disable flag is set and the corresponding interrupt request bit is cleared.

4.The interrupt jump destination address is read from the vector table into the program counter.

■Notes on Interrupts

When the active edge of an external interrupt (INT or CNTR1) is set or an vector interrupt source where several interrupt source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence:

(1) Disable the interrupt. (2) Change the active edge in interrupt edge selection register. (3) Clear the set interrupt request bit to “0.” (4) Enable the interrupt.

0 – INT2, CNTR0

15

Table 6 Interrupt vector addresses and priority

Interrupt Source Reset (Note 2)

INT0

INT1

INT2

Serial I/O

Timer A Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 CNTR0

CNTR1

Key input (Keyon wake-up)

A-D conversion

BRK instruction

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Priority

Vector Addresses (Note 1)

High

1

FFFD16

2

FFFB16

3

FFF916

4

FFF716

5

FFF516

6

FFF316

7

FFF116

8

FFEF16

9

FFED16 10 11 12 13

14

15

16

17

FFEB16

FFE916 FFE716 FFE516

FFE316

FFE116

FFDF16

FFDD16

Low FFFC16 FFFA16

FFF816

FFF616

FFF416

FFF216 FFF016 FFEE16

FFEC16

FFEA16 FFE816 FFE616 FFE416

FFE216

FFE016

FFDE16

FFDC16

At reset At detection of either rising or falling edge of

INT

0 intput

At detection of either rising or falling edge of INT1 input

At detection of either rising or falling edge of INT2 input

At completion of serial I/O data transmit/receive

At timer A underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At timer 5 underflow At timer 6 underflow At detection of either rising or falling edge of

CNTR0 input At detection of either rising or falling edge of

CNTR1 input At falling of port P8 (at input) input logical level

AND At completion of A-D conversion

At BRK instruction execution

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt Request

Generating Conditions

MITSUBISHI MICROCOMPUTERS

38C3 Group

Remarks

Non-maskable External interrupt

(active edge selectable) External interrupt

(active edge selectable) Valid when serial I/O is selected

STP release timer underflow

External interrupt (active edge selectable)

External interrupt (falling valid)

Valid when A-D conversion interrupt is selected

Non-maskable software interrupt

16

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 13 Interrupt control

b7 b0

Interrupt edge selection register

16

(INTEDGE : address 003A

)

INT0 interrupt edge selection bit INT

1

interrupt edge selection bit

2

interrupt edge selection bit

INT Not used (return “0” when read) CNTR

0

active edge switch bit

CNTR

1

active edge switch bit

Interrupt request register 1

16

(IREQ1 : address 003C

)

INT0 interrupt request bit INT

1

interrupt request bit

2

interrupt request bit

INT Serial I/O interrupt request bit Timer A interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit

BRK instruction

Reset

0 : Falling edge active 1 : Rising edge active

0 : Falling edge active, rising edge count 1 : Rising edge active, falling edge count

b7 b0

0 : No interrupt request issued 1 : Interrupt request issued

Interrupt request

Interrupt request register 2 (IREQ2 : address 003D

16

)

Timer 4 interrupt request bit Timer 5 interrupt request bit Timer 6 interrupt request bit CNTR

0

interrupt request bit

1

interrupt request bit

CNTR Key input interrupt request bit AD conversion interrupt request bit Not used (returns “0” when read)

b7 b0

Interrupt control register 1

(ICON1 : address 003E

INT0 interrupt enable bit

1

interrupt enable bit

INT INT

2

interrupt enable bit Serial I/O interrupt enable bit Timer A interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit

Fig. 14 Structure of interrupt-related registers

b7 b0

16

)

Interrupt control register 2

(ICON2 : address 003F

16

)

Timer 4 interrupt enable bit Timer 5 interrupt enable bit Timer 6 interrupt enable bit CNTR

0

interrupt enable bit

1

interrupt enable bit

CNTR Key input interrupt enable bit AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit)

0 : Interrupts disabled 1 : Interrupts enabled

17

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Key Input Interrupt (Key-on Wake-Up)

A key input interrupt request is generated by applying “L” level to any pin of port P8 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example

Port PXx “L” level output

PULL register A Bit 5 = “1”

P8

7

output

6

output

5

output

✽

✽ ✽

✽ ✽✽

Port P8 latch

of using a key input interrupt is shown in Figure 15, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P8

Port P8 direction register = “1”

7

6

5

7

Port P8 direction register = “1”

6

5

Port P8 direction register = “1”

0–P83.

Key input interrupt request

P8

4

output

P8

3

input

2

input

1

input

0

input

4

Port P8

✽ ✽✽

Port P8 latch

✽ ✽✽

Port P8 latch

✽ ✽✽

Port P8 latch

✽ ✽✽

Port P8 latch

✽

✽ ✽

Port P8 latch

direction register = “1”

4

Port P8

3

direction register = “0”

3

Port P8

2

direction register = “0”

2

Port P8

1

direction register = “0”

1

0

Port P8 direction register = “0”

0

Port P8 Input reading circuit

Fig. 15 Connection example when using key input interrupt and port P8 block diagram

18

✽ P-channel transistor for pull-up

✽ ✽ CMOS output buffer

TIMERS 8-Bit Timer

The 38C3 group has six built-in timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches “00 count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1.” The count can be stopped by setting the stop bit of each timer to “1.” The system clock φ can be set to either the high-speed mode or lowspeed mode with the CPU mode register. At the same time, timer internal count source is switched to either f(X

●Timer 1, Timer 2

The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 is output from the P4 form polarity changes each time timer 1 overflows. The active edge of the external clock CNTR interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to “0,” timer 1 is set to “FF set to “01

16.”

●Timer 3, Timer 4

The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 is output from the P4 form polarity changes each time timer 3 overflows. The active edge of the external clock CNTR interrupt edge selection register.

●Timer 5, Timer 6

The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P5

●Timer 6 PWM1 Mode

Timer 6 can output a rectangular waveform with “H” duty cycle n/ (n+m) from the P5

2/PWM1 pin by setting the timer 56 mode register

(refer to Figure 17). The n is the value set in timer 6 latch (address

16) and m is the value in the timer 6 PWM register (address

0025 0027

16). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output

is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur at the rising edge of the PWM output.

16,” an underflow occurs with the next

IN) or f(XCIN).

1/T1OUT pin. The wave-

0 can be switched with the bit 6 of the

16,” and timer 2 is

2/T3OUT pin. The wave-

1 can be switched with the bit 7 of the

2/PWM1 pin.

MITSUBISHI MICROCOMPUTERS

38C3 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

Timer 12 mode register (T12M: address 0028

Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits 00 : f(X

IN

01 : f(X

CIN

10 : f(X

IN

11 : f(X

IN

Timer 2 count source selection bits 00 : Underflow of Timer 1 01 : f(X

CIN

10 : External count input CNTR 11 : Not available Timer 1 output selection bit (P4 0 : I/O port 1 : Timer 1 output Not used (returns “0” when read) (Do not write “1” to this bit.)

b0

Timer 34 mode register (T34M: address 0029

Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bits 00 : f(X 01 : Underflow of Timer 2 10 : f(X 11 : f(X Timer 4 count source selection bits 00 : f(X 01 : Underflow of Timer 3 10 : External count input CNTR 11 : Not available Timer 3 output selection bit (P4 0 : I/O port 1 : Timer 3 output Not used (returns “0” when read) (Do not write “1” to this bit.)

b0

Timer 56 mode register (T56M: address 002A

Timer 5 count stop bit 0 : Count operation 1 : Count stop Timer 6 count stop bit 0 : Count operation 1 : Count stop Timer 5 count source selection bit 0 : f(X

IN

1 : Underflow of Timer 4 Timer 6 operation mode selection bit 0 : Timer mode 1 : PWM mode Timer 6 count source selection bits 00 : f(X 01 : Underflow of Timer 5 10 : Underflow of Timer 4 11 : Not available Timer 6 (PWM) output selection bit (P5 0 : I/O port 1 : Timer 6 output Not used (returns “0” when read) (Do not write “1” to this bit.)

)/16 or f(X

) )/32 or f(X )/128 or f(X

)

IN

)/16 or f(X

IN

)/32 or f(X

IN

)/128 or f(X

IN

)/16 or f(X

IN

)/16 or f(X

16

)

CIN

)/16

CIN

)/32

CIN

)/128

16

)

CIN

)/16

CIN

)/32

CIN

)/128

CIN

)/16

16

)

CIN

)/16

CIN

)/16

0

1

)

1

2

)

2

)

Fig. 16 Structure of Timer Related Register

19

Mitsubishi M38C37ECAFP, M38C37ECMFS, M38C37ECMFP, M38C37ECAFS Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

FEATURES

APPLICATIONS

PIN CONFIGURATION (TOP VIEW)

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

P ART NUMBERING

GROUP EXPANSION

Memory T ype

Memory Size

Packages

Interrupt Vector Area

Zero Page

Special Page

[Direction Registers (ports P0 and P1)]

Pull-up/Pull-down Control

Port P8 Output Selection

INTERRUPTS

Interrupt Control

Interrupt Operation

■Notes on Interrupts

Key Input Interrupt (Key-on Wake-Up)

●Timer 1, Timer 2

●Timer 3, Timer 4

●Timer 5, Timer 6