Mitsubishi M38504M6-XXXSP, M38504M6-XXXFP, M38504E6SS, M38504E6SP, M38504E6FP Datasheet

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MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 3850 group is the 8-bit microcomputer based on the 740 family core technology. The 3850 group is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.

FEATURES

●Basic machine-language instructions ...................................... 71

●Minimum instruction execution time .................................. 0.5 µs

(at 8 MHz oscillation frequency)

●Memory size

ROM ................................................................... 8K to 24K bytes

RAM.....................................................................512 to 640 byte

●Programmable input/output ports ............................................ 34

●Interrupts ................................................. 14 sources, 14 vectors

●Timers ............................................................................. 8-bit ✕ 4

●Serial I/O ....................... 8-bit ✕ 1(UART or Clock-synchronized)

●PWM ............................................................................... 8-bit ✕ 1

●A-D converter ............................................... 10-bit ✕ 5 channels

●Watchdog timer ............................................................ 16-bit ✕ 1

●Clock generating circuit..................................... Built-in 2 circuits

(connect to external ceramic resonator or quartz-crystal oscillator)

●Power source voltage

In high-speed mode .................................................. 4.0 to 5.5 V

(at 8 MHz oscillation frequency)

In high-speed mode .................................................. 2.7 to 5.5 V

(at 4 MHz oscillation frequency)

In middle-speed mode............................................... 2.7 to 5.5 V

(at 8 MHz oscillation frequency)

In low-speed mode.................................................... 2.7 to 5.5 V

(at 32 kHz oscillation frequency)

●Power dissipation

In high-speed mode .......................................................... 34 mW

(at 8 MHz oscillation frequency, at 5 V power source voltage)

In low-speed mode............................................................ 60 µW

(at 32 kHz oscillation frequency, at 3 V power source voltage)

●Operating temperature range.................................... –20 to 85°C

APPLICATION

Office automation equipment, FA equipment, Household products, Consumer electronics, etc.

PIN CONFIGURATION (TOP VIEW)

V

CC

REF

V

SS

AV

P44/INT3/PWM

P43/INT

2

P42/INT

1

P41/INT

0

P40/CNTR

7

/CNTR0/S

P2

P26/S

P20/X

Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP)

Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)

RDY

CLK

P25/TxD

4

/RxD

P2

P2 P2

CNV

P21/X

CIN

COUT

RESET

X

X

OUT

V

1

3 2

SS

IN

SS

P30/AN

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

M38503M4-XXXSP

M38503M4-XXXFP

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

0

P31/AN

1

P32/AN

2

P33/AN

3

P34/AN

4

P0

0

P0

1

P0

2

P0

3

P0

4

P0

5

P0

6

P0

7

P1

0

P1

1

P1

2

P13/(LED0)

4

/(LED1)

P1

5

/(LED2)

P1 P16/(LED3) P1

7

/(LED4)

Fig. 1 M38503M4-XXXFP/SP pin configuration

FUNCTIONAL BLOCK

INT

0

–

CNTR

0

CNTR

1

V

REF

AV

SS

R A M

R O M

C P U

A

X

Y

S

PC

H

PCLPS

V

SS

21

RESET

18

V

CC

1 15

CNV

SS

23

X

IN

19

20

SI/O(8)

Reset input

Clock generating circuit

Main-clock

input

Main-clock

output

A-D

converter

(10)

Timer Y( 8 )

Timer X( 8 )

Prescaler 12(8)

Prescaler X(8)

Prescaler Y(8)

Timer 1( 8 )

Timer 2( 8 )

Sub-clock

input

X

OUT

X

CIN

X

COUT

Sub-clock

output

Watchdog

timer

Reset

P2(8)

P3(5)

I/O port P2

I/O port P3

P4(5)

I/O port P4

INT

3

4

68 5

7

39

4138 40

42

9

11

13

17

10

12

14

16

P1(8)

I/O port P1

22 24 26 2823 25 27 29

P0(8)

I/O port P0

30 3132 3334 35 36

37

PWM

(8)

X

CIN

X

COUT

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM

Fig. 2 Functional block diagram

2

PIN DESCRIPTION

Table 1 Pin description

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

VCC, VSS

RESET

IN

X

XOUT

P00–P07

P10–P17

P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK

P27/CNTR0/ SRDY

P30/AN0– P34/AN4

P4

0/CNTR1

P41/INT0– P43/INT2

P44/INT3/PWM

NamePin

Power source

SS inputCNVSS

CNV Reset input Clock input

Clock output

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

Functions

•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.

•This pin controls the operation mode of the chip.

•Normally connected to V

•Reset input pin for active “L.”

•Input and output pins for the clock generating circuit.

•Connect a ceramic resonator or quartz-crystal oscillator between the X the oscillation frequency.

•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

•8-bit CMOS I/O port.

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level.

•CMOS 3-state output structure.

•P1

3 to P17 (5 bits) are enabled to output large current for LED drive.

•8-bit CMOS I/O port.

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level.

•P20, P21, P24 to P27 : CMOS3-state output structure.

•P22, P23: N-channel open-drain structure.

•8-bit CMOS I/O port with the same function as port P0.

•CMOS compatible input level.

•CMOS 3-state output structure.

•8-bit CMOS I/O port with the same function as port P0.

•CMOS compatible input level.

•CMOS 3-state output structure.

SS.

Function except a port function

IN and XOUT pins to set

• Sub-clock generating circuit I/O pins (connect a resonator)

• Serial I/O function pin

• Serial I/O function pin/ Timer X function pin

• A-D converter input pin

• Timer Y function pin

• Interrupt input pins

• Interrupt input pin

• PWM output pin

3

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Product

M3850 3 M 4 XXX FP

Package type

: 42P2R-A package

FP SP

: 42P4B package

SS

: 42S1B-A package

ROM number

Omitted in some types.

ROM/PROM size

: 4096 bytes

1

: 8192 bytes

2

: 12288 bytes

3

: 16384 bytes

4

: 20480 bytes

5

: 24576 bytes

6

: 28672 bytes

7

: 32768 bytes

8

: 36864 bytes

9 A

: 40960 bytes

B

: 45056 bytes

C

: 49152 bytes

D

: 53248 bytes

E

: 57344 bytes : 61440 bytes

F

Fig. 3 Part numbering

The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.

Memory type

ME : Mask ROM version

: EPROM or One Time PROM version

RAM size

: 192 bytes

0

: 256 bytes

1

: 384 bytes

2

: 512 bytes

3

: 640 bytes

4

: 768 bytes

5

: 896 bytes

6

: 1024 bytes

7

: 1536 bytes

8

: 2048 bytes

9

4

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3850 group as follows:

Memory T ype

Support for mask ROM, One Time PROM, and EPROM versions.

Memory Size

ROM/PROM size................................................... 8K to 24K bytes

RAM size .............................................................. 512 to 640 bytes

Memory Expansion Plan

ROM size (bytes)

48K

32K

28K

24K

20K

16K

12K

8K

Mass production

M38503M4/E4

Mass production

M38503M2

Packages

42P4B..........................................42-pin shrink plastic molded DIP

42P2R-A ............................................ 42-pin plastic molded SSOP

42S1B-A ................... 42-pin shrink ceramic DIP(EPROM version)

Under development

M38504M6/E6

128 192 256

Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped the development.

Fig. 4 Memory expansion plan

Currently planning products are listed below.

Table 2 Support products

Product name

M38503M2-XXXSP M38503M2-XXXFP

(P) ROM size (bytes) ROM size for User in ( )

8192

(8062)

M38503M4-XXXSP M38503E4-XXXSP M38503E4SP M38503E4SS

16384

(16254)

M38503M4-XXXFP M38503E4-XXXFP M38503E4FP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP M38504E6SS

32768

(32638)

M38504M6-XXXFP M38504E6-XXXFP M38504E6FP

384 512 640 768 896 1024

RAM size (bytes)

RAM size (bytes)

512

Package

42P4B

42P2R-A

Remarks

Mask ROM version Mask ROM version

Mask ROM version

42P4B

One Time PROM version One Time PROM version (blank)

512

42S1B-A

EPROM version (stock only replaced by M38504E6SS) Mask ROM version

42P2R-A

One Time PROM version One Time PROM version (blank) Mask ROM version

42P4B

One Time PROM version One Time PROM version (blank)

640

42S1B-A

EPROM version Mask ROM version

42P2R-A

One Time PROM version One Time PROM version (blank)

As of August 1998

5

FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)

The 3850 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B

16.

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

CPU mode register

(

CPUM : address

003B16)

Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 :

Stack page selection bit 0 : 0 page 1 : 1 page

Not used (return “1” when read)

(Do not write “0” to this bit.)

C

switch bit

Port X

0 : I/O port function (stop oscillating)

CIN–XCOUT

1 : X

Main clock (X

0 : Oscillating 1 : Stopped

Main clock division ratio selection bits b7 b6 0 0 : φ = f(X 0 1 : φ = f(X 1 0 : φ = f(X 1 1 : Not available

IN–XOUT

oscillating function

) stop bit

IN

)/2 (high-speed mode)

IN

)/8 (middle-speed mode)

CIN

)/2 (low-speed mode)

Fig. 5 Structure of CPU mode register

6

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area

The Special Function Register area in the zero page contains control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reser ved for device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM size

(bytes)

192 256 384 512 640 768

896 1024 1536 2048 3072 4032

Address XXXX

00FF 013F 01BF 023F 02BF 033F 03BF 043F 063F 083F 0C3F 0FFF

16

16

16

16

16

16

16

16 16 16 16

16

16

Zero Page

Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special Page

Access to this area with only 2 bytes is possible in the special page addressing mode.

0000

RAM

0040

0100

XXXX

0440

16

16

16

16

16

SFR area

Zero page

Reserved area

Not used

ROM area

ROM size

(bytes)

4096

8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440

Fig. 6 Memory map diagram

Address

YYYY

F000 E000 D000 C000 B000 A000 9000 8000 7000 6000 5000 4000 3000 2000 1000

YYYY

16

Reserved ROM area

Address

16

16

16 16 16 16

16 16 16 16 16 16 16 16 16 16

ZZZZ

F080 E080 D080 C080 B080 A080 9080 8080 7080 6080 5080 4080 3080 2080 1080

16 16

16 16 16 16

16 16 16 16 16 16 16 16 16 16

ROM

ZZZZ

FF00

FFDC

FFFE FFFF

16

16

16

16 16

(128 bytes)

Interrupt vector area

Reserved ROM area

Special page

7

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F

Port P0 (P0)

16

Port P0 direction register (P0D)

16

Port P1 (P1)

16

Port P1 direction register (P1D)

16

Port P2 (P2)

16

Port P2 direction register (P2D)

16

Port P3 (P3)

16

Port P3 direction register (P3D)

16

Port P4 (P4)

16

Port P4 direction register (P4D)

16 16 16

16

16 16 16 16 16 16 16 16 16

Reserved ✽

16

Reserved ✽

16

Reserved ✽

Transmit/Receive buffer register (TB/RB)

16

Serial I/O status register (SIOSTS)

16

Serial I/O control register (SIOCON)

16

UART control register (UARTCON)

16

Baud rate generator (BRG)

16

PWM control register (PWMCON)

16

PWM prescaler (PREPWM)

16

PWM register (PWM)

16

✽ Reserved : Do not write “1” to this address.

0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F

Prescaler 12 (PRE12)

16

Timer 1 (T1)

16

Timer 2 (T2)

16

Timer XY mode register (TM)

16

Prescaler X (PREX)

16

Timer X (TX)

16

Prescaler Y (PREY)

16

Timer Y (TY)

16

Timer count source selection register (TCSS)

16 16

16 16

Reserved ✽ Reserved ✽

16 16

Reserved ✽

16

Reserved ✽

16

Reserved ✽

16

Reserved ✽

16 16 16

A-D control register (ADCON)

16

A-D conversion low-order register (ADL)

16

A-D conversion high-order register (ADH)

16 16

MISRG

16

Watchdog timer control register (WDTCON)

16

Interrupt edge selection register (INTEDGE)

16

CPU mode register (CPUM)

16

Interrupt request register 1 (IREQ1)

16

Interrupt request register 2 (IREQ2)

16

Interrupt control register 1 (ICON1)

16

Interrupt control register 2 (ICON2)

16

Fig. 7 Memory map of special function register (SFR)

8

I/O PORTS

The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

Table 3 I/O port function

Pin

P00–P07 P10–P17 P20/XCOUT

P21/XCIN

P22 P23

Name

Port P0 Port P1

Input/Output

I/O Structure Non-Port Function

CMOS compatible input level CMOS 3-state output Sub-clock generating

CMOS compatible input level N-channel open-drain output

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Related SFRs

circuit

CPU mode register

Ref.No .

(1)

(2) (3)

(4)

P24/RxD P25/TxD

6/SCLK

P2

P27/CNTR0/SRDY

P30/AN0– P34/AN4

P40/CNTR1 P41/INT0–

P43/INT2

P44/INT3/PWM

Port P2

Port P3

Port P4

Input/output, individual bits

CMOS compatible input level CMOS 3-state output

Serial I/O function I/O

Serial I/O function I/O

Serial I/O function I/O Timer X function I/O

A-D conversion input

Timer Y function I/O

External interrupt input

External interrupt input PWM output

Serial I/O control register

Serial I/O control register

Serial I/O control register Timer XY mode register

A-D control register

Timer XY mode register Interrupt edge selection

register Interrupt edge selection

register PWM control register

(5) (6)

(7)

(8)

(9)

(10) (11)

(12)

9

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Port P0, P1

Data bus

(3) Port P2

Data bus

1

Port XC switch bit

(5) Port P2

Serial I/O enable bit

Receive enable bit

Data bus

Direction register

Port latch

Direction register

Port latch

Sub-clock generating circuit input

4

Direction register

Port latch

(2) Port P2

Data bus

(4) Port P2

Data bus

(6) Port P2

0

Port XC switch bit

Direction register

Port latch

2, P23

Port latch

5

P-channel output disable bit

Serial I/O enable bit

Transmit enable bit

Direction register

Direction register

Port P2

Port X

Oscillator

1

C

switch bit

(7) Port P2

Serial I/O clock

Serial I/O enable bit Serial I/O mode selection bit

Data bus

6

selection bit

Serial I/O enable bit

Direction register

Port latch

Serial clock output

Fig. 8 Port block diagram (1)

Serial I/O input

External clock input

Data bus

(8) Port P2

Serial I/O mode selection bit

7

Serial I/O enable bit

RDY

output enable bit

S

Data bus

Serial ready output

Port latch

Serial I/O output

Pulse output mode

Pulse output mode

Direction register

Port latch

Timer output

CNTR

0

interrupt

input

10

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Port P30–P3

Data bus

(11) Port P41–P4

Data bus

4

Direction register

Port latch

A-D converter input

3 Direction

register

Port latch

Fig. 9 Port block diagram (2)

Analog input pin selection bit

Interrupt input

(10) Port P4

(12) Port P4

Data bus Port latch

0

Data bus

4

PWM output enable bit

Direction register

PWM output

Direction register

Port latch

Pulse output mode

Timer output

CNTR1 interrupt input

11

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.

Interrupt Operation

By acceptance of an interrupt, the following operations are automatically performed:

1. The contents of the program counter and the processor status register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.

3. The interrupt jump destination address is read from the vector table into the program counter.

■Notes

When the active edge of an external interrupt (INT0–INT3, CNTR0, CNTR

1) is set, the corresponding interrupt request bit may also be

set. Therefore, take the following sequence:

1. Disable the interrupt

2. Change the interrupt edge selection register (the timer XY mode register for CNTR

3. Clear the interrupt request bit to “0”

4. Accept the interrupt.

0 and CNTR1)

12

Table 4 Interrupt vector addresses and priority

Interrupt Source Reset (Note 2)

INT0

Reserved

INT1

INT2

INT3

Reserved Timer X Timer Y Timer 1 Timer 2

Serial I/O reception

Serial I/O Transmission

CNTR

0

CNTR1

A-D converter BRK instruction

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Priority

1 2

3 4

5

6 7

8 9

10 11

12

13

14

15 16

17 Non-maskable software interrupt

Vector Addresses (Note 1)

High

FFFD16

FFFB16 FFF916 FFF716

FFF516

FFF316 FFF116

FFEF16

FFED16

FFEB16 FFE916

FFE716

FFE516

FFE316

FFE116 FFDF16

FFDD16

Low

FFFC FFFA

FFF816 FFF616

FFF416

FFF216 FFF016

FFEE16 FFEC16 FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016 FFDE16

FFDC16

16

16

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt Request

Generating Conditions

At reset

At detection of either rising or falling edge of INT

Reserved At detection of either rising or

falling edge of INT

At detection of either rising or falling edge of INT2 input

At detection of either rising or falling edge of INT

Reserved

At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O data

reception At completion of serial I/O trans-

fer shift or when transmission buffer is empty

At detection of either rising or falling edge of CNTR

At detection of either rising or falling edge of CNTR1 input

At completion of A-D conversion At BRK instruction execution

0 input

1 input

3 input

0 input

3850 Group

Remarks

Non-maskable External interrupt

(active edge selectable)

External interrupt (active edge selectable)

External interrupt (active edge selectable)

External interrupt (active edge selectable)

STP release timer underflow

Valid when serial I/O is selected

Valid when serial I/O is selected

External interrupt (active edge selectable)

External interrupt (active edge selectable)

13

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 10 Interrupt control

b7 b0

b7 b0

Interrupt edge selection register (INTEDGE : address 003A

16

)

INT0 active edge selection bit INT

1

active edge selection bit

INT

2

active edge selection bit

INT

3

active edge selection bit Reserved(Do not write “1” to this bit) Not used (returns “0” when read)

Interrupt request register 1 (IREQ1 : address 003C

16

)

INT0 interrupt request bit Reserved INT

1

interrupt request bit

INT

2

interrupt request bit

3

interrupt request bit

INT Reserved Timer X interrupt request bit Timer Y interrupt request bit

0 : No interrupt request issued 1 : Interrupt request issued

BRK instruction

Reset

0 : Falling edge active 1 : Rising edge active

b7 b0

Interrupt request

Interrupt request register 2 (IREQ2 : address 003D

Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O reception interrupt request bit Serial I/O transmit interrupt request bit CNTR

0

interrupt request bit

CNTR

1

interrupt request bit AD converter interrupt request bit Not used (returns “0” when read)

0 : No interrupt request issued 1 : Interrupt request issued

16

)

b7 b0

Interrupt control register 1

(ICON1 : address 003E

INT0 interrupt enable bit Reserved(Do not write "1" to this bit)

1

interrupt enable bit

INT INT

2

interrupt enable bit

INT

3

interrupt enable bit Reserved(Do not write "1" to this bit) Timer X interrupt enable bit Timer Y interrupt enable bit

0 : Interrupts disabled 1 : Interrupts enabled

Fig. 11 Structure of interrupt-related registers (1)

14

b7 b0

16

)

Interrupt control register 2 (ICON2 : address 003F

16

)

Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O reception interrupt enable bit Serial I/O transmit interrupt enable bit CNTR

0

interrupt enable bit

CNTR

1

interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit)

0 : Interrupts disabled 1 : Interrupts enabled

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMERS

The 3850 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “00 derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.

b7

b0

Timer XY mode register (TM : address 0023

Timer X operating mode bit

b1b0

0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode

CNTR0 active edge selection bit

0: Interrupt at falling edge

Count at rising edge in event counter mode

1: Interrupt at rising edge

Count at falling edge in event counter mode

Timer X count stop bit

0: Count start 1: Count stop

Timer Y operating mode bit

b5b4

0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode

1 active edge selection bit

CNTR

0: Interrupt at falling edge

Count at rising edge in event counter mode

1: Interrupt at rising edge

Count at falling edge in event counter mode

Timer Y count stop bit

0: Count start 1: Count stop

Fig. 12 Structure of timer XY mode register

16”, an un-

16)

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.

(1) Timer Mode

The timer counts the count source selected by Timer count source selection bit.

(2) Pulse Output Mode

The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach “00 signal output from the CNTR CNTR

0 (or CNTR1) active edge selection bit is “0”, output begins

0 (or CNTR1) pin is inverted. If the

16”, the

at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P2

7 ( or port P40) direction register to out-

put mode.

(3) Event Counter Mode

Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR CNTR

1 pin.

When the CNTR rising edge of the CNTR When the CNTR falling edge of the CNTR

0 (or CNTR1) active edge selection bit is “0”, the

0 (or CNTR1) pin is counted.

0 (or CNTR1) active edge selection bit is “1”, the

0 (or CNTR1) pin is counted.

0 or

(4) Pulse Width Measurement Mode

If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts the selected signals by the count source selection bit while the CNTR tive edge selection bit is “1”, the timer counts it while the CNTR (or CNTR1) pin is at “L”.

0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-

0

b7

b0

Timer count source selection register (TCSS : address 0028

Timer X count source selection bit

IN

)/16 (f(X

CIN

)/16 (f(X

)/16 (f(X

)

CIN

CIN

CIN

CIN

)/16 at low-speed mode)

)/2 at low-speed mode)

)/16 at low-speed mode)

)/2 at low-speed mode)

)/16 at low-speed mode)

0 : f(X 1 : f(XIN)/2 (f(X

Timer Y count source selection bit 0 : f(X

IN

1 : f(XIN)/2 (f(X Timer 12 count source selection bit

0 : f(X

IN

1 : f(X

CIN

Not used (returns “0” when read)

16

)

Fig. 13 Structure of timer count source selection register

The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.

■Note

When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.

15

Data bus

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

f(XIN)/16

f(XIN)/2

Timer X count source selection bit

7/CNTR0

P2

7

Port P2

direction register

f(XIN)/16

f(XIN)/2

Timer Y count source selection bit

P40/CNTR1

Port P4

direction register

CNTR edge selection

“0”

“1”

Port P2 latch

Pulse output mode

CNTR edge selection

“0”

“1”

Port P4

0

Pulse output mode

latch

0 active

bit

7

1 active

bit

0

Pulse width measurement mode

Event counter mode

CNTR edge selection bit

Pulse width measurement mode

Event counter mode

CNTR1 active edge selection bit

Timer mode Pulse output mode

Timer X count stop bit

0 active

“1”

“0”

Timer mode Pulse output mode

Timer Y count stop bit

“1”

“0”

Data bus

Prescaler X latch (8)

Prescaler X (8)

Q

Toggle flip-flop

Q

R

Data bus

Prescaler Y latch (8)

Prescaler Y (8)

Q

Toggle flip-flop

Q

R

Timer X latch (8)

Timer X (8)

T

Timer X latch write pulse Pulse output mode

Timer Y latch (8)

Timer Y (8)

T

Timer Y latch write pulse Pulse output mode

To timer X interrupt request bit

To CNTR

0 interrupt

request bit

To timer Y interrupt request bit

To CNTR

1 interrupt

request bit

Prescaler 12 latch (8)

f(XIN)/16

f(XCIN)

Timer 12 count source selection bit

Prescaler 12 (8)

Fig. 14 Block diagram of timer X, timer Y, timer 1, and timer 2

16

Timer 1 latch (8)

Timer 1 (8)

Timer 2 latch (8)

Timer 2 (8)

To timer 2 interrupt request bit

To timer 1 interrupt request bit

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