Mitsubishi M38027E8SS, M38027E8SP, M38027E8FS, M38027M8-XXXSP, M38027M8-XXXFP Datasheet

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Programmable input/output ports ............................................. 56

DESCRIPTION

The 3802 group is the 8-bit microcomputer based on the 740 fam­ily core technology.
The 3802 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
The various microcomputers in the 3802 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3802 group, re­fer to the section on group expansion.

FEATURES

Basic machine-language instructions....................................... 71

•

The minimum instruction execution time ............................ 0.5 µs

•

(at 8 MHz oscillation frequency)
Memory size

•

ROM .................................................................. 8 K to 32 K bytes

RAM ................................................................. 384 to 1024 bytes

•

Interrupts .................................................. 16 sources, 16 vectors

•

Timers ............................................................................. 8 bit ✕ 4

•

Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)

•

Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)

•

PWM................................................................................ 8-bit ✕ 1

•

A-D converter .................................................. 8-bit ✕ 8 channels

•

D-A converter.................................................. 8-bit ✕ 2 channels

•

Clock generating circuit ....................... Internal feedback resistor

•

(connect to external ceramic resonator or quartz-crystal oscillator)

Power source voltage..................................................3.0 to 5.5 V

•

(Extended operating temperature version : 4.0 to 5.5 V)

Power dissipation............................................................... 32 mW

•

Memory expansion possible

•

Operating temperature range .................................... –20 to 85°C

•

(Extended operating temperature version : –40 to 85°C)

APPLICATIONS

Office automation, VCRs, tuners, musical instruments, cameras,
air conditioners, etc.

PIN CONFIGURATION (TOP VIEW)

P37/RD

P36/WR

P35/SYNC

P34/φ

P33/RESETOUT

P32/ONW

P31/DA2
P30/DA1

VCC

VREF

SS

AV

7

/AN

7

P6

6

/AN

6

P6

P65/AN5
P64/AN4

P63 /AN3

2

/AD3

P01/AD1

P03

P00/AD0

P02/AD

45

46

48

47
49
50
51
52
53
54
55
56

M38022M4-XXXFP

57
58
59
60
61
62
63
64

123

4

/AN1

/INT3

P60/AN0

P62/AN2

P61

P57

7

P04/AD4

P06/AD6

P05/AD5

P07/AD

41

44

43

42

56789

0

/PWM

/SRDY2

/CNTR1

5

P56

P53

P54/CNTR

P5

/AD8
P10

40

P52/SCLK2

P11/AD9

39

10

P51/SOUT2

/AD13

P12/AD10

P14/AD12

P16/AD14

P13/AD11

P15

38

37

35

36

34

11

12

131415

D

/SIN2
P50

/SRDY1
P47

P46/SCLK1

4/RXD

P45/TX

P4

Package type : 64P6N-A

64-pin plastic-molded QFP

P17/AD15

33

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

16

/INT2

3

P4

P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
VSS
XOUT
XIN
P40/INT4
P41/INT0
RESET
CNVSS
P42/INT1

PIN CONFIGURATION (TOP VIEW)

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

V

V

AV
P67/AN
P66/AN
P65/AN
P64/AN
P63/AN

2

/AN

P6

1

/AN

P6
P60/AN

P57/INT

P56/PWM

P5

5

/CNTR

P54/CNTR

/S

RDY2

P5

3

2/SCLK2

P5
P51/S

OUT2

P50/S

P47/S

RDY1

P46/S

CLK1

5/TX

P4

P44/R

3

/INT

P4
P42/INT

CNV

RESET
P41/INT
P40/INT

X

OUT

V

REF

IN2

X

X

CC

1
2

SS

7
6
5
4
3
2
1
0
3

3
4
5
6
7
8

9
10
11
12

M38022M4-XXXSP

13
14

1

15

0

16
17
18
19
20
21

D
D

SS

22
23
24

2

25

1

26
27
28

0

29

4

IN

30
31

SS

32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P3

0

/DA

1

P31/DA

2

P32/ONW
P33/RESET
P34/φ
P3

5

/SYNC

/WR

6

P3

/RD

7

P3

P00/AD

0

P01/AD

1

P02/AD

2
3

P03/AD
P04/AD

4

P05/AD

5

P06/AD

6
7

P07/AD

0

/AD

8

P1
P11/AD

9

P12/AD

10

P13/AD

11

P14/AD

12

P15/AD

13
14

P16/AD

15

P17/AD
P20/DB

0

P21/DB

1

P22/DB

2

P23/DB

3

P24/DB

4

P25/DB

5

P26/DB

6

P27/DB

7

OUT

Package type : 64P4B

64-pin shrink plastic-molded DIP

2

MITSUBISHI MICROCOMPUTERS

CNTR1

CNTR

0

VREF AVSS

RAM

ROM

CPU

A

X

Y

S

PC

H

PCL

PS

VSS

32

RESET

27

VCC

1

26

CNVSS

P0(8)

49 50 51

52 53

54

55

56

P1(8)

41

43 45

47

42 44

46

48

P2(8)

33 35 37 39

36

38 40

P3(8)

57 59

61 63

58 60

62 64

P4(8)

20 22

24 28

21 23

25

29

P5(8)

12 14

16 18

13

15

17

19

P6(8)

46

10

59

11

3

34

2

XIN

30

XOUT

31

D-A

(8)

D-A

(8)

A-D

(8)

Reset input

Clock generating circuit

Clock input Clock output

Prescaler 12 (8)

Timer 1 (8)

Timer 2 (8)

I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3

I/O port P5

I/O port P6

7 8

SI/O1 (8)

INT

0

INT2

INT4

Prescaler X (8)

Timer X (8)

Prescaler Y (8)

Timer Y (8)

converter 2

converter 1

~

SI/O2 (8)

PWM (8)

INT3

converter

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B)

3

PIN DESCRIPTION

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Pin

VCC, VSS

CNVSS

VREF

AVSS

RESET
XIN
XOUT

P00–P07
P10–P17
P20–P27
P30/DA1,

P31/DA2

Name

Power source

CNVSS

Analog reference
voltage

Analog power
source

Reset input
Clock input
Clock output

I/O port P0
I/O port P1
I/O port P2
I/O port P3

Function

Function except a port function

• Apply voltage of 3.0 V–5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)

• This pin controls the operation mode of the chip.

• Normally connected to VSS.

• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.

• Reference voltage input pin for A-D and D-A converters

• GND input pin for A-D and D-A converters

• Connect to VSS.

• Reset input pin for active “L”

• Input and output signals for the clock generating circuit.

• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.

• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• The clock is used as the oscillating source of system clock.

• 8 bit CMOS I/O port

• I/O direction register allows each pin to be individually programmed as either input or output.

• At reset this port is set to input mode.

• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.

• CMOS compatible input level

• CMOS 3-state output structure

• D–A conversion output pins

P32–P37
P40/INT4,

P41/INT0,
P42/INT1,
P43/INT2

P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1

P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2

P54/CNTR0,
P55/CNTR1

P56/PWM
P57/INT3
P60/AN0–

P67/AN7

I/O port P4

I/O port P5

I/O port P6

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• 8-bit CMOS I/O port with the same function as port P0

• CMOS compatible input level

• CMOS 3-state output structure

• External interrupt input pin

• Serial I/O1 I/O pins

• Serial I/O2 I/O pins

• Timer X and Timer Y I/O pins

• PWM output pin

• External interrupt input pin

• A-D conversion input pins

4

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 3802 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM

versions

ROM/PROM capacity................................... 8 K to 32 K bytes

RAM capacity .............................................. 384 to 1024 bytes

Memory Expansion Plan

ROM size (bytes)

32K

28K

Mass product

24K

20K

Mass product

16K

12K

Mass product

8K

M38022M4

M38022M2

(2) Packages

64P4B ............................................ Shrink plastic molded DIP

64P6N-A................................................... Plastic molded QFP

64S1B-E.................................................... Shrink ceramic DIP

64D0................................................................... Ceramic LCC

Mass product

M38027M8/E8

M38024M6

4K

192

256 384 512 640 768 896 1024

Currently supported products are listed below

Product

M38022M2-XXXSP
M38022M2-XXXFP
M38022M4-XXXSP
M38022M4-XXXFP
M38024M6-XXXSP
M38024M6-XXXFP

(P) ROM size (bytes)
ROM size for User in ( )

8192

(8062)
16384

(16254)

24576

(24446)

M38027M8-XXXSP
M38027E8-XXXSP
M38027E8SP
M38027M8-XXXFP
M38027E8-XXXFP

32768

(32638)

M38027E8FP
M38027E8SS
M38027E8FS

RAM size (bytes)

RAM size (bytes)

384

384

640

1024

Package

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

64S1B-E

64D0

As of May 1996

Remarks

Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
EPROM version

5

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION (Extended operating temperature version)

Mitsubishi plans to expand the 3802 group (extended operating
temperature version) as follows:
(1) Support for mask ROM One Time PROM, and EPROM ver-

sions

ROM/PROM capacity................................... 8 K to 32 K bytes

RAM capacity .............................................. 384 to 1024 bytes

(2) Packages

64P4B ............................................ Shrink plastic molded DIP

64P6N-A................................................... Plastic molded QFP

Memory Expansion Plan (Extended operating temperature version)

ROM size (bytes)

32K

28K

24K

20K

Mass product

16K

12K

Mass product

8K

M38022M4D

M38022M2D

Mass product

M38027M8D/E8D

4K

192

256 384 512 640 768 896 1024

RAM size (bytes)

Currently supported products are listed below. As of May 1996

Product
M38022M2DXXXSP
M38022M2DXXXFP
M38022M4DXXXSP
M38022M4DXXXFP
M38027M8DXXXSP
M38027E8DXXXSP
M38027E8DSP
M38027M8DXXXFP
M38027E8DXXXFP
M38027E8DFP

(P) ROM size (bytes)

8192
(8062)
16384

(16254)

32768

(32638)

RAM size (bytes)

384

384

1024

Package

64P4B

64P6N-A

64P4B

64P6N-A

64P4B

64P6N-A

Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)

6

PART NUMBERING

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Product

M3802 2 M 4 - XXX SP

Package type

SP : 64P4B package
FP : 64P6N-A package
SS : 64S1B-E package
FS : 64D0 package

ROM number

Omitted in some types.

Normally, using hyphen.
When electrical characteristic, or division of quality
identification code using alphanumeric character

– : standard

D : Extended operating temperature version
ROM/PROM size

: 4096 bytes

1

: 8192 bytes

2

: 12288 bytes

3

: 16384 bytes

4

: 20480 bytes

5

: 24576 bytes

6

: 28672 bytes

7

: 32768 bytes

8

The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.

Memory type

M

: Mask ROM version

E

: EPROM or One Time PROM version

RAM size

: 192 bytes

0

: 256 bytes

1

: 384 bytes

2

: 512 bytes

3

: 640 bytes

4

: 768 bytes

5

: 896 bytes

6

: 1024 bytes

7

7

FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)

The 3802 group uses the standard 740 family instruction set. Re­fer to the table of 740 family addressing modes and machine in­structions or the SERIES 740 <Software> User’s Manual for de­tails on the instruction set.
Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.

CPU mode register

The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

CPU mode register

(

Fig. 1 Structure of CPU mode register

CPUM : address

Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available

Stack page selection bit
0 : 0 page
1 : 1 page

Not used (return “0” when read)

003B16)

8

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Memory
Special function register (SFR) area

The Special Function Register area in the zero page contains con­trol registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine
calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM capacity

(bytes)

192
256
384
512
640
768
896

1024

Address
XXXX

00FF
013F
01BF
023F
02BF
033F
03BF
043F

16

16
16
16
16
16
16
16
16

Zero page

The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis­ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac­cess to this area with only 2 bytes is possible in the special page
addressing mode.

0000

RAM

0040

0100

XXXX

16

16

16

16

SFR area

Zero page

Reserved area

ROM area

ROM capacity

(bytes)

4096

8192
12288
16384
20480
24576
28672
32768

Fig. 2 Memory map diagram

Address
YYYY

F000
E000
D000
C000
B000
A000
9000
8000

0440

16

Not used

16
16

16
16
16
16

16
16
16

Address
ZZZZ

F080
E080
D080
C080
B080
A080
9080
8080

16
16

16
16
16
16

16
16
16

ROM

YYYY

ZZZZ

FF00

FFDC

FFFE
FFFF

16

Reserved ROM area

(128 bytes)

16

16

16

Interrupt vector area

16

Reserved ROM area

16

Special page

9

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

000016

Port P0 direction register (P0D)

000116

Port P1 (P1)

000216

Port P1 direction register (P1D)

000316

Port P2 (P2)

000416

Port P2 direction register (P2D)

000516

Port P3 (P3)

000616

Port P3 direction register (P3D)

000716

Port P4 (P4)

000816

Port P4 direction register (P4D)

000916

Port P5 (P5)

000A16

Port P5 direction register (P5D)

000B16

Port P6 (P6)

000C16

Port P6 direction register (P6D)

000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716

Transmit/Receive buffer register (TB/RB)

001816

Serial I/O1 status register (SIO1STS)

001916

Serial I/O1 control register (SIO1CON)

001A16

UART control register (UARTCON)

001B16

Baud rate generator (BRG)

001C16

Serial I/O2 control register (SIO2CON)

001D16
001E16

Serial I/O2 register (SIO2)

001F16

Prescaler 12 (PRE12)

002016

Timer 1 (T1)

002116

Timer 2 (T2)

002216

Timer XY mode register (TM)

002316

Prescaler X (PREX)

002416

Timer X (TX)

002516

Prescaler Y (PREY)

002616

Timer Y (TY)

002716
002816
002916
002A16

PWM control register (PWMCON)

002B16

PMW prescaler (PREPWM)

002C16
002D16

PWM register (PWM)
002E16
002F16
003016
003116
003216
003316

AD/DA control register (ADCON)

003416

A-D conversion register (AD)

003516

D-A1 conversion register (DA1)

003616

D-A2 conversion register (DA2)

003716
003816
003916

Interrupt edge selection register (INTEDGE)

003A16

CPU mode register (CPUM)

003B16

Interrupt request register 1(IREQ1)

003C16

Interrupt request register 2(IREQ2)

003D16

Interrupt control register 1(ICON1)

003E16

Interrupt control register 2(ICON2)

003F16

Fig. 3 Memory map of special function register (SFR)

10

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O Ports
Direction registers

The 3802 group has 56 programmable I/O pins arranged in seven
I/O ports (ports P0 to P6). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be­comes an input pin. When “1” is written to that bit, that pin be­comes an output pin.

Pin

P00–P07

P10–P17

P20–P27

P30/DA1
P31/DA2
P32–P37
P40/INT4,
P41/INT0,
P43/INT2
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2
P54/CNTR0,
P55/CNTR1
P56/PWM
P57/INT3

P60/AN0–
P67/AN7

Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-

tion I/O ports, refer to the applicable sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

Input/Output

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

Input/output,
individual bits

I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

CMOS 3-state output
CMOS compatible
input level

If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.

Non-Port Function

Address low-order byte
output

Address high-order
byte output

Data bus I/O

D-A conversion output

Control signal I/O

External interrupt input

Serial I/O1 function I/O

Serial I/O2 function I/O

Timer X and Timer Y
function I/O
PWM output
External interrupt input

A-D conversion input

Related SFRs

CPU mode register

CPU mode register

CPU mode register

AD/DA control register
CPU mode register
CPU mode register

Interrupt edge selection
register

Serial I/O1 control
register
UART control register

Serial I/O2 control
register

Timer XY mode register
PWM control register

Interrupt edge selection register

Ref.No.

(1)

(2)
(1)

(3)

(4)
(5)
(6)
(7)
(8)

(9)
(10)
(11)

(12)
(13)

(3)

(14)

11

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Ports P0, P1, P2, P32–P37

Direction register

Data bus

Port latch

(3) Ports P40–P43, P57

Direction register

Data bus

Port latch

Interrupt input

(2) Ports P30, P31

Direction register

Data bus

Port latch

(4) Port P44

Serial I/O1 enable bit

Receive enable bit

Direction register

Data bus

Port latch

D–A conversion output

DA1 output enable bit (P30)
DA

2 output enable bit (P31)

Serial I/O1 input

(5) Port P45 (6) Port P46

P45/TXD P-channel output disable bit

Serial I/O1 enable bit

Transmit enable bit

Direction register

Data bus

Port latch

Serial I/O1 output

Serial I/O1 synchronous
clock selection bit

Serial I/O1 enable bit

Serial I/O1 mode selection bit

Data bus

(7) Port P47 (8) Port P50

Serial I/O1 mode selection bit

Serial I/O1 enable bit

S

RDY1 output enable bit

Data bus

Direction register

Port latch

Data bus

Serial I/O1 enable bit

Direction register

Port latch

Serial I/O1 clock output

Direction register

Port latch

Serial I/O2 input

Serial I/O1
external
clock input

Serial I/O1 ready output

Fig. 4 Port block diagram (single-chip mode) (1)

12

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Port P5

Data bus

(11) Port P5

1

P5

1/SOUT2

Serial I/O2 transmit end signal

Serial I/O2 port selection bit

Direction register

Port latch

Serial I/O2 output

3

Data bus

Serial I/O2 ready output

P-channel output disable bit

S

RDY2

output enable bit

Direction register

Port latch

(10) Port P5

Data bus

2

Serial I/O2
synchronous clock selection bit

Serial I/O2 port selection bit

Serial I/O2 clock output

(12) Ports P54, 5

Data bus

Direction register

Port latch

5

Direction register

Port latch

Pulse output mode

Timer output

Serial I/O2 external clock input

CNTR

0

, CNTR

Interrupt input

1

6

PWM output enable bit

Direction register

Data bus

Port latch

PWM output

Fig. 5 Port block diagram (single-chip mode) (2)

(14) Port P6(13) Port P5

Data bus

Direction register

Port latch

A-D conversion input

Analog input pin selection bit

13

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupts occur by sixteen sources: seven external, eight internal,
and one software.

Interrupt control

Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in­terrupt set by the BRK instruction. An interrupt occurs if the corre­sponding interrupt request and enable bits are “1” and the inter­rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in­struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.

Table 1. Interrupt vector addresses and priority

Interrupt Source
Reset (Note 2)
INT

0

INT1
Serial I/O1

reception
Serial I/O1

transmission
Timer X

Timer Y
Timer 1
Timer 2

CNTR0

CNTR1

Serial I/O2

INT2

INT3

INT4
A-D converter

Priority

1
2

3

4

5

6
7
8
9

10

11

12

13

14

15
16

Vector Addresses (Note 1)

High

FFFD16
FFFB16

FFF916

FFF716

FFF516

FFF316
FFF116
FFEF16
FFED16

FFEB16

FFE916

FFE716

FFE516

FFE316

FFE116
FFDF16

Low

FFFC16
FFFA16

FFF816

FFF616

FFF416

FFF216
FFF016
FFEE16
FFEC16

FFEA16

FFE816

FFE616

FFE416

FFE216

FFE016
FFDE16

Interrupt operation

When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.

Notes on use

When the active edge of an external interrupt (INT0 to INT4,
CNTR

0, or CNTR1) is changed, the corresponding interrupt re-

quest bit may also be set. Therefore, please take following se­quence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.

Interrupt Request

Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion

Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Valid when serial I/O1 is selected

Valid when serial I/O1 is selected

STP release timer underflow

External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Valid when serial I/O2 is selected
External interrupt

(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)

Remarks

BRK instruction

Note 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

14

17

FFDD16

FFDC16

At BRK instruction execution

Non-maskable software interrupt

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 6 Interrupt control

b7 b0

b7 b0

BRK instruction

Interrupt edge selection register

16

(INTEDGE : address 003A

)

INT0 active edge selection bit
INT

1

active edge selection bit
Not used (returns “0” when read)
INT

2

active edge selection bit
INT

3

active edge selection bit
INT

4

active edge selection bit
Not used (returns “0” when read)

Interrupt request register 1
(IREQ1 : address 003C

16

)

INT0 interrupt request bit
INT

1

interrupt request bit

Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit

Reset

0 : Falling edge active
1 : Rising edge active

b7 b0

Interrupt request

Interrupt request register 2
(IREQ2 : address 003D

CNTR0 interrupt request bit
CNTR

1

interrupt request bit
Serial I/O2 interrupt request bit
INT2 interrupt request bit
INT

3

interrupt request bit

INT

4

interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)

0 : No interrupt request issued
1 : Interrupt request issued

16

)

b7 b0

Interrupt control register 1
(ICON1 : address 003E

INT0 interrupt enable bit
INT

1

interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit

Fig. 7 Structure of interrupt-related registers

b7 b0

16

)

Interrupt control register 2
(ICON2 : address 003F16)

CNTR0 interrupt enable bit
CNTR

1

interrupt enable bit
Serial I/O2 interrupt enable bit
INT

2

interrupt enable bit

INT

3

interrupt enable bit

INT

4

interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)

0 : Interrupts disabled
1 : Interrupts enabled

15

MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timers

The 3802 group has four timers: timer X, timer Y, timer 1, and timer

2.
All timers are count down. When the timer reaches “00
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.

b7

b0

Timer XY mode register
(TM : address 002316)

Timer X operating mode bit

b1b0

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

CNTR0 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event

counter mode

1: Interrupt at rising edge

Count at falling edge in event

counter mode

Timer X count stop bit

0: Count start
1: Count stop

Timer Y operating mode bit

b4b5

0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode

CNTR1 active edge switch bit

0: Interrupt at falling edge

Count at rising edge in event
counter mode

1: Interrupt at rising edge

Count at falling edge in event
counter mode

Timer Y count stop bit

0: Count start
1: Count stop

16”, an un-

Timer 1 and Timer 2

The count source of prescaler 12 is the oscillation frequency di­vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.

Timer X and Timer Y

Timer X and Timer Y can each be selected in one of four operating
modes by setting the timer XY mode register.

Timer Mode

The timer counts f(X

Pulse Output Mode

Timer X (or timer Y) counts f(X
the timer reach “00
CNTR

1) pin is inverted. If the CNTR0 (or CNTR1) active edge

switch bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P5
put mode.

Event Counter Mode

Operation in event counter mode is the same as in timer mode,
except the timer counts signals input through the CNTR
CNTR

1 pin.

Pulse Width Measurement Mode

If the CNTR
counts at the oscillation frequency divided by 16 while the CNTR
(or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge
switch bit is “1”, the count continues during the time that the
CNTR

0 (or CNTR1) pin is at “L”.

In all of these modes, the count can be stopped by setting the
timer X (timer Y) count stop bit to “1”. Every time a timer
underflows, the corresponding interrupt request bit is set.

IN)/16 in timer mode.

IN)/16. Whenever the contents of

16”, the signal output from the CNTR0 (or

4 ( or port P55) direction register to out-

0 or

0 (or CNTR1) active edge selection bit is “0”, the timer

0

Fig. 8 Structure of timer XY register

16