Mitsubishi M37920FCCHP, M37920FCCGP, M37920FGCHP, M37920FGCGP Datasheet
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
DESCRIPTION
These are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash
memory. These are housed in 100-pin plastic molded QFP. These
microcomputers support the 7900 Series instruction set, which are
enhanced and expanded instruction set and are upper-compatible
with the 7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. These microcomputers
include the 4-channel DMA controller and the DRAM controller.
Therefore, these microcomputers are suitable for office, business,
and industrial equipment controller that require fast processing of
large data.
For the internal flash memory, single-power-supply programming
and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain
software which controls programming and erasure (reprogramming
control software). Therefore, on these microcomputers, the program
can easily be changed even after they are mounted on the board.
DISTINCTIVE FEATURES
<Microcomputer mode>
Number of basic machine instructions .................................... 203
•
Memory
•
[M37920FCCGP, M37920FCCHP]
Flash memory (User ROM area) ................................. 120 Kbytes
RAM .............................................................................4096 bytes
[M37920FGCGP, M37920FGCHP]
Flash memory (User ROM area) ................................. 248 Kbytes
RAM .............................................................................6144 bytes
[All of the above computers]
Flash memory (Boot ROM area) ................................... 16 Kbytes
Instruction execution time
•
The fastest instruction at 20 MHz frequency ........................ 50 ns
Single power supply .................................................... 5 V ± 0.5 V
•
Interrupts ........... 6 external sources, 20 internal sources, 7 levels
•
Multi-functional 16-bit timer ................................................... 5 + 3
•
Serial I/O (UART or Clock synchronous)..................................... 2
•
10-bit A-D converter ............................................ 4-channel inputs
•
DMA controller.............................................................. 4 channels
•
DRAM controller
•
Real-time output
•
....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
12-bit watchdog timer
•
Programmable input/output (ports P0–P12).............................. 85
•
Erase method ............................................
•
Programming/Erase control by software command
•
Maximum number of reprograms ............................................ 100
•
(Data protection per block is enabled.)
Block erase or Total erase
APPLICATION
Control devices for personal computer peripheral equipment such as
CD-ROM drives, DVD-ROM drives, hard disk drives, high density
FDD, printers
Control devices for office equipment such as copiers and facsimiles
Control devices for industrial equipment such as communication and
measuring instruments
<Flash memory mode>
Power supply voltage .................................................. 5 V ± 0.5 V
•
Programming/Erase voltage........................................ 5 V ± 0.5 V
•
Programming method............ Programming in a unit of 256 bytes
•
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
M37920FxCGP PIN CONFIGURATION (TOP VIEW)
1
/A
1
↔ P10
8079787776757473727170696867666564636261605958575655545352
81
82
↔
83
↔
84
85
86
↔
87
88
89
90
91
92
93
94
95
96
97
98
99
100
123456789
↔
3
/DMAREQ
6
P6
P7
3
3
/CTS0/RTS0 ↔
P8
P8
2
/CTS0/CLK1 ↔
/AN3/AD
P7
2
P12
2
/INT2/TB2IN ↔
P12
1
/INT1/TB1IN ↔
P12
0
/INT0/TB0IN ↔
P100/A0 ↔
P8
6
/CLK0 ↔
5/RXD0
P8
P8
4/TXD0
1/RXD1
P8
P80/TXD1 ↔
CC
V
CC
AV
REF
V
AV
SS
SS
V
TRG
/INT4 ↔
/AN2/INT3 ↔
1
/AN1 ↔
P7
P7
0
/AN0 ↔
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
5
4
3
2
1
2
/A
2
↔ P10
3
/A
3
↔ P10
4
/A
4
↔ P10
5
/A
5
↔ P10
6
/A
6
↔ P10
7
/A
7
↔ P10
0
/MA
8
/A
0
↔ P11
/MA
9
/A
1
↔ P11
/MA
10
/A
2
↔ P11
/MA
11
/A
3
↔ P11
/MA
12
/A
4
↔ P11
/MA
13
/A
5
↔ P11
M37920FCCGP
M37920FGCGP
↔
↔
↔
2
2
1
/DMAACK
/DMAREQ
/DMAREQ
IN
IN
OUT
/TA4
/TA3
5
3
/TA4
4
P6
P6
P6
↔
↔
1
0
/DMAACK
/DMAREQ
IN
OUT
/TA1
1
/TA3
2
P6
P6
101112131415161718192021222324252627282930
↔
↔
↔
↔
↔
↔
1
0
/RTP1
/RTP1
5
4
P5
P5
↔
3
2
/RTP0
/RTP0
3
2
P5
P5
0
2
3
/RTP1
/RTP1
IN
OUT
/DMAACK
/TA2
7
OUT
/TA2
6
P5
P5
/TA1
0
P6
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
7
6
/MA
/MA
15
14
/A
/A
7
6
↔ P11
↔ P11
↔
↔
0
1
/RTP0
/RTP0
IN
OUT
/TA0
1
/TA0
0
P5
P5
8
/MA
16
/A
0
↔ P0
/WRH/UCAS ↔
6
P9
17
/A
1
↔ P0
/WRL/LCAS ↔
5
P9
9
/MA
18
/A
2
↔ P0
/CAS/W ↔
4
P9
19
/A
3
↔ P0
↔
3
/RAS
3
/CS
3
P9
10
/MA
20
/A
4
↔ P0
↔
2
/RAS
2
/CS
2
P9
21
/A
5
↔ P0
↔
1
/RAS
1
/CS
1
P9
11
/MA
22
/A
6
↔ P0
↔
0
/CS
0
P9
23
/A
7
↔ P0
/HLDA ↔
4
P4
4
3
0
2
1
/D
/D
/D
/D
/D
4
3
0
2
1
SS
V
MD1
←
↔ P1
↔
1
/φ
/TC ↔
1
2
P4
/HOLD ↔
P4
3
P4
↔ P1
/ALE ↔
0
P4
↔ P1
/BHW ↔
3
P3
↔ P1
/BLW ↔
2
P3
↔ P1
51
50
↔ P15/D
49
↔ P16/D
48
↔ P17/D
47
↔ P20/D
46
↔ P21/D
45
↔ P22/D
44
↔ P23/D
43
↔ P24/D
42
↔ P25/D
41
↔ P26/D
40
↔ P27/D
39
V
38
→ X
37
← X
36
35
←
34
←
33
←
32
←
31
↔ P30/RDY
/RD ↔
1
P3
CC
OUT
IN
V
SS
MD0
RESET
NMI
BYTE
5
6
7
8
9
10
11
12
13
14
15
Outline 100P6S-A
2
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
M37920FxCHP PIN CONFIGURATION (TOP VIEW)
P103/A3 ↔
P102/A2 ↔
P101/A1 ↔
P100/A0 ↔
P86/CLK0 ↔
P8
P8
P8
3
/CTS0/RTS0 ↔
P8
2
/CTS0/CLK1 ↔
P8
P80/TXD1 ↔
P7
3
/AN3/AD
TRG
P7
2
/AN2/INT3 ↔
P7
P7
2
/INT2/TB2IN ↔
P12
P12
1
/INT1/TB1IN ↔
P12
0
/INT0/TB0IN ↔
P66/DMAREQ3 ↔
P6
5
/TA4IN/DMAREQ2 ↔
5/RXD0
4/TXD0
1/RXD1
V
AV
V
REF
AV
V
/INT4 ↔
1
/AN1 ↔
0
/AN0 ↔
76
77
78
79
80
↔
81
↔
82
83
84
↔
85
86
CC
87
CC
88
89
SS
90
SS
91
92
93
94
95
96
97
98
99
100
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
0
/MA
/MA
/MA
/MA
11
10
9
8
7
6
5
4
/A
/A
/A
/A
7
6
5
4
↔ P10
↔ P10
↔ P10
↔ P10
75747372717069686766656463626160595857565554535251
/A
0
↔ P11
/A
1
↔ P11
/A
2
↔ P11
/A
3
↔ P11
/MA
12
/A
4
↔ P11
/MA
13
/A
5
↔ P11
/MA
14
/A
6
↔ P11
/MA
15
/A
7
↔ P11
7
6
5
4
3
2
1
M37920FCCHP
M37920FGCHP
123456789
↔
2
/DMAACK
OUT
/TA4
4
P6
↔
↔
↔
1
1
0
/DMAACK
/DMAREQ
/DMAREQ
IN
IN
OUT
/TA3
/TA1
3
1
/TA3
2
P6
P6
P6
↔
↔
0
3
/RTP1
IN
/DMAACK
/TA2
7
OUT
P5
/TA1
0
P6
101112131415161718192021222324
↔
↔
↔
↔
↔
0
3
/RTP1
/RTP0
4
3
P5
P5
↔
2
1
/RTP0
/RTP0
2
IN
P5
/TA0
1
P5
2
1
/RTP1
/RTP1
5
P5
OUT
/TA2
6
P5
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
11
10
9
8
/MA
/MA
/MA
/MA
17
16
/A
/A
1
0
↔ P0
↔ P0
↔
0
/RTP0
OUT
/WRH/UCAS ↔
6
/TA0
P9
0
P5
18
/A
2
↔ P0
/WRL/LCAS ↔
5
P9
19
/A
3
↔ P0
/CAS/W ↔
4
P9
20
/A
4
↔ P0
↔
3
/RAS
3
/CS
3
P9
21
/A
5
↔ P0
↔
2
/RAS
2
/CS
2
P9
22
/A
6
↔ P0
↔
1
/RAS
1
/CS
1
P9
23
/A
7
↔ P0
↔
0
/CS
0
P9
SS
V
/HLDA ↔
4
P4
MD1
←
/HOLD ↔
3
P4
0
/D
0
↔ P1
↔
/TC
2
P4
1
/D
1
↔ P1
↔
1
/φ
1
P4
2
/D
2
↔ P1
50
↔ P13/D
49
↔ P14/D
48
↔ P15/D
47
↔ P16/D
46
↔ P17/D
45
↔ P20/D
44
↔ P21/D
43
↔ P22/D
42
↔ P23/D
41
↔ P24/D
40
↔ P25/D
39
↔ P26/D
38
↔ P27/D
37
V
36
→ X
35
← X
34
←
33
←
32
←
31
30
←
↔ P30/RDY
29
28↔
27↔
26↔
25
↔
/ALE
0
P4
CC
OUT
IN
V
SS
MD0
RESET
NMI
BYTE
P31/RD
P32/BLW
P33/BHW
3
4
5
6
7
8
9
10
11
12
13
14
15
Outline 100P6Q-A
3
PRELIMINARY
Data bank Register DT (8)
Program Counter PC (16)
Incrementer/Decrementer (24)
Program Bank Register PG (8)
Input Buffer Register IB (16)
Direct Page Register DPR0 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Arithmetic Logic
Unit (16)
Accumulator B (16)
Accumulator A (16)
Instruction register (8)
Central Processing Unit (CPU)
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Bus
Interface
Unit
(BIU)
RESET
MD1
Reference
voltage input
V
REF
(0V)
AV
SS
AVcc
Vcc
External data bus width
select input
BYTE
Clock Generating Circuit
Clock input
X
IN
X
OUT
Data Buffer DQ0 (8)
Instruction Queue Buffer Q0 (8)
Data Bus (Odd)
Address Bus
A-D converter (10)
Watchdog timer
Timer TB1 (16)
Timer TB2 (16)
Timer TB0 (16)
Timer TA1 (16)
Timer TA2 (16)
Timer TA3 (16)
Timer TA4 (16)
Timer TA0 (16)
Input/Output
port P8
Input/Output
port P7
Input/Output
port P4
Input/Output
port P10
Input/Output
port P6
Input/Output
port P5
Input/Output
port P11
Input/Output
port P1
Input/Output
port P2
Input/Output
port P3
Input/Output
port P0
MD0
(0V)
Vss
Processor Status Register PS (11)
NMI
Data Bus (Even)
Data Buffer DQ
1
(8)
Data Buffer DQ
2
(8)
Data Buffer DQ
3
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
3
(8)
Instruction Queue Buffer Q
4
(8)
Instruction Queue Buffer Q
5
(8)
Instruction Queue Buffer Q
6
(8)
Instruction Queue Buffer Q
7
(8)
Instruction Queue Buffer Q
8
(8)
Instruction Queue Buffer Q
9
(8)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Clock output
Reset input
Note:
Flash memory RAM
M37920FCCGP, M37920FCCHP 120 Kbytes 4096 bytes
M37920FGCGP, M37920FGCHP 248 Kbytes 6144 bytes
UART1(9)
UART0(9)
RAM
(Note)
P8(7)
P7(4)
P9(7)
P4(5)
P10(8)
P6(7)
P5(8)
DRAM controoler
DMA0(16)
DMA1(16)
DMA2(16)
DMA3(16)
P11(8)
P12(3)
P1(8)
P2(8)
P3(4)
P0(8)
Flash memory
(Note)
Input/Output
port P9
Input/Output
port P12
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
BLOCK DIAGRAM
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONS (Microcomputer mode)
Number of basic machine instructions
Instruction execution time
External clock input frequency f(XIN)
Memory size
Programmable input/output
ports
Multi-functional timers
Serial I/O
A-D converter
Watchdog timer
DMA controller
DRAM controller
Chip-select wait control
Flash memory (User ROM area)
RAM
Flash memory (Boot ROM area)
P0–P2, P5, P10, P11
P3, P7
P4
P6, P8, P9
P12
TA0–TA4
TB0–TB2
UART0 and UART1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
FunctionsParameter
203
50 ns (the fastest instruction at f(XIN) = 20 MHz)
20 MHz (Max.)
(Note)
(Note)
16 Kbytes
8-bit ✕ 6
4-bit ✕ 2
5-bit ✕ 1
7-bit ✕ 3
3-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or Clock synchronous serial I/O) ✕ 2
10-bit successive approximation method ✕ 1 (4 channels)
12-bit ✕ 1
4 channels
Maximum transfer rate 20 Mbytes/sec.
(at f(XIN) = 20 MHz, 0 wait, 1-bus cycle transfer)
10 Mbytes/sec.
(at f(XIN) = 20 MHz, 0 wait, 2-bus cycles transfer)
1 channel
Incorporates 8-bit refresh timer.
Supports CAS before RAS refresh method or self refresh method.
Chip select area ✕ 4 (CS0–CS3). A wait number and bus width
can be set for each chip select area.
Real-time output
Interrupts
Clock generating circuit
Power supply voltage
Power dissipation
Ports’ input/output
characteristics
Memory expansion
Operating ambient temperature range
Device structure
Package
Note:
Flash memory M37920FCCGP, M37920FCCHP 120 Kbytes
(User ROM area) M37920FGCGP, M37920FGCHP 248 Kbytes
RAM M37920FCCGP, M37920FCCHP 4096 bytes
Input/Output withstand voltage
Output current
M37920FGCGP, M37920FGCHP 6144 bytes
4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel
6 external types, 20 internal types. Each interrupt except NMI
can be set to a priority level within the range of 0–7 by software.
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator).
5 V±0.5 V
125 mW (at f(XIN) = 20 MHz)
5 V
5 mA
Up to 16 Mbytes. Note that bank FF16 is a reserved area.
–20 to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONS (Flash memory mode)
Power supply voltage
Programming/Erase voltage
Flash memory mode
Block division for erasure
Programming method
Erase method
Programming/Erase control
Data protection method
Number of commands
Maximum number of reprograms
User ROM area
Boot ROM area
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
FunctionsParameter
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
3 modes: parallel I/O, serial I/O, and CPU reprogramming modes
(Note 1)
1 block (16 Kbytes ✕ 1) (Note 2)
Programmed per page (in a unit of 256 Kbytes)
User ROM area + Boot ROM area
User ROM area
User ROM area
Total erase/Block erase
User ROM area + Boot ROM area
User ROM area
User ROM area
Programming/Erase control by software commands
Protected per block, by using a lock bit.
8 commands
100
Notes 1:
User ROM area
2:
On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.
Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode.
M37920FCCGP, M37920FCCHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes
M37920FGCGP, M37920FGCHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION (MICROCOMPUTER MODE)
NamePin
Vcc, Vss
MD0
MD1
RESET
XIN
XOUT
BYTE
AVcc,
AVss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40–P44
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
External data bus width
select input
Analog power supply input
Reference voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Input/
Output
—
Apply 5 V±0.5 V to Vcc, and 0 V to Vss.
Input
Input
Input
Input
Output
Input
Input
This pin controls the processor mode. Connect this pin to VSS for the single-chip
mode or memory expansion mode, and VCC for the microprocessor mode.
Connect this pin to Vss.
The microcomputer is reset when “L” level is applies to this pin.
These are input and output pins of the internal clock generating circuit. Connect a
ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an
external clock is used, the clock source should be connected to the XIN pin, and the
XOUT pin should be left open.
This pin determines whether the external data bus has an 8-bit width or 16-bit width
for the memory expansion mode or microprocessor mode. The width is 16 bits when
“L” signal is input, and 8 bits when “H” signal is input.
—
Power supply input pin for the A-D converter. Connect AVcc to Vcc, and AVss to Vss
externally.
This is the reference voltage input pin for the A-D converter.
I/O
■ In single-chip mode
Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin
can be programmed for input or output. These pins enter the input mode at
reset.
■ In memory expansion and microprocessor modes
Address (A16–A23) is output. In DRAM space is accessed, Multiplexed address
(MA8–MA11) is output.
■ In single-chip mode
I/O
I/O
I/O
I/O
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
The low-order 8 bits of data (D0–D7) are input/output.
■ In single-chip mode or when 8-bit external data bus is used with “H” level applied
to pin BYTE in memory expansion or microprocessor mode
These pins have the same functions as port P0.
■ When the 16-bit external data bus is used with “L” level applied to pin BYTE in
memory expansion or microprocessor mode
The high-order 8 bits of data (D8–D15) are input or output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P30 functions as an I/O port pin. According to the register setting, this pin funtions
as an output pin of RDY. P31, P32, P33 funtion as output pins of RD, BLW, BHW,
respectively.
■ In microprocessor mode
P30 functions as an input pin of RDY; and P31, P32, P33 function as output pins of
RD, BLW, BHW, respectively.
■ In single-chip mode
These pins have the same functions as port P0. P42 also funtions as pin TC.
■ In memory expansion mode
P40–P44 function as I/O port pins. According to the register setting, these pins
function as output pins or input pins of ALE, φ1, TC, HOLD, HLDA, respectively.
■ In microprocessor mode
P40 and P41 function as outpout pins of ALE, φ1. According to the register setting,
these pins also funtion as I/O port pins. P42 funtions as an I/O port pin. According to the register setting, this pin also funtions as pin TC. P43 functions as an input pin of HOLD, and P44 functions as an output pin of HLDA.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
Functions
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
P50–P57
P60–P66
P70–P73
P80–P86
P90–P96
P100–P107
P110–P117
P120–P122
NMI
NamePin
I/O port P5
I/O port P6
I/O port P7
I/O port P8
I/O port P9
I/O port P10
I/O port P11
I/O port P12
Non-maskable interrupt
Input/
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Functions
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timers A0, A2, and output pins for the real-time output.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timers A1, A3, A4, input pins for DMA requests,
and output pins for DMA acknowledge signals.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as input pins for the A-D converter. P72 and P73 also function as
input pins for INT3 and INT4.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for UART0, UART1.
■ In single-chip mode
These pins have the same function as port P0.
■ In memory expansion or microprocessor mode
According to the software setting, P90–P93 also funtion as chip select output
pins. While DRAM space is selected, P94–P96 function as output pins for DRAM
control signals. Some pins of P91–P93, coressponding to the selected DRAM
space, function as pins RAS.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A0–A7) is output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion or microprocessor mode
Address (A8–A15) is output. While DRAM space is accessed, Multiplexed address
(MA0–MA7) is output.
In addition to having the same functions as port P0 in the single-ship mode, these
pins also function as input pins for timers B0–B2.
This pin is for a non-maskable interrupt.
8
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
BASIC FUNCTION BLOCKS
These microcomputers contain the following devices on the single
chip: the flash memory, RAM, CPU, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial I/O,
A-D converter, I/O ports, clock generating circuit, etc.
MEMORY
Figures 1 and 2 show the memory maps. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16. Bank FF16 is a reserved area for the development
support tool. Therefore, do not use bank FF16.
000000
Bank 0
Bank 1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FE
Bank FF
00FFFF
010000
01FFFF
FE0000
FEFFFF
FF0000
FFFFFF
16
16
16
16
16
16
16
16
Reserved area
for development
support tool
16
16
16
16
000000
0000FF
000800
0017FF
001800
001FFF
002000
00FFC0
00FFFF
Internal flash memory and internal RAM are assigned as shown in
Figures 1 and 2.
Addresses FFC016 to FFFF16 contain the RESET and the interrupt
vector addresses, and the interrupt vectors are stored there.
For details, refer to the section on interrupts.
Assigned to addresses 016 to FF16 are peripheral devices such as
I/O ports, A-D converter, UART, timers, interrupt control registers,
DMA controoler, DRAM controller, etc.
For the flash memory in the boot ROM area, refer to the section on
the flash memory mode.
16
Peripheral devices
control registers
16
16
Internal RAM
4096 bytes
16
16
16
16
16
16
Internal flash memory
120 Kbytes
(User ROM area)
00FFC0
00FFFE
Interrupt vector table
16
DMA3
DMA2
DMA1
DMA0
Reserved area
Address matching detect
Reserved area
Reserved area
INT
INT
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
NMI
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
4
3
2
1
0
Fig. 1 Memory map of M37920FCCGP and M37920FCCHP (Single-chip mode)
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Bank 0
16
Bank 1
16
Bank 2
16
Bank 3
16
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FE
16
16
Bank FF
000000
00FFFF
010000
01FFFF
020000
02FFFF
030000
03FFFF
FE0000
FEFFFF
FF0000
FFFFFF
16
16
16
16
16
16
16
16
16
16
16
16
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
000000
16
Peripheral devices
control registers
16
16
Internal RAM
6144 bytes
16
16
16
16
Internal flash memory
248 Kbytes
(User ROM area)
00FFC0
00FFFE
Interrupt vector table
16
DMA3
DMA2
DMA1
DMA0
Reserved area
Address matching detect
Reserved area
Reserved area
INT
INT
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
NMI
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
4
3
2
1
0
Reserved area
for development
support tool
0000FF
000800
001FFF
002000
00FFC0
00FFFF
Fig. 2 Memory map of M37920FGCGP and M37920FGCHP (Single-chip mode)
10
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Address (Hexadecimal notation)
000000
16
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
000013
000014
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
000021
000022
000023
000024
000025
000026
000027
000028
000029
00002A
00002B
00002C
00002D
00002E
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
Reserved area (Note)
16
Reserved area (Note)
Port P0 register
16
Port P1 register
16
16
Port P0 direction register
16
Port P1 direction register
16
Port P2 register
16
Port P3 register
Port P2 direction register
16
16
Port P3 direction register
16
Port P4 register
16
Port P5 register
16
Port P4 direction register
16
Port P5 direction register
16
Port P6 register
16
Port P7 register
16
Port P6 direction register
16
Port P7 direction register
16
Port P8 register
16
Port P9 register
16
Port P8 direction register
16
Port P9 direction register
16
Port P10 register
16
Port P11 register
16
Port P10 direction register
16
Port P11 direction register
16
Port P12 register
16
16
Port P12 direction register
16
16
A-D control register 0
16
A-D control register 1
16
A-D register 0
16
16
A-D register 1
16
16
A-D register 2
16
16
A-D register 3
16
16
16
16
16
16
16
16
16
16
UART0 transmit/receive mode register
16
UART0 baud rate register (BRG0)
16
UART0 transmit buffer register
16
16
UART0 transmit/receive control register 0
16
UART0 transmit/receive control register 1
16
UART0 receive buffer register
16
16
UART1 transmit/receive mode register
16
UART1 baud rate register (BRG1)
16
UART1 transmit buffer register
16
16
UART1 transmit/receive control register 0
16
UART1 transmit/receive control register 1
16
UART1 receive buffer register
16
Address (Hexadecimal notation)
Count start register
16
000040
000041
16
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
One-shot start register
16
16
Up-down register
16
Timer A clock division select register
16
16
Timer A0 register
16
16
Timer A1 register
16
16
Timer A2 register
16
16
Timer A3 register
16
16
Timer A4 register
16
16
Timer B0 register
16
16
Timer B1 register
16
16
Timer B2 register
16
Timer A0 mode register
16
Timer A1 mode register
16
Timer A2 mode register
16
Timer A3 mode register
16
Timer A4 mode register
16
Timer B0 mode register
16
16
Timer B1 mode register
16
Timer B2 mode register
Processor mode register 0
16
16
Processor mode register 1
16
Watchdog timer register
Watchdog timer frequency select register
16
16
Particular function select register 0
Particular function select register 1
16
16
Particular function select register 2
16
Reserved area (Note)
16
Debug control register 0
Debug control register 1
16
16
Address comparison register 0
16
16
16
Address comparison register 1
16
16
16
3
interrupt control register
INT
16
INT
4
interrupt control register
A-D conversion interrupt control register
16
16
UART0 transmit interrupt control register
UART0 receive interrupt control register
16
16
UART1 transmit interrupt control register
16
UART1 receive interrupt control register
16
Timer A0 interrupt control register
16
Timer A1 interrupt control register
16
Timer A2 interrupt control register
16
Timer A3 interrupt control register
16
Timer A4 interrupt control register
16
Timer B0 interrupt control register
Timer B1 interrupt control register
16
16
Timer B2 interrupt control register
16
INT
0
interrupt control register
16
1
interrupt control register
INT
16
INT
2
interrupt control register
Fig. 4 Location of SFRs (1)
Note: Do not write to this address.
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Address (Hexadecimal notation)
16
000080
000081
000082
000083
000084
000085
000086
000087
000088
000089
00008A
00008B
00008C
00008D
00008E
00008F
000090
000091
000092
000093
000094
000095
000096
000097
000098
000099
00009A
00009B
00009C
00009D
00009E
00009F
0000A0
0000A1
0000A2
0000A3
0000A4
0000A5
0000A6
0000A7
0000A8
0000A9
0000AA
0000AB
0000AC
0000AD
0000AE
0000AF
0000B0
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9
0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
control register L
0
CS
control register H
16
CS
0
16
control register L
1
CS
control register H
16
CS
1
control register L
16
CS
2
control register H
2
CS
16
control register L
16
CS
3
control register H
16
3
CS
16
16
Area
16
16
Area
16
16
Area
16
16
Area
16
16
16
16
16
16
16
16
16
16
16
16
16
Reserved area (Note)
16
Reserved area (Note)
16
Flash memory control register
16
16
Real-time output control register
16
Pulse output data register 0
16
16
Pulse output data register 1
16
16
Reserved area (Note)
16
16
16
DRAM control register
16
Refresh timer
16
16
16
CTS/RTS separate select register
16
16
16
16
DMAC control register L
16
DMAC control register H
16
DMA0 interruput control register
16
DMA1 interruput control register
16
DMA2 interruput control register
16
DMA3 interruput control register
16
16
16
16
16
16
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
start address register
CS
0
start address register
CS
1
start address register
CS
2
start address register
CS
3
Address (Hexadecimal notation)
0000C0
0000C1
0000C2
0000C3
0000C4
0000C5
0000C6
0000C7
0000C8
0000C9
0000CA
0000CB
0000CC
0000CD
0000CE
0000CF
0000D0
0000D1
0000D2
0000D3
0000D4
0000D5
0000D6
0000D7
0000D8
0000D9
0000DA
0000DB
0000DC
0000DD
0000DE
0000DF
0000E0
0000E1
0000E2
0000E3
0000E4
0000E5
0000E6
0000E7
0000E8
0000E9
0000EA
0000EB
0000EC
0000ED
0000EE
0000EF
0000F0
0000F1
0000F2
0000F3
0000F4
0000F5
0000F6
0000F7
0000F8
0000F9
0000FA
0000FB
0000FC
0000FD
0000FE
0000FF
16
Source address
16
Source address
16
Source address
16
16
Destination address
16
Destination address
16
Destination address
16
16
Transfer counter
16
Transfer counter
16
Transfer counter
16
16
DMA0 mode
16
DMA0 mode
16
DMA0 control
16
16
Source address
16
Source address
16
Source address
16
16
Destination address
16
Destination address
16
Destination address
16
16
Transfer counter
16
Transfer counter
16
Transfer counter
16
16
DMA1 mode
16
DMA1 mode
16
DMA1 control
16
Source address
16
Source address
16
Source address
16
16
Destination address
16
Destination address
16
Destination address
16
16
16
Transfer counter
16
Transfer counter
16
Transfer counter
16
16
DMA2 mode
16
DMA2 mode
16
DMA2 control
16
16
Source address
16
Source address
16
Source address
16
16
Destination address
16
Destination address
16
Destination address
16
16
Transfer counter
16
Transfer counter
16
Transfer counter
16
16
DMA3 mode
16
DMA3 mode
16
DMA3 control
16
register 0 L
register 0 M
register 0 H
register 0 L
register 0 M
register 0 H
register L
register H
register
register 1 L
register 1 M
register 1 H
register 1 L
register 1 M
register 1 H
register L
register H
register
register 2 L
register 2 M
register 2 H
register 2 L
register 2 M
register 2 H
register L
register H
register
register 3 L
register 3 M
register 3 H
register 3 L
register 3 M
register 3 H
register L
register H
register
register 0 L
register 0 M
register 0 H
register 1 L
register 1 M
register 1 H
register 2 L
register 2 M
register 2 H
register 3 L
register 3 M
register 3 H
Note: Do not write to this address.
Fig. 5 Location of SFRs (2)
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
CENTRAL PROCESSING UNIT (CPU)
The CPU has 13 registers, and they are shown in Figure 6. Each of
these registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. Data
length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is
“0” and as an 8-bit register when flag m is “1”. Flag m is a part of the
processor status register (PS) which is described later.
Data operations such as calculations, data transfer, input/output,
etc., are executed mainly through accumulator A.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use
of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
ACCUMULATOR E
Accumulator E is a 32-bit register and consists of accumulator A
(low-order 16 bits) and accumulator B (high-order 16 bits). It is used
for 32-bit data processing.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. Index register length flag x determines whether the
register is used as 16-bit register or as 8-bit register. It is used as a
16-bit register when flag x is “0” and as an 8-bit register when flag x
is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register X is used as the index
register, the contents of this address are added to obtain the real address.
Index register X functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when flag
x is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register Y is used as the index
register, the contents of this address are added to obtain the real address.
Index register Y functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
15 7 0
31
70
PG Program bank register PG
70
Fig. 6 Register structure
B
H
Accumulator B
Data bank register DTDT
B
L
Accumulator A
15 7 0
Accumulator E
1570
1570
15
1570
15 0
15 0
15 0
15
00000
A
H
A
H
B
H
X
H
H
Y
IPL2IPL1IPL
7
S
PC
DPR0 to DPR3
7
0
NVmxD I ZC
A
L
A
L
B
L
X
L
Y
L
0
0
Index register X
Index register Y
Stack pointer S
Program counter PC
Direct page registers DPR0 to DPR3
0
Processor status register PS
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing mode.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3)
The direct page register is a 16-bit register. An addressing mode of
which name includes ‘direct’ generates an address of data to be accessed, regarding the contents of this register as the base address.
The 7900 Series has been expanded direct page registers up to 4
(DPR0 to DPR3), in comparison to the 7700 Series which has the
single direct page register. Accordingly, the 7900 Series’s direct addressing method which uses direct page registers differs from that of
the 7700 Series. However, the conventional direct addressing
method, using only DPR0, is still be selectable, in order to make use
of the 7700 Series software property. For more details, refer to the
section on the direct page.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of
flags to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V , and
N.
The details of each bit of the processor status register are described
below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
watchdog timer, NMI, and software interrupt are disabled. This flag
is set to “1” automatically when an interrupt is accepted. It can be set
and reset directly with the SEI and CLI instructions or SEP and CLP
instructions.
___
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when data length flag m is “0” and with
two digits when it is “1”. Decimal adjust is automatically performed.
(Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it
is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtraction is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
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8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, data’s bit 15 is
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other
cases. It can also be set and reset with the SEP and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than
the processor interrupt priority . When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level
of the device requesting the interrupt. Refer to the section on interrupts for more details.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
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BANK
In order to effectively use the integrated hardware on the chip, this
CPU core uses an address generating method with a 24-bit address
split into high-order 8 bits and low-order 16 bits. In other words, the
64 Kbytes specified by the low-order 16 bits are one unit (referred to
as “bank”), and the address space is divided into 256 banks (016 to
FF16) specified by the high-order 8 bits.
In the program area on the address space, the bank is specified by
the program bank register (PG), and the address in the bank is
specified by the program counter (PC).
As for each bank boundary, when an overflow has occurred in PC,
the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the
normal conditions, therefore, programming without concern for the
bank boundaries is possible. Furthermore, as for the data area on
the address space, the bank is specified by the data bank register
(DT), and the address in the bank is specified by the operation result
by using the various addressing modes (Note).
Note: Some addressing modes directly specify a bank.
DIRECT PAGE
The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The
direct page and direct addressing modes have been provided for the
effective access to bank 016. In the 7900 Series, two types of direct
addressing modes are available: the conventional direct addressing
mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected
according to the contents of bit 1 of the processor mode register 1.
This bit 1 is cleared to “0” at reset. (In other words, the conventional
direct addressing mode is selected.) However, once this bit 1 has
been set to “1” by software, this bit cannot be cleared to “0” again,
except by reset. That is to say , when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is
running.
Refer to “7900 Series Software Manual” for details concerning the
various addressing modes which use the direct page area.
Instruction Set
The CPU core of the 7900 Series has an expanded instruction set
based on the existing 7700/7751 Series’ CPU core. In addition, its
source code (mnemonic) has the complete upper compatibility with
the 7700 Series instruction set.
For details concerning addressing modes and instruction set, refer to
“7900 Series Software Manual”.
■ Conventional direct addressing mode
The direct page area consists of 256-byte space. Its bank address is
“0016”, and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an
instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area.
■ Expanded direct addressing mode
The direct page area consists of four 64-byte spaces. Their bank
address is “0016”, and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct
page registers. In this expanded direct addressing mode, a value (1
byte) just after an instruction code is regarded as follows:
• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
• Low-order 6 bits: regarded as an offset value for the selected direct
page register.
Then, the CPU accesses each address in each direct page area:
16
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
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BUS INTERFACE UNIT
Data transfer shown below is always performed via the bus interface
unit (BIU), which is located between the CPU and the internal buses:
• Between the CPU and the internal memory, internal peripheral devices, external areas
• Between the DMA controller (DMAC) and the internal memory, internal peripheral devices, external areas
Figure 7 shows the BIU and the bus structure. The CPU and BIU, or
DMAC and BIU are connected by a dedicated bus respectivery, and
any transfer between the CPU and BIU, or DMAC and BIU is controlled by this dedicated bus.
On the other hand, data transfer between the BIU and internal peripheral devices uses the following internal common buses: 32-bit
code bus, 16-bit data bus, 24-bit address bus, and control signals.
The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/
data bus method) is employed in order to improve data transfer ca-
Central
Processing
Unit
(CPU)
CPU bus
Bus
Interface
Unit
(BIU)
Internal code bus (CB0 to CB31)
Internal data bus (DB0 to DB15)
Internal address bus (AD0 to AD23)
Internal control signal
pabilities. As a result, the internal memory is connected to both the
code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus.
Each width of external buses are as follows: a 24-bit address bus,
16-bit data bus.
The external data bus transfers instruction codes and data. When
the code or data access occurs for the external, the external access
is performed via the bus conversion circuit.
When the DRAM is selected in external devices, the internal DMAC
controller (DRAMC) is operated, and access for DRAM and DRAM
refresh operation become enabled. For details, refer to the section
on the chip select wait controller and DRAMC described later.
When accessing the external devices, it is possible to insert the recovery cycles. Refer to the section on the processor modes and chip
select wait controller described later.
When the burst ROM is used as an external device, refer to the section on the chip select wait controller described later.
Internal bus
Internal
memory
DMA
controller
(DMAC)
SFR : Special Function Register
❈ The CPU bus, DMAC bus, internal bus, and external bus separate out independently.
DMAC bus
Refresh request
Hold request
Fig. 7 BIU and bus structure
Internal
peripheral
devices
(SFR)
DRAM
controller
(DRAMC)
conversion
circuit
Bus
External bus
DRAM control signal
A0 to A23 (MA0 to MA11)
D
0
to D
7
D8 to D
15
Control signal
HOLD
HLDA
External
devices
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
BIU structure
The BIU consists of four registers shown in Figure 8. Table 1 lists the
functions of each register.
Table 1. Functions of each register
Name
Program address register
Instruction queue buffer
Data address register
Data buffer
Indicates a storage address for an instruction to be next taken into an instruction queue buffer.
Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes.
Indicates an address where data will be next read from or written to.
Temporarily stores data which has been read from internal memory, internal peripheral devices, and
external areas by the BIU; or temporarily stores data which is to be written to internal memory, internal
peripheral devices, and external areas by the CPU or DMAC. Consists of 32 bits.
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Functions
Fig. 8 Register structure of BIU
b23
PA
b23 b0
DA
b31 b0
DQ
b0
b7 b0
Q0
Q9
Program address register
Instruction queue buffer
Data address register
Data buffer
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
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BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory, internal peripheral devices, or external areas, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
(3) Data write operation
When executing an instruction for writing data into the internal
memory, internal peripheral devices, or external area, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory, internal peripheral devices,
external areas. This operation is called “bus cycle”. The bus cycle is
affected by the following conditions at instruction prefetch and data
access.
[Instruction prefetch]
• Whether the address area locates in the internal area or the external area.
• When the address area locates in the external area
➀ Whether the bus width of external devices = 16 bits or 8 bits:
(a) When the external bus width = 16 bits:
whether the start address for access locates at a 4byte boundary or at an 8-byte boundary.
(b) When the external bus width = 8 bits:
whether the start address for access locates at an
even-numbered address, a 4-byte boundary or at the 8byte bound ary.
➁ Whether the prefetch operation is generated by a branch, or
not.
➂ Number of waits
➃ Others: Whether any the burst ROM access and the DRAM
space is specified or not. (For details, refer to the section on
the chip select wait controller and DRAM controller described
later.)
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
AD2 (A2)
Even-numbered address
4-byte boundary
8-byte boundary
X: 0 or 1
[Data Access]
• Whether the address area locates in the internal area or the external area.
• Length of data to be transferred: byte, word, double word
• When the address area locates in the external area:
➀ Whether the bus width of external devices = 16 bits or 8 bits:
➁ Number of waits
➂ Others: Whether the DRAM space is specified or not. (For
details, refer to the section on the chip select wait controller
and DRAM controller described later.)
The BIU controls the bus cycle depending on the above conditions.
Instruction prefetch and data access are performed as shown in
Tables 3 to 10.
X
X
0
AD1 (A1)
X
0
0
AD0 (A0)
0
0
0
19
PRELIMINARY
Access to internal area
Access to external area
When address locates at 4-byte boundary or when branched:
double consecutive access
When branched or at instruction
prefetch
When external data bus width = 16 bits When external data bus width = 8 bits
φ
BIU
Internal address bus
Internal code bus
CB
31
to CB
0
Code
φ
1
A
23
to A
0
D
7
to D
0
D
15
to D
8
ALE
RD
BLW
BHW
D
7
to D
0
D
7
to D
0
D
15
to D
8
D
15
to D
8
Address Address + 2
When address of instruction to be prefetched locates at 8-byte boundary:
quadruple consecutive access
φ
1
A
23
to A
0
D
7
to D
0
D
15
to D
8
ALE
RD
BLW
BHW
D
7
to D
0
D
7
to D
0
D
7
to D
0
D
7
to D
0
D
15
to D
8
D
15
to D
8
D
15
to D
8
D
15
to D
8
Address Address + 2
Address + 4 Address + 6
When address is even-numbered address or when branched:
double consecutive access
φ
1
A
23
to A
0
D
7
to D
0
ALE
RD
BLW
BHW
D
7
to D
0
D
7
to D
0
Address Address + 1
When address of instruction to be prefetched locates at 4-byte boundary or
8-byte boundary: quadruple consecutive access
φ
1
A
23
to A
0
D
7
to D
0
ALE
RD
BLW
BHW
D
7
to D
0
D
7
to D
0
D
7
to D
0
D
7
to D
0
Address Address + 1
Address + 2 Address + 3
Internal RAM
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
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20
Table 3. Instruction prefetch
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 4. Data access (1)
Access starting from even-numbered address Access starting from odd-numbered address
φ
1
A23 to A
0
D7 to D
Byte
data
read
D15 to D
ALE
BLW
BHW
0
8
RD
Address
D7 to D
Invalid
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φ
1
A23 to A
0
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
Address
Invalid
D15 to D
8
φ
1
A23 to A
0
D7 to D
Byte
data
written
Word
External data bus width = 16 bits
data
read
D15 to D
ALE
BLW
BHW
φ
1
A23 to A
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
0
8
RD
Address
D7 to D
Address
D7 to D
D15 to D
φ
1
A23 to A
0
D7 to D
D15 to D
ALE
BLW
BHW
φ
1
A23 to A
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
0
8
RD
0
0
8
Address
D15 to D
8
Address Address + 1
Invalid
D15 to D
8
D7 to D
Invalid
0
Word
data
written
φ
1
A23 to A
D7 to D
D15 to D
ALE
BLW
BHW
RD
φ
1
0
0
8
Address
D7 to D
D15 to D
A23 to A
0
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
8
Address Address + 1
D7 to D
D15 to D
8
0
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 5. Data access (2)
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Access starting from even-numbered address
φ
1
A23 to A
0
D7 to D
D15 to D
ALE
BLW
BHW
φ
1
A23 to A
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
0
8
RD
Double
word
data
read
Double
External data bus width = 16 bits
word
data
written
Address Address + 1
D7 to D
D15 to D
Address Address + 1
D7 to D
D15 to D
Access starting from odd-numbered address
φ
1
A23 to A
0
D7 to D
D15 to D
ALE
BLW
BHW
φ
1
A23 to A
D7 to D
D15 to D
ALE
BLW
BHW
0
8
RD
0
0
8
RD
D7 to D
D15 to D
D7 to D
D15 to D
0
8
0
8
0
8
0
8
Address Address + 1 Address + 2
Invalid
D15 to D
8
D7 to D
D15 to D
0
8
D7 to D
Invalid
Address Address + 1 Address + 2
D7 to D
D15 to D
0
8
D15 to D
8
D7 to D
0
0
22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 6. Data access (3)
Access starting from even- or odd-numbered address
φ
1
A23 to A0
D7 to D0
D15 to D8
Byte
data
read
ALE
RD
BLW
BHW
(Note)
(Note)
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Address
D7 to D0
φ
1
A23 to A0
D7 to D0
D15 to D8
Byte
data
written
External data bus width = 8 bits
Word
data
read
Word
data
written
ALE
BLW
BHW
φ
A23 to A0
D7 to D0
D15 to D8
ALE
BLW
BHW
φ
A23 to A0
D7 to D0
D15 to D8
ALE
BLW
BHW
(Note)
RD
(Note)
1
(Note)
RD
(Note)
1
(Note)
RD
(Note)
Address
Address Address + 1
Address Address + 1
D7 to D0
D7 to D0D7 to D0
D7 to D0D7 to D0
Note: When the voltage level at pin BYTE = “L”, functions as pins D15 to D8 are valid.
However, when 8-bit width is selected as the external bus width by the chip select
15
wait controller, the functions as pins D
to D8 and BHW become invalid.
When the voltage level at pin BYTE = “H”, these pins function as programmable
I/O port (P2) pins.
23
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 7. Data access (4)
Access starting from even- or odd-numbered address
φ
1
A23 to A
0
D7 to D
Double
word
data
read
0
D15 to D8(Note)
ALE
RD
BLW
BHW
(Note)
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Address Address + 1 Address + 2 Address + 3
D7 to D
D7 to D
0
0
D7 to D
0
D7 to D
MITSUBISHI MICROCOMPUTERS
0
φ
1
A23 to A
0
D7 to D
Double
word
External data bus width = 8 bits
data
written
0
D15 to D8(Note)
ALE
RD
BLW
BHW
(Note)
Address Address + 1 Address + 2 Address + 3
D7 to D
D7 to D
0
0
D7 to D
0
D7 to D
0
Note: When the voltage level at pin BYTE = “L”, functions as pins D15 to D8 are valid. However, when 8-bit width is selected as
the external bus width by the chip select wait controller, the functions as pins D15 to D8 and BHW become invalid. When
the voltage level at pin BYTE = “H”, these pins function as programmable I/O port (P2) pins.
24
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 8. Wait number (Instruction prefetch or data access)
Access to internal area Access to external area
φ
BIU
Internal address bus
Internal code bus
CB
31
to CB
0
φ
BIU
Internal address bus
Internal data bus
DB
15
to DB
0
Code
Data
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
A23 to A
External data bus
0-wait access
φ
1
0
ALE
RD,
BLW,
BHW
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Data
1-wait access
φ
1
A23 to A
External data bus
ALE
RD,
BLW,
BHW
2-wait access
φ
1
A23 to A
External data bus
ALE
RD,
BLW,
BHW
0
Data
0
Data
ALE expansion wait access
φ
1
A23 to A
0
External data bus
ALE
RD,
BLW,
BHW
Data
25
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
At double consecutive access (when address locates at 4-byte boundary or when branched)
φ
1
A23 to A0
ALE
RD
At quadruple consecutive access (when address locates at 8-byte boundary)
Instruction prefetch
Address
Address + 2
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Recovery
cycle
Next access cycle
Address
φ
1
A23 to A0
ALE
RD
Address Address + 4
Note: External data bus width = 16 bits and at 0 wait.
Fig. 9 Recovery cycle (at instruction prefetch)
Access
cycle
φ1
A23 to A0
ALE
RD,
BLW, BHW
Recovery
cycle
Address
Instruction prefetch
Address + 2
Next access cycle
Address + 6
Next access cycle
Address
Note: At 0 wait.
Fig. 10 Recovery cycle (at data access)
26
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
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Selection of processor mode
Figures 11, 12 show the bit configurations of the processor mode
registers 0, 1.
Any of the three processor modes (single-chip mode, memory expansion mode, microprocessor mode) can be selected with the following:
• Processor mode bits of the processor mode register 0 (bits 1 and 0
at address 5E16; Figure 11)
Table 9 lists the selection method of a processor mode.
The memory map which the CPU can access depends on the selected processor mode. Figure 13 shows the memory maps in three
processor modes.
Also, the functions of ports P0 to P4, P10, P11, and part of port P9
depend on the selected processor mode. For details, see Table 10.
In the single-chip mode, ports P0 to P4, P10, P11, and P9 function
as I/O ports. In this mode, only the internal area (SFRs, internal
76543210
Processor mode register 0
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
RAM, internal ROM) is accessible.
In the memory expansion and microprocessor modes, external devices assigned in the external memory area can be connected via
buses. Therefore, ports P0 to P4, P10, P1 1, and part of port P9 function as I/O pins for the address bus, data bus, bus control signals.
(Some of port functions are selectable.)
In the memory expansion mode, all of the internal area (SFRs, internal RAM, internal ROM) and external area are accessible. In the microprocessor mode, the internal area except for the internal ROM (in
other words, SFRs and internal RAM) and the external area are accessible.
Note that, when the external devices are located to an area where
the internal area and external area overlap, only the internal area
can be read/written; the external area cannot be read/written.
Table 11 lists each bus control signal’s function.
Address
16
5E
Fig. 11 Bit configuration of processor mode register 0
External bus wait number select bits
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait
Interrupt priority detection time select bits
0 0 : 7 cycles of φ
0 1 : 4 cycles of φ
1 0 : 2 cycles of φ
1 1 : Do not select.
Software reset bit
By a write of “1” to this bit, the microcomputer will be reset, and then, restarted.
1
output select bit
Clock φ
1
output is disabled. (P41 functions as an programmable I/O port pin.)
0 : φ
1
output is enabled. (P41 functions as the clock φ1 output pin.)
1 : φ
27
PRELIMINARY
g
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
76543210
00
Notes 1: After reset, this bit’s contents can be switched only once. During the software execution, be sure not to switch this bit’s contents.
2: In the single-chip mode, these bits’ functions are disabled regardless of these bits’ contents.
SS
3: While V
4: In the memory expansion or microprocessor mode, if this bit’s contents is switched from “1” to “0”, this bit will be cleared to “0”.
5: In the microprocessor mode, this bit is invalid.
level voltage is applied to pin MD0, each of these bits is “0” at reset. While VCC level voltage is applied to pin MD0,
on the other hand, each of these bits is “1” at reset.
After this clearance, this bit cannot return to “1”. If it is necessary to set this bit to “1”, be sure to reset the microcomputer.
When the internal flash memory is repro
Processor mode register 1
Fix this bit to “0”.
Direct page register switch bit (Note 1)
0 : Only DPR0 is used.
1 : DPR0 to DPR3 are used.
RDY input select bit (Notes 2 to 4)
0 : RDY input is disabled. (P3
1 : RDY input is enabled. (P3
ALE output select bit (Notes 2 and 3)
0 : ALE output is disabled. (P4
1 : ALE output is enabled. (P4
Recovery cycle insert select bit (Notes 2 and 3)
0 : No recovery cycle is inserted at access to the external area.
1 : Recovery cycle is inserted at access to the external area.
HOLD input, HLDA output select bit (Notes 2 to 4)
0 : HOLD input and HLDA output are disabled.
3
and P44 function as programmable I/O port pins.)
(P4
1 : HOLD input and HLDA output are enabled.
3
and P44 function as pins HOLD and HLDA, respectively.)
(P4
“0” at read.
Internal ROM access wait bit (Note 5)
0 : 1 wait
1 : 0 wait
rammed in the CPU reprogramming mode, be sure to clear this bit to “0”.
Address
16
5F
0
functions as a programmable I/O port pin.)
0
functions as pin RDY.)
0
functions as a programmable I/O port pin.)
0
functions as pin ALE.)
Fig. 12 Bit configuration of processor mode register 1
Table 9. Selection method of processor mode
MD0
• Single-chip mode
•
VSS
• Microprocessor mode
Mode
Memory expansion mode
Description
After reset is removed, the
single-chip mode is selected.
By changing the processor
mode bits’ contents by software, the single-chip mode,
memory expansion mode or
microprocessor mode can be
selected.
• Microprocessor mode
VCC
After reset is removed, the microprocessor mode is selected.
Single-chip
mode
0
16
SFR
FF
16
Unused area
RAM
Unused area
ROM
FEFFFF
FFFFFF
: External memory area.
Note: Do not access this area.
Memory expansion
mode
SFR
RAM
ROM
16
FF0000
16
Reserved area
(Note)
16
Microprocessor
mode
SFR
RAM
Reserved area
(Note)
28
Fig. 13 Memory maps in three processor modes
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 10. Relationship between processor modes, memory area, and port function
Single-chip mode
Mode
(Note 1)
Pin MD0
Processor mode
bits (Note 2)
SFR area
Internal RAM area
Internal ROM area
Other area
Memory area
Port pins P100 to P107
Port pins P110 to P1 17
Port pins P00 to P07
External data bus
Port pins
P10 to P17
width = 16 bits
External data bus
VSS level voltage is applied
00
SFR area
Internal RAM area
Internal ROM area
(Do not access.)
I/O port pins P100 to P107
I/O port pins P110 to P117
I/O port pins P00 to P07
I/O port pins P10 to P17
width = 8 bits
I/O port pins P20 to P27
I/O port pin P30
I/O port pin P31
I/O port pin P32
Port pins
P20 to P27
Port pin P30
Port pin P31
Port pin
P32
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
External data bus
width = 8 bits
Port pin
P33
External data bus
width = 16 bits
External data bus
I/O port pin P33
width = 8 bits
Port pin P40
Port pin P41
Port pin P42
Port pin P43
Port pin P90
Port pins P91 to P93
Notes 1: For details of the processor mode setting, see Table 9.
2: Processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5E
3: While DRAM space is accessed, the multiplexed address is output.
4: In the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5E
3 can operate as pins for RDY input, ALE output, φ1 output, HLDA output, HOLD input, respectively.
P4
In the microprocessor mode, by the above select bits, the above pins (RDY, ALE,
tively.
5: In the memory expansion mode, port pin P9
6: In the memory expansion and microprocessor modes, port pins P91 to P93 can operate as the CS1/CS2/CS3 output pins by the CSi output select bits (i =
1 to 3) (bit 7s at addresses 82
I/O port pin P40
I/O port pin P41
Clock
φ
1 is output (Note 4).
I/O port pin P42
I/O port pin P43
I/O port pin P90
I/O port pins P91 to P93
16, 8416, 8616).
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Memory expansion mode
VSS level voltage is applied
01
SFR area
Internal RAM area
Internal ROM area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is output.
Multiplexed address (MA0 to MA7) is output
(Note 3)
High-order address (A16 to A23) is output.
Multiplexed address (MA8 to MA11) is out-
put (Note 3)
Low-order data (D0 to D7, data at even-
numbered address) is input/output.
Low-order data (D0 to D7, data at even-/
odd-numbered address) is input/output.
Low-order data (D0 to D7, data at odd-num-
bered address) is input/output.
I/O port pins P20 to P27
I/O port pin P30
Ready signal RDY is input (Note 5).
Read signal RD is output.
Write signal BLW (write to even-numbered
address) is output.
Write signal BLW (write to even-/odd-num-
bered address) is output.
Write signal BHW (write to odd-numbered
address) is output.
I/O port pin P33
I/O port pin P40
Address latch enable signal ALE is output (Note 4).
I/O port pin P41
Clock
φ
1 is output (Note 4).
I/O port pin P42
Hold acknowledge signa HLDA is output (Note 4).
I/O port pin P43
Hold request signal HOLD is input (Note 4).
I/O port pin P90
Chip select signal CS0 is output (Note 5).
I/O port pins P91 to P93
C
hip select signals CS1 to CS3 are output (Note 6).
16).
φ
1, HLDA, HOLD) can operate as port pins P30, P40 to P43, respec-
0 can operate as the CS0 output pin by the CS0 output select bit of the CS0 control register L (bit 7 at address 8016).
Microprocessor mode
VCC level voltage is applied
10
SFR area
Internal RAM area
External memory area
External memory area
Low-order address (A0 to A7) is output.
Middle-order address (A8 to A15) is output.
Multiplexed address (MA0 to MA7) is
output (Note 3)
High-order address (A16 to A23) is output.
Multiplexed address (MA8 to MA11) is
output (Note 3)
Low-order data (D0 to D7, data at even-
numbered address) is input/output.
Low-order data (D0 to D7, data at even-/
odd-numbered address) is input/output.
Low-order data (D0 to D7, data at odd-
numbered address) is input/output.
I/O port pins P20 to P27
Ready signal RDY is input.
I/O port pin P30 (Note 5)
Read signal RD is output
Write signal BLW (write to even-num-
bered address) is output.
Write signal BLW (write to even-/odd-
numbered address) is output.
Write signal BHW (write to odd-num-
bered address) is output.
I/O port pin P33
Address latch enable signal ALE is output.
I/O port pin P40 (Note 4)
Clock
φ
1 is output.
I/O port pin P41 (Note 4)
Hold acknowledge signal HLDA is output.
I/O port pin P42 (Note 4)
Hold request signal HOLD is input.
I/O port pin P43 (Note 4)
Chip select signal CS0 is output.
I/O port pin P91 to P93
Chip select signals CS1 to CS3 are output (Note 6).
16, 5F16), port pins P30, P40 to
29
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 11. Each bus control signal’s function
Signal
RD
I/O
Output
Read signal. Outputs “L” at read from the external area.
MITSUBISHI MICROCOMPUTERS
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Function
Remarks
BLW
BHW
ALE
φ
1
RDY
HOLD
HDLA
CS0–CS3
BYTE
Output
Write signal. Outputs “L” at write to the external area.
Output
Address latch enable signal. Outputs “H” level pulse in the
period just before signals RD, BLW, BHW become “L”.
This is used to latch an address in the external.
Output
Internal standard clock’s output. Outputs system clock
(fsys).
Input
Ready signal. The “L” level period of the last
cess cycle for the external area (in other words, “L” level
period of RD, BLW, BHW) will be extended while “L” level
voltage is applied to this pin.
Input
Hold request signal. Appliance of “L” level voltage will generate a hold request; appliance of “H” level voltage will request to terminate the hold state.
Output
Hold acknowledge signal. Outputs “L” in the hold state.
Output
Chip select signal. Outputs “L” in access to the specified
chip select area.
Input
Input signal to select the external data bus width. When
this pin’s level = Vss, 16-bit width will be selected; and
when Vcc, 8-bit width will be selected.
φ
1 in the ac-
For operation differences between BLW and BHW depending on the external data bus width, see Table 5.
In order to latch an address with signal ALE, do as follows:
• While ALE = “H”, be sure to open a latch, so the address
will pass it.
• While ALE = “L”, be sure to hold the address.
Acceptance and termination of a hold request is performed
at completion of the bus cycle while the BIU operates.
In the hold state, A
CS0–CS3 enter the floating state. At termination of the hold
state, simultaneously with the timing when HLDA becomes
“H” level, the above floating state is terminated. Then, bus
access will be restarted 1 cycle of
In the hold state, also, the CPU operates with access to
the internal area. If the CPU accesses the external area, in
the hold state, the CPU stops its operation.
For details, refer to the section on the chip select wait controller.
When BYTE = Vss level, by the register setting, each chip
select area (CS1 to CS3) can have the 8-bit data bus, independently.
For details, refer to the section on the chip select wait controller.
0–A23, D0–D15, RD, BLW, BHW, ALE,
φ
1 after.
30
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