Mitsubishi M37905M8C-XXXSP, M37905M8C-XXXFP, M37905M6C-XXXSP, M37905M6C-XXXFP, M37905M4C-XXXSP Datasheet
...
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
DESCRIPTION
These are single-chip 16-bit microcomputers designed with high-performance CMOS silicon gate technology, being packaged in 64-pin
plastic molded QFP or shrink plastic molded SDIP. These microcomputers support the 7900 Series instruction set, which are enhanced
and expanded instruction set and are upper-compatible with the
7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data.
Also, they are suitable for motor-control equipment since each of
them includes the motor control circuit.
DISTINCTIVE FEATURES
Number of basic machine instructions .................................... 203
•
Memory
•
[M37905M4C-XXXFP, M37905M4C-XXXSP]
ROM .............................................................................. 32 Kbytes
RAM .............................................................................1024 bytes
[M37905M6C-XXXFP, M37905M6C-XXXSP]
ROM .............................................................................. 48 Kbytes
RAM .............................................................................3072 bytes
[M37905M8C-XXXFP, M37905M8C-XXXSP]
ROM .............................................................................. 60 Kbytes
RAM .............................................................................3072 bytes
Instruction execution time
•
The fastest instruction at 20 MHz frequency ........................ 50 ns
Single power supply .................................................... 5 V ± 0.5 V
•
Interrupts ........... 8 external sources, 23 internal sources, 7 levels
•
Multi-functional 16-bit timer ................................................. 10 + 3
•
(Three-phase motor drive waveform and Pulse motor drive waveform output are available.)
Serial I/O (UART or Clock synchronous)..................................... 3
•
10-bit A-D converter .......................................... 12-channel inputs
•
8-bit D-A converter ............................................2-channel outputs
•
12-bit watchdog timer
•
Programmable input/output (ports P1, P2, P4, P5, P6, P7, P8) .. 50
•
APPLICATION
Control devices for office equipment such as copiers and facsimiles
Control devices for industrial equipment such as communication
and measuring instruments
Control devices for equipment, requiring motor control, such as
inverter air conditioners and general-purpose inverters
M37905MxC-XXXFP PIN CONFIGURATION (TOP VIEW)
0
P12/RXD
P11/CTS0/CLK
P10/CTS0/RTS
AV
V
AV
P83/AN11/TXD
P82/AN10/RXD
P81/AN9/CTS2/CLK
P80/AN8/CTS2/RTS2/DA
P77/AN7/DA
P76/AN
P75/AN
P74/AN
1
1
/CLK
/RTS
1
1
1
0
/RxD
/CTS
/CTS
/TxD
6
5
4
3
P1
P1
P1
P1
0
0
0
V
CC
CC
REF
SS
V
SS
2
2
2
1
0
6
5
4
48474645444342414039383736
49
50
51
52
53
54
55
56
M37905MXC-XXXFP
57
58
59
60
61
62
63
64
123456789
3
2
1
0
/AN
/AN
/AN
/AN
3
2
1
0
P7
P7
P7
P7
Outline 64P6N-A
OUT
1
/TA4
/TxD
0
7
P2
P1
2
3
/RTP1
/RTP1
IN
OUT
/TA3
7
/TA3
6
P6
P6
OUT
IN
/TA9
/TA4
2
1
P2
P2
0
1
/V/RTP1
/U/RTP1
IN
OUT
/TA2
5
/TA2
4
P6
P6
IN
/TA9
3
P2
3
/W/RTP0
IN
/TA1
3
P6
Note
)
)
IN
IN
(/TB1
(/TB0
5
4
P2
P2
10111213141516
2
1
/V/RTP0
/U/RTP0
IN
OUT
/TA0
1
/TA1
2
P6
P6
)
IN
(/TB2
6
P27P2
0
/IDU
IN
/W/RTP0
/TB2
7
OUT
/INT
7
/TA0
0
P5
P6
MD1
35
/IDV
IN
/TB1
6
/INT
6
P5
Note
1
/RTP2
/RTP2
IN
OUT
/TA5
/TA5
1
0
P4
P4
34
33
4
/IDW
/INT
IN
CUT
/TB0
5
P6OUT
/INT
5
P5
32
P42/TA6
OUT
/RTP2
CUT
2
3
OUT
/RTP3
0
1
OUT
/RTP3
2
3
/INT
0
1
TRG1
TRG0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P43/TA6IN/RTP2
P44/TA7
P45/TA7IN/RTP3
P46/TA8
P47/TA8IN/RTP3
P4OUT
P51/INT
P52/INT2/RTP
P53/INT3/RTP
V
SS
V
CONT
X
OUT
IN
X
RESET
MD0
Note : Allocation of pins TB0
can be switched by software.
IN to TB2IN
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
M37905MxC-XXXSP PIN CONFIGURATION (TOP VIEW)
2
/TxD
11
/AN
3
P8
2
/RxD
10
/AN
2
P8
P80/AN8/CTS
Note
P81/AN9/CTS2/CLK
2
/RTS2/DA1
P77/AN7/DA0
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P67/TA3IN/RTP13
P66/TA3OUT/RTP12
P65/TA2IN/U/RTP11
P64/TA2OUT/V/RTP10
P63/TA1IN/W/RTP03
P62/TA1OUT/U/RTP02
P61/TA0IN/V/RTP01
P60/TA0OUT/W/RTP00
P57/INT7/TB2IN/IDU
6/INT6/TB1IN/IDV
P5
5/INT5/TB0IN/IDW
P5
P6OUTCUT/INT4
P53/INT3/RTPTRG0
P52/INT2/RTPTRG1
MD0
RESET
XIN
XOUT
V
CONT
VSS
2
M37905M8C-XXXFP, M37905M8C-XXXSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Outline 64P4B
28
29
30
31
32
M37905M
X
C-XXXSP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
SS
V
AVSS
VREF
AVCC
VCC
P10/CTS0/RTS0
P11/CTS0/CLK0
P12/RxD0
P13/TxD0
P14/CTS1/RTS1
5/CTS1/CLK1
P1
P16/RxD1
P17/TxD1
P20/TA4OUT
P21/TA4IN
P22/TA9OUT
P23/TA9IN
P24(/TB0IN)
P25(/TB1IN)
6(/TB2IN)
P2
7
P2
Note
MD1
P40/TA5OUT/RTP20
P41/TA5IN/RTP21
P42/TA6OUT/RTP22
P43/TA6IN/RTP23
P44/TA7OUT/RTP30
P45/TA7IN/RTP31
P46/TA8OUT/RTP32
P47/TA8IN/RTP33
P4OUTCUT/INT0
P51/INT1
Note : Allocation of pins TB0IN to TB2IN
can be switched by software.
Outline 64P4B
2
Central Processing Unit (CPU)
Bus
Interface
Unit
(BIU)
RESET
MD1
V
Reference
Voltage Input
Instruction Register (8)
REF
(0V)
AV
SS
AV
CC
V
CC
X
Clock input
Clock Generating Circuit
Reset inputClock output
IN
X
OUT
Address Bus
Data Bus (Odd)
Data Bus (Even)
A-D Converter (12)
UART1 (9)
UART0 (9)
Watchdog Timer
Timer TB1 (16)
Timer TB2 (16)
Timer TB0 (16)
D-A
1
Converter (8)
Timer TA1 (16)
Timer TA2 (16)
Timer TA3 (16)
Timer TA4 (16)
Timer TA0 (16)
RAM
(Note)
P6(8)
Input/Output P6
P5(6)
Input/Output P5
P7(8)
Input/Output P7
P4(8)
Input/Output P4
D-A
0
Converter (8)
P8(4)
Input/Output P8
MD0
(0V)
V
SS
P4OUT
CUT
ROM
(Note)
V
CONT
Timer TA6 (16)
Timer TA7 (16)
Timer TA8 (16)
Timer TA9 (16)
Timer TA5 (16)
P6OUT
CUT
P2(8)
Input/Output P2
P1(8)
Input/Output P1
UART2 (9)
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
ROM
32 Kbytes
48 Kbytes
60 Kbytes
RAM
1 Kbyte
3 Kbytes
3 Kbytes
Note:
Data Buffer DQ0 (8)
Data Buffer DQ
1
(8)
Data Buffer DQ
2
(8)
Data Buffer DQ
3
(8)
Instruction Queue Buffer Q
0
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
3
(8)
Instruction Queue Buffer Q
4
(8)
Instruction Queue Buffer Q
5
(8)
Instruction Queue Buffer Q
6
(8)
Instruction Queue Buffer Q
7
(8)
Instruction Queue Buffer Q
8
(8)
Instruction Queue Buffer Q
9
(8)
Program Address Register PA (24)
Data Address Register DA (24)
Incrementer (24)
Incrementer/Decrementer (24)
Input Buffer Register IB (16)
Program Counter PC (16)
Program Bank Register PG (8)
Processor Status Register PS (11)
Direct Page Register DPR0 (16)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Accumulator B (16)
Accumulator A (16)
Arithmetic Logic
Unit (16)
Data Bank Register DT (8)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM
3
PRELIMINARY
Notice: This is not a final specification.
e param
Som
its are subject to change.
etric lim
FUNCTIONS
Number of basic machine instructions
Instruction execution time
External clock input frequency f(X
System clock frequency f(f
Memory size
Programmable input/output
ports
Multi-functional timers
Serial I/O
A-D converter
D-A converter
Dead-time timer
Watchdog timer
Interrupts
Clock generating circuit
PLL frequency multiplier
Power supply voltage
Power dissipation
Ports’ input/output
characteristics
Memory expansion
Operating ambient temperature range
Device structure
Package
sys)
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
IN)
ROM
RAM
P1, P2, P4, P6, P7
P5
P8
TA0–TA9
TB0–TB2
UART0, UART1, and UART2
Maskable interrups
Non-maskable interrups
nput/Output withstand voltage
utput current
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
FunctionsParameter
203
50 ns (the fastest instruction at f(f
20 MHz (Max.)
20 MHz (Max.)
(Note 1)
(Note 1)
8-bit ✕ 5
6-bit ✕ 1
4-bit ✕ 1
16-bit ✕ 10
16-bit ✕ 3
(UART or Clock synchronous serial I/O) ✕ 3
10-bit successive approximation method ✕ 1 (12 channels)
8-bit ✕ 2
8-bit ✕ 3
12-bit ✕ 1
8 external sources, 20 internal sources. Each interrupt can be set
to a priority level within the range of 0–7 by software.
3 internal sources
Incorporated (externally connected to a ceramic resonator or
quartz-crystal resonator).
The following multiplication ratios are available: ✕2, ✕3, ✕4.
5 V±0.5 V
125 mW (at f(fsys) = 20 MHz, Typ, ; the PLL frequency multiplier is inactive.)
5 V
5 mA
Not available (single-chip mode only).
–20 to 85 °C
CMOS high-performance silicon gate process
(Note 2)
sys) = 20 MHz)
Notes 1:
4
ROM
RAM
2:
Packages M37905M4C-XXXFP, M37905M6C-XXXFP, M37905M8C-XXXFP 64-pin plastic molded QFP (64P6N-A)
M37905M4C-XXXSP, M37905M6C-XXXSP, M37905M8C-XXXSP
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
32 Kbytes
48 Kbytes
60 Kbytes
1024 bytes
3072 bytes
3072 bytes
64-pin shrink plastic moldeds DIP (64P4B)
PRELIMINARY
Notice: This is not a final specification.
e param
Som
its are subject to change.
etric lim
PIN DESCRIPTION
NamePin
Vcc, Vss
MD0
MD1
RESET
IN
X
XOUT
VCONT
AVcc,
AVss
REF
V
P10–P17
P20–P27
P40–P47
P51–P53,
P55–P57
P60–P67
P70–P77
P80–P83
P4OUTCUT
P6OUTCUT
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
Filter circuit connection
Analog power supply input
Reference voltage input
I/O port P1
I/O port P2
I/O port P4
I/O port P5
I/O port P6
I/O port P7
I/O port P8
CUT input
P4OUT
P6OUT
CUT input
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
Input/
Output
—
Input
Input
Input
Input
Output
—
—
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Apply 5 V±0.5 V to Vcc, and 0 V to Vss.
Connect this pin to V
Connect this pin to Vss.
The microcomputer is reset when “L” level is applies to this pin.
These are input and output pins of the internal clock generating circuit. Connect a
ceramic resonator or quartz-crystal oscillator between pins X
external clock is used, the clock source should be connected to pin X
X
OUT should be left open.
When using the PLL frequency multiplier, connect this pin to the filter circuit. When
not using the PLL frequency multiplier, this pin should be left open.
Power supply input pins for the A-D and D-A converters. Connect AVcc to Vcc, and
AVss to Vss externally.
This is the reference voltage input pin for the A-D and D-A converters.
Port P1 is an 8-bit I/O port. This port has an I/O direction register, and each pin can
be programmed for input or output. These pins enter the input mode ar reset. These
pins also function as I/O pins of UART0, 1.
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A4 and A9. Also, they can be programmed to function as input pins for timers B0 to B2.
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A5 to A8. Also, they function as output pins for motor drive waveform.
In addition to having the same functions as port P1, these pins function as input pins
for INT
1 to INT3 and INT5 to INT7. Also, pins P55 to P57 function as input pins for
timers B0 to B2 and as input pins for position data in the three-phase waveform
mode; and pins P5
mode.
In addition to having the same functions as port P1, these pins function as I/O pins
for timers A0 to A3. Also, they function as motor drive waveform output pins.
In addition to having the same functions as port P1, these pins function as input pins
for the A-D converter. Also, P7
In addition to having the same functions as port P1, these pins function as input pins
for the A-D converter. Also, these pins function as I/O pins for UART2,and pin P8
functions as an output pin for the D-A converter.
This pin has the function to forcibly place port P4 pins in the input mode. Also, this
pin functions as an input pin for INT
forcibly cuts off a motor drive waveform output.
This pin has the function to forcibly place port P6 pins in the input mode. Also, this
pin functions as an input pin for INT
forcibly cuts off a motor drive waveform output.
SS.
2 and P53 function as trigger-input pins in the pulse output port
Functions
IN and XOUT. When an
7 functions as an output pin for the D-A converter.
0; and this pin is used to input a signal, which
4; and this pin is used to input a signal, which
IN, and pin
0
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
These microcomputers contain the following devices in the single
chip: ROM, RAM, CPU, bus interface unit, and peripheral devices
such as the interrupt control circuit, timers, serial I/O,
A-D converter, D-A converter, I/O ports, clock generating circuit, etc.
MEMORY
Figures 1 (1) through (3) show the memory maps. The address
space is 64 Kbytes from addresses 016 through FFFF16. This ad-
000000
Bank 0
16
16
00FFFF
16
000000
0000FF
000100
000BFF
000C00
000FFF
001000
007FFF
008000
00FFB4
00FFFF
dress space is called “bank 016”.
The internal ROM and RAM are allocated as shown in Figures 1 (1)
through (3).
Addresses FFB416 through FFFF16 contain the RESET and the interrupt vector addresses, and the interrupt vectors are stored there.
For details, refer to the section on interrupts.
Allocated to addresses 016 through FF16 are peripheral devices such
as I/O ports, A-D converter , D-A converter, serial I/O, timers, interrupt
control registers, etc. Figures 2 and 3 show the location of SFRs.
16
Peripheral devices'
control registers
16
16
16
16
16
16
16
16
16
16
Unused area
Internal RAM
1024 bytes
Unused area
Internal ROM
32 Kbytes
000000
0000FF
00FFB4
00FFFE
16
Peripheral devices'
control registers
(See Figures 2 and 3.)
16
Interrupt vector table
16
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT
7
INT
6
INT
5
Reserved area
Address matching detect
Reserved area
Reserved area
INT
4
INT
3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
Received area
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
Fig. 1 (1) Memory map of M37905M4C-XXXFP/SP (Single-chip mode)
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
000000
16
Bank 0
16
00FFFF
16
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
000000
0000FF
000100
0003FF
000400
000FFF
001000
003FFF
004000
00FFB4
00FFFF
Peripheral devices'
16
control registers
16
16
16
16
16
16
16
16
16
16
Unused area
Internal RAM
3072 bytes
Unused area
Internal ROM
48 Kbytes
000000
0000FF
00FFB4
00FFFE
16
Peripheral devices'
control registers
(See Figures 2 and 3.)
16
Interrupt vector table
16
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT
7
INT
6
INT
5
Reserved area
Address matching detect
Reserved area
Reserved area
INT
4
INT
3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
Reserved area
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
Fig. 1 (2) Memory map of M37905M6C-XXXFP/SP (Single-chip mode)
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
000000
16
Bank 0
16
00FFFF
16
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
000000
16
0000FF
000100
0003FF
000400
000FFF
001000
00FFB4
00FFFF
Peripheral devices'
control registers
16
16
16
16
Internal RAM
16
16
Internal ROM
16
16
Unused area
3072 bytes
60 Kbytes
000000
0000FF
00FFB4
00FFFE
16
Peripheral devices'
control registers
(See Figures 2 and 3.)
16
Interrupt vector table
16
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT
7
INT
6
5
INT
Reserved area
Address matching detect
Reserved area
Reserved area
INT
4
INT
3
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
Reserved area
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
Fig. 1 (3) Memory map of M37905M8C-XXXFP/SP (Single-chip mode)
8
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Address (Hexadecimel notation) Address (Hexadecimel notation)
000000
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
000013
000014
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
000021
000022
000023
000024
000025
000026
000027
000028
000029
00002A
00002B
00002C
00002D
00002E
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Port P1 register
16
Reserved area (Note)
16
Port P1 direction register
16
16
Port P2 register
Reserved area (Note)
16
16
Port P2 direction register
Reserved area (Note)
16
Port P4 register
16
16
Port P5 register
16
Port P4 direction register
16
Port P5 direction register
16
Port P6 register
16
Port P7 register
16
Port P6 direction register
16
Port P7 direction register
16
Port P8 register
16
16
Port P8 direction register
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
16
16
16
16
16
A-D control register 0
16
A-D control register 1
16
A-D register 0
16
16
A-D register 1
16
16
A-D register 2
16
16
A-D register 3
16
16
A-D register 4
16
16
A-D register 5
16
16
A-D register 6
16
16
A-D register 7
16
16
UART0 transmit/receive mode register
16
UART0 band rate register (BRG0)
16
UART0 transmit buffer register
16
16
UART0 transmit/receive control register 0
16
UART0 transmit/receive control register 1
16
UART0 receive buffer register
16
16
UART1 transmit/receive mode register
16
UART1 baud rate register (BRG1)
16
UART1 transmit buffer register
16
16
UART1 transmit/receive control register 0
16
UART1 transmit/receive control register 1
16
UART1 receive buffer register
16
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
16
000040
000041
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Count start register 0
16
Count start register 1
16
One-shot start register 0
One-shot start register 1
16
Up-down register 0
16
Timer A clock division select register
16
16
Timer A0 register
16
16
Timer A1 register
16
16
Timer A2 register
16
16
Timer A3 register
16
16
Timer A4 register
16
16
Timer B0 register
16
16
Timer B1 register
16
16
Timer B2 register
16
Timer A0 mode register
16
Timer A1 mode register
16
Timer A2 mode register
16
Timer A3 mode register
16
16
Timer A4 mode register
16
Timer B0 mode register
16
Timer B1 mode register
16
Timer B2 mode register
Processor mode register 0
16
Processor mode register 1
16
16
Watchdog timer register
Watchdog timer frequency select register
16
16
Particular function select register 0
Particular function select register 1
16
16
Particular function select register 2
Reserved area (Note)
16
16
Debug control register 0
Debug control register 1
16
16
Address comparison register 0
16
16
16
Address comparison register 1
16
16
interrupt control register
16
3
INT
16
interrupt control register
INT
4
16
A-D conversion interrupt
16
UART0 transmit interrupt
16
UART0 receive interrupt
16
UART1 transmit interrupt
16
UART1 receive interrupt
16
Timer A0 interrupt
16
Timer A1 interrupt
16
Timer A2 interrupt
16
Timer A3 interrupt
16
Timer A4 interrupt
16
Timer B0 interrupt
16
Timer B1 interrupt
16
Timer B2 interrupt
16
0
INT
16
1
INT
16
2
INT
interrupt
interrupt
interrupt
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
control register
Fig. 2 Location of SFRs (1)
Note: Do not write to this address.
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Address (Hexadecimel notation) Address (Hexadecimel notation)
000080
000081
000082
000083
000084
000085
000086
000087
000088
000089
00008A
00008B
00008C
00008D
00008E
00008F
000090
000091
000092
000093
000094
000095
000096
000097
000098
000099
00009A
00009B
00009C
00009D
00009E
00009F
0000A0
0000A1
0000A2
0000A3
0000A4
0000A5
0000A6
0000A7
0000A8
0000A9
0000AA
0000AB
0000AC
0000AD
0000AE
0000AF
0000B0
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9
0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
16
Reserved area (Note)
16
16
Reserved area (Note)
16
16
Reserved area (Note)
16
16
Reserved area (Note)
16
16
Reserved area (Note)
16
16
16
Reserved area (Note)
16
16
External interrupt input read-out register
16
D-A control register
16
16
D-A register 0
16
D-A register 1
16
16
16
16
16
16
16
16
Pulse output control register
16
16
Pulse output data register 0
16
Pulse output data register 1
16
16
16
Waveform output mode register
16
Dead-time timer
16
Three-phase output data register 0
16
Three-phase output data register 1
Position-data-retain function control register
16
16
Serial I/O pin control register
16
16
16
Port P2 pin
16
16
UART2 transmit/receive mode register
16
UART2 band rate register (BRG2)
16
UART2 transmit buffer register
16
UART2 transmit/receive control register 0
16
UART2 transmit/receive control register 1
16
16
UART2 receive buffer register
16
Reserved area (Note)
16
16
Reserved area (Note)
16
Reserved area (Note)
16
Clock control register 0
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
16
function control register
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
0000C0
16
0000C1
16
0000C2
16
0000C3
16
0000C4
16
0000C5
0000C6
0000C7
0000C8
0000C9
0000CA
0000CB
0000CC
0000CD
0000CE
0000CF
0000D0
0000D1
0000D2
0000D3
0000D4
0000D5
0000D6
0000D7
0000D8
0000D9
0000DA
0000DB
0000DC
0000DD
0000DE
0000DF
0000E0
0000E1
0000E2
0000E3
0000E4
0000E5
0000E6
0000E7
0000E8
0000E9
0000EA
0000EB
0000EC
0000ED
0000EE
0000EF
0000F0
0000F1
0000F2
0000F3
0000F4
0000F5
0000F6
0000F7
0000F8
0000F9
0000FA
0000FB
0000FC
0000FD
0000FE
0000FF
Up-down register
16
16
Timer A5 register
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
A6
Timer
A7
Timer
A8
Timer
A9
Timer
A01 register
Timer
A11 register
Timer
A21 register
Timer
A5 mode register
Timer
Timer
A6 mode register
Timer
A7 mode register
Timer
A8 mode register
Timer
A9 mode register
A-D control register 2
Comparator function select register 0
Comparator function select register 1
Comparator result register 0
Comparator result register 1
A-D register 8
A-D register 9
A-D register 10
A-D register 11
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
Reserved area (Note)
UART2 transmit interrupt
UART2 receive interrupt
Timer A5
Timer A6
Timer A7
Timer A8
Timer A9
INT5 interrupt
INT6 interrupt
INT7 interrupt
register
register
register
register
interrupt
interrupt
interrupt
interrupt
interrupt
control register
control register
control register
1
control register
control register
control register
control register
control register
control register
control register
Note: Do not write to this address.
Fig. 3 Location of SFRs (2)
10
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has 13 registers and is shown in Figure 4. Each of these
registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. Data
length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is
“0” and as an 8-bit register when flag m is “1”. Flag m is a part of the
processor status register (PS) which is described later.
Data operations such as calculations, data transfer, input/output,
etc., are executed mainly through accumulator A.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use
of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
ACCUMULATOR E
Accumulator E is a 32-bit register and consists of accumulator A
(low-order 16 bits) and accumulator B (high-order 16 bits). It is used
for 32-bit data processing.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. Index register length flag x determines whether the
register is used as 16-bit register or as 8-bit register. It is used as a
16-bit register when flag x is “0” and as an 8-bit register when flag x
is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register X is used as the index
register, the contents of this address are added to obtain the real address.
Index register X functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when flag
x is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register Y is used as the index
register, the contents of this address are added to obtain the real address.
Index register Y functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
15 7 0
31
70
PG Program bank register PG
70
Fig. 4 Register structure
B
H
Accumulator B
Data bank register DTDT
B
L
Accumulator A
15 7 0
Accumulator E
15 7 0
15 7 0
15
15 7 0
15 0
15 0
15 0
15
00000
A
A
H
B
H
X
H
Y
H
H
IPL2IPL1IPL
7
S
PC
DPR0 to DPR3
7
0
NVmxDIZC
A
L
A
L
B
L
X
L
Y
L
0
0
Index register X
Index register Y
Stack pointer S
Program counter PC
Direct page registers DPR0 to DPR3
0
Processor status register PS
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing mode.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
DIRECT PAGE REGISTERS 0 through 3
(DPR0 through DPR3)
The direct page register is a 16-bit register. An addressing mode of
which name includes ‘direct’ generates an address of data to be accessed, regarding the contents of this register as the base address.
The 7900 Series has been expanded direct page registers up to 4
(DPR0 to DPR3), in comparison to the 7700 Series which has the
single direct page register. Accordingly, the 7900 Series’s direct addressing method which uses direct page registers differs from that of
the 7700 Series. However, the conventional direct addressing
method, using only DPR0, is still be selectable, in order to make use
of the 7700 Series software property. For more details, refer to the
section on the direct page.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of
flags to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V , and
N.
The details of each bit of the processor status register are described
below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
watchdog timer and software interrupts are disabled. This flag is set
to “1” automatically when an interrupt is accepted. It can be set and
reset directly with the SEI and CLI instructions or SEP and CLP instructions.
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when data length flag m is “0” and with
two digits when it is “1”. Decimal adjust is automatically performed.
(Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.
12
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it
is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtraction is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
M37905M8C-XXXFP, M37905M8C-XXXSP
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, data’s bit 15 is
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other
cases. It can also be set and reset with the SEP and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than
the processor interrupt priority . When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level
of the device requesting the interrupt. Refer to the section on interrupts for more details.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BANK
In order to effectively use the integrated hardware on the chip, this
CPU core uses an address generating method with a 24-bit address
split into high-order 8 bits and low-order 16 bits. In other words, the
64 Kbytes specified by the low-order 16 bits are one unit (referred to
as “bank”), and the address space is divided into 256 banks (016 to
FF16) specified by the high-order 8 bits.
In the program area on the address space, the bank is specified by
the program bank register (PG), and the address in the bank is
specified by the program counter (PC).
As for each bank boundary, when an overflow has occurred in PC,
the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the
normal conditions, therefore, programming without concern for the
bank boundaries is possible. Furthermore, as for the data area on
the address space, the bank is specified by the data bank register
(DT), and the address in the bank is specified by the operation result
by using the various addressing modes (Note).
Note: Some addressing modes directly specify a bank.
DIRECT PAGE
The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The
direct page and direct addressing modes have been provided for the
effective access to bank 016. In the 7900 Series, two types of direct
addressing modes are available: the conventional direct addressing
mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected
according to the contents of bit 1 of the processor mode register 1.
This bit 1 is cleared to “0” at reset. (In other words, the conventional
direct addressing mode is selected.) However, once this bit 1 has
been set to “1” by software, this bit cannot be cleared to “0” again,
except by reset. That is to say , when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is
running.
Refer to “7900 Series Software Manual” for details concerning the
various addressing modes which use the direct page area.
Instruction Set
The CPU core of the 7900 Series has an expanded instruction set
based on the existing 7700/7751 Series’ CPU core. In addition, its
source code (mnemonic) has the complete upper compatibility with
the 7700 Series instruction set.
For details concerning addressing modes and instruction set, refer to
“7900 Series Software Manual”.
■ Conventional direct addressing mode
The direct page area consists of 256-byte space. Its bank address is
“0016”, and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an
instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area.
■ Expanded direct addressing mode
The direct page area consists of four 64-byte spaces. Their bank
address is “0016”, and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct
page registers. In this expanded direct addressing mode, a value (1
byte) just after an instruction code is regarded as follows:
• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
• Low-order 6 bits: regarded as an offset value for the selected direct
page register.
Then, the CPU accesses each address in each direct page area:
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BUS INTERFACE UNIT
Data transfer between the central processing unit (CPU) and internal memory, internal peripheral devices is always performed via the
bus interface unit (BIU), which is located between the CPU and the
internal buses.
Figure 5 shows the BIU and the bus structure. The CPU and BIU are
connected by a dedicated bus, and any transfer between the CPU
and BIU is controlled by this dedicated bus.
On the other hand, data transfer between the BIU and internal pe-
M37905
CPU bus
Central
Processing
Unit
(CPU)
Bus
Interface
Unit
(BIU)
ripheral devices uses the following internal common buses: 32-bit
code bus, 16-bit data bus, 24-bit address bus, and control signals.
The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/
data bus method) is employed in order to improve data transfer capabilities. As a result, the internal memory is connected to both the
code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus.
Internal buses
Internal code bus (CB0 to CB31)
Internal data bus (DB0 to DB15)
Internal address bus (AD0 to AD23)
Internal control signal
Internal
memory
SFR : Special Function Register
❈ The CPU bus and internal bus separate out independently.
Fig. 5 BIU and bus structure
Internal
peripheral
devices
(SFR)
15
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
BIU structure
The BIU consists of four registers shown in Figure 6. Table 1 lists the
functions of each register.
Table 1. Functions of each register
Name
Program address register
Instruction queue buffer
Data address register
Data buffer
Indicates a storage address for an instruction to be next taken into an instruction queue buffer.
Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes.
Indicates an address where data will be next read from or written to.
Temporarily stores data which has been read from internal memory or internal peripheral devices by the
BIU; or temporarily stores data which is to be written to internal memory or internal peripheral devices
by the CPU. Consists of 32 bits.
M37905M8C-XXXFP, M37905M8C-XXXSP
MITSUBISHI MICROCOMPUTERS
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Functions
Fig. 6 Register structure of BIU
b23
PA
b23 b0
DA
b31 b0
DQ
b0
b7 b0
Q0
Q9
Program address register
Instruction queue buffer
Data address register
Data buffer
16
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
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M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory or internal peripheral devices, at first, the CPU informs the
BIU’s data address register of the address where the data has been
located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
AD2 (A2)
Even address
4-byte boundary
8-byte boundary
X: 0 or 1
Figures 7 and 8 show the bus cycle waveform examples for instruction prefetch and data access.
X
X
0
AD
1 (A1)
X
0
0
AD
0 (A0)
0
0
0
Access to internal area
When branched or at instruction
prefetch
φ
BIU
Internal address bus
Internal code bus
0
to CB
CB
Address
31
Code
(3) Data write operation
When executing an instruction for writing data into the internal
memory or internal peripheral devices, at first, the CPU informs the
BIU’s data address register of the address where the data has been
located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory or internal peripheral devices.
This operation is called “bus cycle”. The bus cycle is affected by the
lengh of data to be transferred (byte, word, or double-word) at data
access.
Fig. 7 Bus cycle waveform example for instruction prefetch
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Access starting from even address Access starting from odd address
8-bit
data
read
8-bit
data
written
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
MITSUBISHI MICROCOMPUTERS
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M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
φ
BIU
Address
D0 to D7
Invalid
φ
BIU
Address
D0 to D7
Internal address bus
Internal address bus
φ
BIU
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Internal data bus
DB0 to DB7
DB8 to DB15
Address
Address
Invalid
D8 to D
D8 to D
15
15
16-bit
data
read
Access to internal area
16-bit
data
written
32-bit
data
read
32-bit
data
written
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
A0 to A23
D0 to D7
D8 to D15
φ
BIU
Internal address
bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Internal address
bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Address
D0 to D7
D8 to D
15
φ
1
Address
D0 to D7
D8 to D
15
D8 to D
D8 to D
15
15
Address + 2
Address + 2
D0 to D7D0 to D7
D8 to D
D0 to D7D0 to D7
D8 to D
15
15
Address
Address
Internal address bus
Internal address
Internal data bus
DB8 to DB15
Internal address
Internal data bus
DB8 to DB15
Internal data bus
DB0 to DB7
DB8 to DB15
A0 to A23
D8 to D15
φ
BIU
bus
DB0 to DB7
φ
BIU
bus
DB0 to DB7
φ
BIU
φ
1
D0 to D7
Address Address + 1
D8 to D
Address Address + 1
D8 to D
Address
Address
Invalid
D8 to D
D8 to D
15
15
Invalid
15
15
Address + 1
Address + 1
D0 to D7
D8 to D
D0 to D7
D8 to D
D0 to D7
Invalid
D0 to D7
15
15
Address + 3
D0 to D7
Invalid
Address + 3
D0 to D7
Fig. 8 Bus cycle waveform example for data access (access to internal area)
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
● Number of bus cycles
Figure 9 shows the bus cycle waveform at access to the internal
area. Bit 7 of the processor mode register 1 (address 5F16), which is
shown in Figure 10, selects the number of bus cycles for the internal
1 bus cycle = 3φ (Note)
(Internal ROM bus cycle select bit = 0)
1 bus cycle = 3φ
BIU
φ
ROM
RAM
SFR
Internal address bus
Internal data bus,
Internal code bus
Address
Internal address bus
Internal data bus,
Internal code bus
Data
φ
BIU
ROM: 3φ or 2φ. (This bit 7 is the internal ROM bus cycle select bit.)
The internal RAM, SFRs (internal peripheral devices’ control registers) are always accessed with 1 bus cycle = 2φ.
1 bus cycle = 2φ
(Internal ROM bus cycle select bit = 1)
1 bus cycle = 2φ
φ
BIU
Internal address bus
Internal data bus
Internal code bus
1 bus cycle = 2φ
Address
Data
Address
Data
Note: When reprogramming the internal flash memory in the CPU reprogramming mode, select the bus cycle = 3φ.
Fig. 9 Bus cycle waveform at access to internal area
76543210
0000000
Fig. 10 Bit configuration of processor mode register 1
Processor mode register 1
Fix these bits to “0000000
Internal ROM bus cycle select bit
0 : 1 bus cycle = 3φ
1 : 1 bus cycle = 2φ
2
”.
Address
16
5F
19
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PROCESSOR MODES
This microcomputer is dedicated to the single-chip mode. Therefore,
be sure to connect pin MD0 to Vss, and be sure to fix the processor
mode bits (bits 1 and 0 of the processor mode register 0, address
5E16), which is shown in Figure 11, to “002”.
M37905M8C-XXXFP, M37905M8C-XXXSP
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
76543210
0
Fig. 11 Bit configuration of processor mode register 0
00
00
Processor mode register 0
Processor mode bits
0 0 : Single-chip mode
0 1 : Do not select.
1 0 : Do not select.
1 1 : Do not select.
Fix these bits to “00
Interrupt priority detection time select bits
0 0 : 7 cycles of f
0 1 : 4 cycles of f
1 0 : 2 cycles of f
1 1 : Do not select.
Software reset bit
By a write of “1” to this bit, the microcomputer will be reset, and then, restarted.
Fix this bit to “0”.
sys
sys
sys
2
”.
Address
16
5E
20
PRELIMINARY
76543210
INT0 read bit
INT
1
read bit
INT
2
read bit
INT
3
read bit
INT
4
read bit
INT
5
read bit
INT
6
read bit
INT
7
read bit
External interrupt input read register
Address
95
16
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 3 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as an interrupt source in
this section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, and address
matching detection all have interrupt control registers. Table 4 shows
the addresses of the interrupt control registers and Figure 13 shows
the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits except for that of a watchdog timer interrupt can be cleared by
software.
An INTi (i = 0 to 7) interrupt request is generated by an external input.
INTi is an external interrupt; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be selected
with the level/edge select bit. Furthermore, the polarity of the interrupt input can be selected with the polarity select bit.
When using the following pins as external interrupt input pins, be
sure to clear the direction registers of the corresponding multiplexed
ports to “0”: pins P51/INT1, P52/INT2, P53/INT3, P55/INT5, P56/INT6,
and P57/INT7.
When the external interrupt input read register (address 9516), which
is shown in Figure 12, is read out, the status of pins INT0 through
INT7 can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be adjusted by software as shown in Figure 14.
The hardware priority is fixed as the following:
reset > watchdog timer > other interrupts
Table 3. Interrupt sources and interrupt vector addresses
Interrupts
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT7 external interrupt
INT6 external interrupt
INT5 external interrupt
Address matching detection interrupt
INT4 external interrupt
INT3 external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2 external interrupt
INT1 external interrupt
INT0 external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Vector addresses
00FFB416 00FFB516
00FFB616 00FFB716
00FFB816 00FFB916
00FFBA16 00FFBB16
00FFBC16 00FFBD16
00FFBE16 00FFBF16
00FFC016 00FFC116
00FFC216 00FFC316
00FFC416 00FFC516
00FFC616 00FFC716
00FFCA16 00FFCB16
00FFD016 00FFD116
00FFD216 00FFD316
00FFD416 00FFD516
00FFD616 00FFD716
00FFD816 00FFD916
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
00FFE016 00FFE116
00FFE216 00FFE316
00FFE416 00FFE516
00FFE616 00FFE716
00FFE816 00FFE916
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
00FFF016 00FFF116
00FFF216 00FFF316
00FFF616 00FFF716
00FFF816 00FFF916
00FFFA16 00FFFB16
00FFFC16 00FFFD16
00FFFE16 00FFFF16
Fig. 12 Bit configuration of external interrupt input read register
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
76543210
Interrupt control register bit configuration for A-D converter, UART0, UART1, UART2,
timer A0 to timer A9, and timer B0 to timer B2.
76543210
MITSUBISHI MICROCOMPUTERS
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16-BIT CMOS MICROCOMPUTER
Interrupt priority level select bits (Note 1)
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Interrupt priority level select bits (Note 1)
Interrupt request bit (Note 2)
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;
this bit is set to “1” at falling edge when edge sense is selected.
1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;
this bit is set to “1” at rising edge when edge sense is selected.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Interrupt control register bit configuration for INT
Notes 1: Use the MOVM (MOVMB) instruction or the STA (STAB, STAD) instruction for writing to this bit.
2: Interrupt request bits of INT
Fig. 13 Bit configuration of interrupt control register
0
– INT
7
0
to INT7 are invalid when the level sense is selected.
22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
Table 4. Addresses of interrupt control registers
Interrupt control registers
INT3 interrupt control register
INT4 interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 receive control register
Timer A8 interrupt control register
Timer A9 interrupt control register
INT5 interrupt control register
INT6 interrupt control register
INT7 interrupt control register
Addresses
00006E16
00006F16
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
0000F116
0000F216
0000F516
0000F616
0000F716
0000F816
0000F916
0000FD16
0000FE16
0000FF16
Interrupts caused by the address matching detection and when dividing by zero are software interrupts and are not included in Figure
14.
Other interrupts previously mentioned are A-D converter, UART , etc.
interrupts. The priority of these interrupts can be changed by changing the priority level in the corresponding interrupt control register by
software.
Figure 15 shows a diagram of the interrupt priority detection circuit.
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset and
watchdog timer interrupts are not affected by the interrupt disable
flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
A-D converter, UART, etc. interrupts
Priority can be changed by software inside ➂.
Fig. 14 Interrupt priority
Interrupt request
Reset
Watchdog timer
Interrupt disable flag I
IPL
Fig. 15 Interrupt priority detection
Priority is determined by hardware
➂➁➀
Watchdog
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT7
INT6
INT5
INT4
INT
3
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT2
INT1
INT0
timer
Reset
Level 0
23
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to “0” and enable further interrupts.
For reset, watchdog timer, zero divide, and address match detection
interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 5.
The interrupt request bit and the interrupt priority level of each interrupt source are sampled and latched at each operation code fetch
cycle while fsys is “H”. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
As shown in Figure 16, there are three different interrupt priority detection time from which one is selected by software. After the selected time has elapsed, the highest priority is determined and is
processed after the currently executing instruction has been completed.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E16) shown in Figure 11. Table 6 shows the relationship
between these bits and the number of cycles. After a reset, the processor mode register 0 is initialized to “0016.” Therefore, the longest
time is automatically set, however, the shortest time must be selected by software.
Table 5.
Value loaded in processor interrupt level (IPL) during an interrupt
Interrupt types
Reset
Watchdog timer
Zero divide
Address matching detection
Setting value
0
7
Not change value of IPL.
Not change value of IPL.
Table 6. Relationship between interrupt priority detection time select
bit and number of cycles
Priority detection time select bit
Bit 5
0
0
1
Bit 4
0
1
0
Number of cycles (Note)
7 cycles of fsys
4 cycles of fsys
2 cycles of fsys
Note: For system clock fsys, refer to the section on the clock gener-
ating circuit.
f
sys
Operation code fetch cycle
Sampling pulse
Priority detection time
Select one between 00 to
10 with bits 4 and 5 of
processor mode register 0
Fig. 16 Interrupt priority detection time
(Note)
b5 b4
0 0
0 1
1 0
sys
Note: This pulse resides when 2 cycles of f
is selected.
24
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
76543210
Fig. 17 Bit configuration of port P2 pin function control register
Port P2 pin function control register
Pin TB0
0: Allocate pin TB0
1: Allocate pin TB0
Pin TB1IN select bit
0: Allocate pin TB1
1: Allocate pin TB1
Pin TB2
0: Allocate pin TB2
1: Allocate pin TB2
IN
select bit
IN
select bit
IN
to P55.
IN
to P24.
IN
to P56.
IN
to P25.
IN
to P57.
IN
to P26.
Address
16
AE
25
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
TIMER
There are eight 16-bit timers. They are divided by type into timer A
(10) and timer B (3).
The timer I/O pins are multiplexed with I/O pins for ports P2, P4, P5
and P6. To use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to “0” to specify
input mode.
TIMER A
Figure 18 shows a block diagram of timer A.
Timer A has four modes: timer mode, event counter mode, one-shot
pulse mode, and pulse width modulation mode. The mode is selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 9). Each
of these modes is described below.
Figure 19 shows the bit configuration of the timer A clock division select register. Timers A0 to A9 use the count source which has been
selected by bits 0 and 1 of this register.
Timer A clock
division select bit
f
2
f
1
f
16
Count source
select bits
(1) Timer mode [00]
Figure 20 shows the bit configuration of the timer Ai mode register in
the timer mode. Bits 0, 1 and 5 of the timer Ai mode register must be
“0” in timer mode. The timer A’s count source is selected by bits 6
and 7 of the timer Ai mode register and the contents of the timer A
clock division select register. (See Table 7.)
The counting of the selected clock starts when the count start bit is
“1” and stops when it is “0”.
Figure 21 shows the bit configuration of the count start bit. The
counter is decremented, an interrupt is caused and the interrupt request bit in the timer Ai interrupt control register is set when the contents becomes 000016. At the same time, the contents of the reload
register is transferred to the counter and count is continued.
f
64
f
512
f
4096
Polarity
selection
IN
TAi
(i = 0–9)
Pulse output
TAi
OUT
(i = 0–9)
Fig. 18 Block diagram of timer A
• Timer
• One-shot pulse
• Pulse width
Timer (gate function)
Event counter
External trigger
Count start registers 0, 1
(Addresses 4016, 4116)
Countdown
Up-down registers 0, 1
(Addresses 4416, C416)
Toggle flip-flop
Data bus (odd)
Data bus (even)
(Low-order 8 bits) (High-order 8 bits)
Reload register(16)
Counter (16)
Countup/Countdown switching
“Countdown” is always
selected when not in the
event counter mode.
Timer A0 4716 46
Timer A1 4916 48
Timer A2 4B16 4A
Timer A3 4D16 4C
Timer A4 4F16 4E
Addresses
16
16
16
16
16
Timer A5 C716 C6
Addresses
Timer A6 C916 C8
Timer A7 CB16 CA
Timer A8 CD16 CC
Timer A9 CF16 CE
16
16
16
16
16
26
M37905M4C-XXXFP, M37905M4C-XXXSP
Clock source select bits
(bits 7 and 6 at addresses
56
16
to 5A16)
(bits 7 and 6 at addresses
D6
16
to DA16)
1 0
0 0
0 1
Timer A clock division select bits
(bits 1 and 0 at address 45
16
)
f
2
f
16
f
64
1 1 f
512
00
f
1
f
16
f
64
f
4096
01
f
1
f
64
f
512
f
4096
10
11
Do not
select.
Note: Timers A0 to A9 use the same clock, which is selected by the
timer A clock division select bits.
M37905M6C-XXXFP, M37905M6C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
When bit 2 of the timer Ai mode register is “1”, the output is generated from TAiOUT pin. The output is toggled each time the contents
of the counter reaches to 000016. When the contents of the count
start bit is “0”, “L” is output from TAiOUT pin.
When bit 2 is “0”, TAiOUT can be used as a normal port pin. When bit
4 is “0”, TAiIN can be used as a normal port pin.
When bit 4 is “1”, counting is performed only while the input signal
from the T AiIN pin is “H” or “L” as shown in Figure 22. Therefore, this
can be used to measure the pulse width of the TAiIN input signal.
Whether to count while the input signal is “H” or while it is “L” is determined by bit 3. If bit 3 is “1”, counting is performed while the TAiIN
pin input signal is “H” and if bit 3 is “0”, counting is performed while it
is “L”.
Note that, the duration of “H” or “L” on the TAiIN pin must be 2 or
more cycles of the timer count source.
When data is written to timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The new data is reloaded
from the reload register to the counter at the next reload time and
counting continues. The contents of the counter can be read at any
time.
When the value set in the timer Ai register is n, the timer frequency
division ratio is 1/(n+1).
M37905M8C-XXXFP, M37905M8C-XXXSP
MITSUBISHI MICROCOMPUTERS
16-BIT CMOS MICROCOMPUTER
76543210
Timer A clock division select register
Timer A clock division select bit
(See Table 7.)
Fig. 19 Bit configuration of timer A clock division select register
Table 7. Relationship between timer A clock division select bits,
clock source select bits, and count source
Address
45
16
Timer A0 mode register
Timer A1 mode register
6543210
7
0
00
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
0 0 : Always “00” in timer mode
0 : No pulse output (TAi
1 : Pulse output (TAi
×
: No gate function (TAiIN is normal port pin.)
0
1 0 : Count only while TAi
1 1 : Count only while TAi
0 : Always “0” in timer mode.
Clock source select bits
See Table 7.
Fig. 20 Bit configuration of timer Ai mode register in timer mode
Addresses
56
16
5716
5816
5916
5A16
OUT is normal port pin.)
OUT is pulse output pin.)
IN input is “L”.
IN input is “H”.
Timer A5 mode register
Timer A6 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
Addresses
16
D6
D716
D816
D916
DA16
27
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
76543210
Count start register 0
(Stopped at “0”, Started at “1”)
Timer A0 count start bit
Timer A1 count start bit
Timer A2 count start bit
Timer A3 count start bit
Timer A4 count start bit
Timer B0 count start bit
Timer B1 count start bit
Timer B2 count start bit
Fig. 21 Bit configuration of count start register
Selected clock source fi
TAi
IN
Address
16
40
76543210
Count start register 1
(Stopped at “0”, Started at “1”)
Timer A5 count start bit
Timer A6 count start bit
Timer A7 count start bit
Timer A8 count start bit
Timer A9 count start bit
Address
16
41
Timer mode register
Bit 4 Bit 3
10
Timer mode register
Bit 4 Bit 3
11
Fig. 22 Count waveform when gate function is available
28
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 23 shows the bit configuration of the timer Ai mode register in
the event counter mode. In event counter mode, bit 0 of the timer Ai
mode register must be “1” and bits 1 and 5 must be “0”.
The input signal from the TAiIN pin is counted when the count start
bit shown in Figure 21 is “1” and counting is stopped when it is “0”.
Count is performed at the fall of the input signal when bit 3 is “0” and
at the rise of the signal when it is “1”.
In event counter mode, whether to increment or decrement the count
can be selected with the up-down bit or the input signal from the
TAiOUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down bit is
used to determine whether to increment or decrement the count
(decrement when the bit is “0” and increment when it is “1”). Figure
24 shows the bit configuration of the up-down register.
When bit 4 of the timer Ai mode register is “1”, the input signal from
the TAiOUT pin is used to determine whether to increment or decrement the count. However, note that bit 2 must be “0” if bit 4 is “1”. It is
because if bit 2 is “1”, TAiOUT pin becomes an output pin to output
pulses.
The count is decremented when the input signal from the T AiOUT pin
is “L” and incremented when it is “H”. Determine the level of the input
signal from the TAiOUT pin before a valid edge is input to the TAiIN
pin.
An interrupt request signal is generated and the interrupt request bit
in the timer Ai interrupt control register is set when the counter
reaches 000016 (decrement count) or FFFF16 (increment count). At
the same time, the contents of the reload register is transferred to the
counter and the count is continued.
When bit 2 is “1”, each time the counter reaches 000016 (decrement
count) or FFFF16 (increment count), the waveform’s polarity is reversed and is output from TAiOUT pin.
If bit 2 is “0”, TAiOUT pin can be used as a normal port pin.
However, if bit 4 is “1” and the TAiOUT pin is used as an output pin,
the output from the pin changes the count direction. Therefore, bit 4
must be “0” unless the output from the T AiOUT pin is to be used to select the count direction.
Data write and data read are performed in the same way as for timer
mode. That is, when data is written to timer Ai halted, it is also written to the reload register and the counter. When data is written to
timer Ai which is busy, the data is written to the reload register, but
not to the counter. The counter is reloaded with new data from the
reload register at the next reload time. The counter can be read at
any time.
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90° to timer A2, A3, A4, A7, A8 or A9. There
are two types of two-phase pulse processing operations. One uses
timers A2, A3, A7, and A8 and the other uses timers A4 and A9. In
both processing operations, two pulses described above are input to
the TAjOUT (j = 2 to 4, 7 to 9) pin and TAjIN pin respectively.
When timers A2, A3, A7, and A8 are used, as shown in Figure 25, the
count is incremented when a rising edge is input to the TAkIN (k=2,
3, 7, 8) pin after the level of T AkOUT pin changes from “L” to “H”, and
when the falling edge is input, the count is decremented.
For timers A4 and A9, as shown in Figure 26, when a phase-related
pulse with a rising edge input to the TAlIN (l = 4, 9) pin is input after
the level of TAlOUT pin changes from “L” to “H”, the count is
incremented at the respective rising edge and falling edge of the
TAlOUT pin and TAlIN pin.
Timer A0 mode register
Timer A1 mode register
76543210
××
0
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
10
0 1 : Always “01” in event counter mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input signal
1 : Count at the rising edge of input signal
0 : Increment or decrement according to up/down bit
1 : Increment or decrement according to TAi
0 : Always “0” in event counter mode
× × : Not used in event counter mode
Fig. 23 Bit configuration of timer Ai mode register in event counter mode
Addresses
16
56
5716
5816
5916
5A16
Timer A5 mode register
Timer A6 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
OUT pin input signal level
Addresses
16
D6
D716
D816
D916
DA16
29
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
76543210
Up-down register 0
Timer A0 up-down bit
Timer A1 up-down bit
Timer A2 up-down bit
Timer A3 up-down bit
Timer A4 up-down bit
Timer A2 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A3 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A4 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Address
16
44
Fig. 24 Bit configuration of up-down register
When a phase-related pulse with a falling edge input to the TAkOUT
pin is input after the level of TAlIN pin changes from “H” to “L”, the
count is decremented at the respective rising edge and falling edge
of the TAlIN pin and TAlOUT pin. When performing this two-phase
pulse signal processing, bits 0 and 4 of timer Aj mode register must
be set to “1” and bits 1, 2, 3, and 5 must be “0”. Bits 6 and 7 are ignored. (See Figure 27.) Note that bits 5, 6, and 7 of the up-down register 0 (address 4416) are the two-phase pulse signal processing
select bits for timers A2, A3, and A4, respectively . Also, bits 5, 6, and
7 of the up-down register 1 (address C416) are the two-phase pulse
signal processing select bits for timers A7, A8, and A9, respectively.
Each timer operates in normal event counter mode when the corresponding bit is “0” and performs two-phase pulse signal processing
when it is “1”.
Count is started by setting the count start bit to “1”. Data write and
read are performed in the same way as for normal event counter
mode. Note that the direction register of the input port must be set to
input mode because two kinds of pulse signals, described above,
are input. Also, there can be no pulse output in this mode.
76543210
TAk
OUT
TAk
IN
(k = 2, 3, 7, 8)
Incrementcount
Up-down register 1
Timer A5 up-down bit
Timer A6 up-down bit
Timer A7 up-down bit
Timer A8 up-down bit
Timer A9 up-down bit
Timer A7 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A8 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Timer A9 two-phase pulse signal
processing select bit
0 : Two-phase pulse signal processing
disabled
1 : Two-phase pulse signal processing
mode
Incre-
Incre-
ment-
ment-
count
count
Decrementcount
Address
16
C4
Decrementcount
Decrementcount
Fig. 25 Two-phase pulse processing operation of timer A2, A3, A7,
A8
TAl
OUT
TAl
IN
(l = 4, 9)
Increment-count at each edge
Decrement-count at each edge
Decrement-count at each edgeIncrement-count at each edge
Fig. 26 Two-phase pulse processing operation of timers A4 and A9
30
Addresses
58
76543210
××
0100
10
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
0 1 : Always “01” in event counter mode
0 1 0 0 : Always “0100” when processing
two-phase pulse signal
× × : Not used in event counter mode
5A
C8
C9
CA
16
59
16
16
16
16
16
Fig. 27 Bit configuration of timer Aj mode register when performing
two-phase pulse signal processing in event counter mode
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