Mitsubishi M37902FCCHP, M37902FJCHP, M37902FGCHP Datasheet
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
These are single-chip microcomputers designed with high-performance CMOS silicon gate technology, including the internal flash
memory. These microcomputers support the 7900 Series instruction
set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 Series instruction set.
The CPU of these microcomputers is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. Also, the
bus interface unit of these microcomputers enhances the memory
access efficiency to execute instructions fast. Therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require high-speed processing of large data.
For the internal flash memory, single-power-supply programming
and erasure, using a PROM programmer or the control by the central processing unit (CPU), is supported. Also, each of these microcomputers has the memory area dedicated for storing a certain
software which controls programming and erasure (reprogramming
control software). Therefore, on these microcomputers, the program
can easily be changed even after they are mounted on the board.
DISTINCTIVE FEATURES
<Microcomputer mode>
Number of basic machine instructions .................................... 203
•
Memory
•
[M37902FCCHP]
Flash memory (User ROM area) ................................. 120 Kbytes
RAM .............................................................................4096 bytes
[M37902FGCHP]
Flash memory (User ROM area) ................................. 248 Kbytes
RAM .............................................................................6144 bytes
[M37902FJCHP]
Flash memory (User ROM area) ................................. 498 Kbytes
RAM ...........................................................................12288 bytes
[All of the above computers]
Flash memory (Boot ROM area) ................................... 16 Kbytes
Instruction execution time
•
The fastest instruction at 26 MHz frequency ........................ 38 ns
Single power supply .................................................... 5 V ± 0.5 V
•
Interrupts ........... 6 external sources, 16 internal sources, 7 levels
•
Multi-functional 16-bit timer ................................................... 5 + 3
•
Serial I/O (UART or Clock synchronous)..................................... 2
•
10-bit A-D converter ............................................ 8-channel inputs
•
8-bit D-A converter ............................................ 3-channel outputs
•
Real-time output
•
....4 bits × 2 channels, or 6 bits × 1 channel + 2 bits × 1 channel
12-bit watchdog timer
•
Programmable input/output (ports P0–P8, P10, P11) ............... 84
•
Programming/Erase control by software command
•
Maximum number of reprograms ............................................ 100
•
APPLICATION
Control devices for personal computer peripheral equipment such as
CD-ROM drives, DVD-ROM drives, hard disk drives, high density
FDD, printers
<Flash memory mode>
Power supply voltage .................................................. 5 V ± 0.5 V
•
Programming/Erase voltage........................................ 5 V ± 0.5 V
•
Programming method............ Programming in a unit of 256 bytes
•
Erase method ............................................
•
(Data protection per block is enabled.)
Block erase or Total erase
M37902FCCHP, M37902FGCHP, M37902FJCHP
M37902FxCHP PIN CONFIGURATION (TOP VIEW)
5
6
4
7
8
10
9
11
13
12
14
15
16
/A
/A
/A
5
6
7
/A
0
↔ P11
↔ P11
↔ P0
↔ P11
101112131415161718192021222324
↔
↔
↔
↔
0
2
1
3
/KI
/KI
/KI
/KI
0
2
1
3
/RTP1
/RTP1
/RTP1
/RTP1
IN
IN
OUT
OUT
/TA2
/TA3
5
7
/TA2
/TA3
4
6
P5
P5
P5
P5
P10
3/A3
2/A2
P10
1/A1
P10
P100/A0 ↔
7/TXD1
P8
6/RXD1
P8
5
/CTS1/CLK1 ↔
P8
4
/CTS1/RTS1/INT4 ↔
P8
P8
P8
3/TXD0
2/RXD0
P81/CTS0/CLK0 ↔
CC
V
CC
AV
REF
V
AV
V
NMI →
P80/CTS0/RTS0/DA2/INT3 ↔
P7
7
/AN7/AD
TRG
/DA1/(INT2) ↔
6
/AN6/DA0 ↔
P7
5
/AN5/(INT4) ↔
P7
4
/AN4/(INT3) ↔
P7
3
/AN3 ↔
P7
2
/AN2 ↔
P7
1
/AN1 ↔
P7
/A
/A
/A
/A
/A
/A
/A
/A
4
↔ P10
5
↔ P10
6
↔ P10
7
↔ P10
0
↔ P11
1
↔ P11
2
↔ P11
3
↔ P11
/A
4
↔ P11
75747372717069686766656463626160595857565554535251
↔
76
↔
77
↔
78
79
↔
80
↔
81
82
83
↔
84
↔
85
86
87
88
→
89
90
SS
SS
91
M37902FCCHP
M37902FGCHP
M37902FJCHP
92
93
94
95
96
97
98
99
100
123456789
↔
0
/AN
0
P7
↔
IN
/TB2
7
P6
↔
IN
/TB1
6
P6
↔
IN
/TB0
5
P6
↔
2
/INT
4
P6
↔
1
/INT
3
P6
↔
0
/INT
2
P6
↔
IN
/TA4
1
P6
↔
OUT
/TA4
0
P6
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0
1
2
/LA
/LA
/LA
0
1
MD1
←
/HOLD ↔
3
P4
/D
0
↔ P1
/HLDA ↔
2
P4
/D
1
↔ P1
↔
1
/φ
1
P4
2
/D
2
↔ P1
50
↔ P13/D3/LA
49
↔ P14/D4/LA
48
↔ P15/D5/LA
47
↔ P16/D6/LA
46
↔ P17/D7/LA
45
↔ P20/D
44
↔ P21/D
43
↔ P22/D
42
↔ P23/D
41
↔ P24/D
40
↔ P25/D
39
↔ P26/D
38
↔ P27/D
37
V
36
→ X
35
← X
34
33
←
32
← RESET
V
31
←
30
↔ P30/RDY
29
↔ P3
28
↔ P3
27
↔ P3
26
25
/ALE ↔
0
P4
OUT
IN
V
MD0
BYTE
CC
SS
CONT
1
/RD
2
/BLW
3
/BHW
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
/A
/A
1
2
↔ P0
↔ P0
↔
↔
2
3
/RTP0
/RTP0
IN
OUT
/TA1
3
/TA1
2
P5
P5
19
20
/A
/A
3
4
↔ P0
↔ P0
↔
↔
0
1
/RTP0
/RTP0
IN
OUT
/TA0
1
/TA0
0
P5
P5
21
/A
5
↔ P0
↔
3
/CS
7
P4
22
/A
6
↔ P0
↔
2
/CS
6
P4
23
/A
7
↔ P0
↔
1
/CS
5
P4
SS
V
↔
0
/CS
4
P4
Outline 100P6Q-A
2
Data bank Register DT (8)
Program Counter PC (16)
Incrementer/Decrementer (24)
Program Bank Register PG (8)
Input Buffer Register IB (16)
Direct Page Register DPR0 (16)
Stack Pointer S (16)
Index Register Y (16)
Index Register X (16)
Arithmetic Logic
Unit (16)
Accumulator B (16)
Accumulator A (16)
Instruction register (8)
Central Processing Unit (CPU)
Incrementer (24)
Program Address Register PA (24)
Data Address Register DA (24)
Bus
Interface
Unit
(BIU)
RESET
MD1
Reference
voltage input
V
REF
(0V)
AV
SS
AVcc
Vcc
External data bus width
select input
BYTE
Clock Generating Circuit
Clock input
X
IN
V
CONT
X
OUT
Data Buffer DQ0 (8)
Instruction Queue Buffer Q0 (8)
Data Bus (Odd)
Address Bus
A-D converter (10)
UART1 (9)
UART0 (9)
Watchdog timer
Timer TB1 (16)
Timer TB2 (16)
Timer TB0 (16)
D-A
1
converter (8)
D-A
2
converter (8)
Timer TA1 (16)
Timer TA2 (16)
Timer TA3 (16)
Timer TA4 (16)
Timer TA0 (16)
RAM
(Note)
P8(8)
Input/Output
port P8
P7(8)
Input/Output
port P7
Input/Output
port P4
P4(8)
P10(8)
Input/Output
port P10
P6(8)
Input/Output
port P6
P5(8)
Input/Output
port P5
P11(8)
Input/Output
port P11
P1(8)
Input/Output
port P1
P2(8)
Input/Output
port P2
P3(4)
Input/Output
port P3
P0(8)
Input/Output
port P0
MD0
(0V)
Vss
Processor Status Register PS (11)
NMI
Flash memory
(Note)
D-A
0
converter (8)
Data Bus (Even)
Data Buffer DQ
1
(8)
Data Buffer DQ
2
(8)
Data Buffer DQ
3
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
3
(8)
Instruction Queue Buffer Q
4
(8)
Instruction Queue Buffer Q
5
(8)
Instruction Queue Buffer Q
6
(8)
Instruction Queue Buffer Q
7
(8)
Instruction Queue Buffer Q
8
(8)
Instruction Queue Buffer Q
9
(8)
Direct Page Register DPR1 (16)
Direct Page Register DPR2 (16)
Direct Page Register DPR3 (16)
Clock output
Reset input
Note:
Flash memory RAM
M37902FCCHP 120 Kbytes 4096 bytes
M37902FGCHP 248 Kbytes 6144 bytes
M37902FJCHP 498 Kbytes 12288 bytes
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM
3
M37902FCCHP, M37902FGCHP, M37902FJCHP
FUNCTIONS (Microcomputer mode)
Number of basic machine instructions
Instruction execution time
External clock input frequency f(XIN)
System clock frequency f(fsys)
Memory size
Programmable input/output
ports
Multi-functional timers
Serial I/O
A-D converter
D-A converter
Watchdog timer
Chip-select wait control
Flash memory (User ROM area)
RAM
Flash memory (Boot ROM area)
P0–P2, P4–P8, P10, P11
P3
TA0–TA4
TB0–TB2
UART0 and UART1
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FunctionsParameter
203
38 ns (the fastest instruction at f(fsys) = 26 MHz)
26 MHz (Max.)
26 MHz (Max.)
(Note)
(Note)
16 Kbytes
8-bit ✕ 10
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or Clock synchronous serial I/O) ✕ 2
10-bit successive approximation method ✕ 1 (8 channels)
8-bit ✕ 3
12-bit ✕ 1
Chip select area ✕ 4 (CS0–CS3). A bus cycle type and bus width
can be set for each chip select area.
Real-time output
Interrupts
Clock generating circuit
PLL frequency multiplier
Power supply voltage
Power dissipation
Ports’ input/output
characteristics
Memory expansion
Operating ambient temperature range
Device structure
Package
Note:
Flash memory M37902FCCHP 120 Kbytes
(User ROM area) M37902FGCHP 248 Kbytes
RAM M37902FCCHP 4096 bytes
Maskable interrups
Non-maskable interrups
Input/Output withstand voltage
Output current
M37902FJCHP 498 Kbytes
M37902FGCHP 6144 bytes
M37902FJCHP 12288 bytes
4 bits ✕ 2 channels; or 6 bits ✕ 1 channel + 2 bits ✕ 1 channel
5 external types, 13 internal types. Each interrupt can be set to a
priority level within the range of 0–7 by software.
1 external type, 3 internal types.
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator).
The following multiplication methods are available: double, triple,
and quadruple.
5 V±0.5 V
150 mW (at f(fsys) = 26 MHz, Typ., PLL frequency multiplier
stopped)
5 V
5 mA
Up to 16 Mbytes. Note that bank FF16 is a reserved area.
–20 to 85 °C
CMOS high-performance silicon gate process
100-pin plastic molded QFP
4
M37902FCCHP, M37902FGCHP, M37902FJCHP
FUNCTIONS (Flash memory mode)
Power supply voltage
Programming/Erase voltage
Flash memory mode
Block division for erasure
Programming method
Erase method
Programming/Erase control
Data protection method
Number of commands
Maximum number of reprograms
User ROM area
Boot ROM area
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
Flash memory parallel I/O mode
Flash memory serial I/O mode
Flash memory CPU reprogramming mode
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FunctionsParameter
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
5 V±0.5 V (in the flash memory parallel I/O mode, 3.3 V±0.3 V)
3 modes: parallel I/O, serial I/O, and CPU reprogramming modes
(Note 1)
1 block (16 Kbytes ✕ 1) (Note 2)
Programmed per page (in a unit of 256 Kbytes)
User ROM area + Boot ROM area
User ROM area
User ROM area
Total erase/Block erase
User ROM area + Boot ROM area
User ROM area
User ROM area
Programming/Erase control by software commands
Protected per block, by using a lock bit.
8 commands
100
Notes 1:
User ROM area
2:
On shipment, our reprogramming control firmware for the flash memory serial I/O mode has been stored into the boot ROM area.
Note that the boot ROM area can be erased/programmed only in the flash memory parallel I/O mode.
M37902FCCHP 5 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 1), total 120 Kbytes
M37902FGCHP 7 blocks (8 Kbytes ✕ 3, 32 Kbytes ✕ 1, 64 Kbytes ✕ 3), total 248 Kbytes
M37902FJCHP
11 blocks (2 Kbytes ✕ 1, 8 Kbytes ✕ 2, 32 Kbytes ✕ 1, 64 Kbytes ✕ 7), total 498 Kbytes
5
M37902FCCHP, M37902FGCHP, M37902FJCHP
PIN DESCRIPTION (MICROCOMPUTER MODE)
Input/
Output
—
Input
Input
Input
Input
Output
Input
—
—
Input
I/O
I/O
I/O
I/O
I/O
Apply 5 V±0.5 V to Vcc, and 0 V to Vss.
This pin controls the processor mode. Connect this pin to VSS for the single-chip
mode or memory expansion mode, and VCC for the microprocessor mode.
Connect this pin to Vss.
The microcomputer is reset when “L” level is applied to this pin.
These are input and output pins of the internal clock generating circuit. Connect a
ceramic or quartz- crystal resonator between the XIN and XOUT pins. When an
external clock is used, the clock source should be connected to the XIN pin, and the
XOUT pin should be left open.
This pin determines whether the external data bus has an 8-bit width or 16-bit width
for the memory expansion mode or microprocessor mode. The width is 16 bits when
“L” signal is input, and 8 bits when “H” signal is input. When BYTE = Vss level, by
the register setting, the external data bus for each of areas CS1 to CS3 can have a
width of 8 bits.
When using the PLL frequency multiplier, connect this pin to the filter circuit. When
not using, this pin should be left open.
Power supply input pins for the A-D converter and the D-A converter. Connect AVcc
to Vcc, and AVss to Vss externally.
This is the reference voltage input pin for the A-D converter and the D-A converter.
■ In single-chip mode
Port P0 is an 8-bit I/O port. This port has an I/O direction register, and each pin
can be programmed for input or output. These pins enter the input mode at
reset.
■ In memory expansion and microprocessor modes
Address (A16–A23) is output. These pins also function as I/O port pins according
to the register setting.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
The low-order 8 bits of data (D0–D7) are input/output. When the external data bus
has an 8-bit width, address (LA0–LA7) output and data (D0–D7) input/output can
be performed with the time-sharing method, according to the register setting.
■ In single-chip mode or When 8-bit external data bus is used in memory expansion
mode and microprocessor mode
These pins have the same functions as port P0.
■ When the 16-bit external data bus is used in memory expansion or microprocessor mode
The high-order 8 bits of data (D8–D15) are input or output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P30 functions as an I/O port pin; and P31, P32, and P33 function as the output
pins of RD, BLW, BHW, respectively. P30 also functions as an output pin of RDY
according to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
■ In microprocessor mode
P30 functions as an input pin of RDY; and P31,P32, P33 function as the output
pins of RD, BLW, BHW, respectively. P30 also functions as an I/O port pin according to the register setting. When the external data bus has a width of 8 bits,
the BHW pin functions as an I/O port pin (P33).
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion mode
P40–P47 function as I/O port pins. According to the register setting, these pins
function as output pins or input pins of ALE, φ1, HLDA, HOLD, CS0–CS3, respectively.
■ In microprocessor mode
P40–P44 function as output or input pins of ALE, φ1, HLDA, HOLD, CS0, and
P45–P47 as I/O port pins, respectively. According to the register setting, P40–P43
also function as I/O port pins, and P45–P47 as output pins of CS1–CS3.
Vcc, Vss
MD0
MD1
RESET
XIN
XOUT
BYTE
VCONT
AVcc,
AVss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40–P47
NamePin
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
External data bus width
select input
Filter circuit connection
Analog power supply input
Reference voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions
6
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P50–P57
P60–P67
P70–P77
P80–P87
P100–P107
P110–P117
NMI
NamePin
I/O port P5
I/O port P6
I/O port P7
I/O port P8
I/O port P10
I/O port P11
Non-maskable interrupt
Input/
Output
I/O
I/O
I/O
I/O
I/O
I/O
Input
Functions
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timers A0–A3, output pins for the real-time output,
and input pins for the key-input interrupt.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for timer A4, input pins for external interrupt inputs
____ ____
INT0–INT2, and input pins for timers B0–B2.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as input pins for the A-D converter, output pins for the D-A
converter, and input pins for INT2, INT3, and INT4.
In addition to having the same functions as port P0 in the single-chip mode, these
pins also function as I/O pins for UART0, UART1, output pins for D-A converter,
and input pins for INT3 and INT4.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A0–A7) is output.
■ In single-chip mode
These pins have the same functions as port P0.
■ In memory expansion and microprocessor modes
Address (A8–A15) is output. Also, these pins function as I/O port pins according to
the register setting.
This pin is for a non-maskable interrupt.
7
M37902FCCHP, M37902FGCHP, M37902FJCHP
PIN DESCRIPTION (FLASH MEMORY SERIAL I/O MODE)
Pin
VCC, VSS
MD0
MD1
_____
RESET
XIN
XOUT
BYTE
VCONT
AVcc, A Vss
VREF
P00–P07
P10–P17
P20–P27
P30–P33
P40,
P44– P47
P41
P42
P43
P50–P57
P60–P67
P70–P77
P80–P87
P100–P107
P110–P117
NMI
Name
Power supply input
MD0
MD1
Reset input
Clock input
Clock output
BYTE
Filter circuit connection
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
SCLK input
SDA I/O
BUSY output
Input port P5
Input port P6
Input port P7
Input port P8
Input port P10
Input port P11
Non-maskable interrupt
Input
/Output
—
Input
Input
Input
Input
Output
Input
—
—
Input
Input
Input
Input
Input
Input
Input
I/O
Output
Input
Input
Input
Input
Input
Input
Input
Apply 5 V ± 0.5 V to Vcc, and 0 V to Vss.
Connect this pin to Vss.
Connect this pin to Vss via a resistor of 10 kΩ to 100 kΩ.
The reset input pin.
Connect a ceramic resonator between the XIN and XOUT pins, or input an external
clock from the XIN pin with the XOUT pin left open.
Connect this pin to Vcc or Vss. (This is not used in the flash memory serial I/O mode.)
Connect this pin to the filter circuit, or leave this pin open. (This is not used in the flash memory serial I/O mode.)
Connect AVcc to Vcc, and AVss to Vss.
Input an arbitrary level within the range of VSS–VCC. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
This is an input pin for a serial clock.
This is an I/O pin for serial data. Connect this pin to VCC via a resistor (about 1 kΩ).
This is an output pin for the BUSY signal.
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H” or “L”, or leave them open. (This is not used in the flash memory serial I/O mode.)
Input “H”, or leave this pin open.
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions
8
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
These microcomputers contain the following devices on the single
chip: the flash memory, RAM, CPU, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial I/O,
A-D converter, D-A converter, I/O ports, clock generating circuit, etc.
MEMORY
Figures 1 to 3 show the memory maps. The address space is 16
Mbytes from addresses 016 to FFFFFF16. The address space is divided into 64-Kbyte units called banks. The banks are numbered
from 016 to FF16. Bank FF16 is a reserved area for the development
support tool. Therefore, do not use bank FF16.
000000
Bank 0
Bank 1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FE
Bank FF
00FFFF
010000
01FFFF
FE0000
FEFFFF
FF0000
FFFFFF
16
16
16
16
16
16
16
16
Reserved area
for development
support tool
16
16
16
16
000000
0000FF
000800
0017FF
001800
001FFF
002000
00FFC0
00FFFF
Internal flash memory and internal RAM are assigned as shown in
Figures 1 to 3.
Addresses FFC016 to FFFF16 contain the RESET and the interrupt
vector addresses, and the interrupt vectors are stored there.
For details, refer to the section on interrupts.
Assigned to addresses 016 to FF16 are peripheral devices such as
I/O ports, A-D converter, D-A converter, UART, timers, interrupt control registers, etc. Figures 7 and 8 show the location of SFRs.
For the flash memory in the boot ROM area, refer to the section on
the flash memory mode.
16
Peripheral devices
control registers
16
16
Internal RAM
4096 bytes
16
16
16
16
16
16
Internal flash memory
120 Kbytes
(User ROM area)
00FFC0
00FFFE
Interrupt vector table
16
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Address matching detect
Reserved area
Reserved area
INT
INT
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
NMI
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
4
3
2
1
0
Fig. 1 Memory map of M37902FCCHP (Single-chip mode)
9
Bank 0
Bank 1
Bank 2
Bank 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bank FE
Bank FF
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000000
00FFFF
010000
01FFFF
020000
02FFFF
030000
03FFFF
FE0000
FEFFFF
FF0000
FFFFFF
16
16
16
16
16
16
16
16
16
16
16
16
Reserved area
for development
support tool
16
16
16
16
16
16
000000
0000FF
000800
001FFF
002000
00FFC0
00FFFF
16
Peripheral devices
control registers
16
16
Internal RAM
6144 bytes
16
16
16
16
Internal flash memory
248 Kbytes
(User ROM area)
00FFC0
00FFFE
Interrupt vector table
16
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Address matching detect
Reserved area
Reserved area
INT
INT
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
NMI
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
4
3
2
1
0
Fig. 2 Memory map of M37902FGCHP (Single-chip mode)
000000
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
•
•
•
•
•
•
•
Bank FE
Bank FF
16
16
16
16
16
16
16
16
16
16
00FFFF
010000
01FFFF
020000
02FFFF
030000
03FFFF
040000
04FFFF
050000
05FFFF
060000
06FFFF
070000
07FFFF
FE0000
FEFFFF
FF0000
FFFFFF
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Reserved area
for development
support tool
000000
0000FF
000800
0037FF
003800
00FFC0
00FFFF
16
Peripheral devices
control registers
16
16
Internal RAM
12288 bytes
16
16
16
16
Internal flash memory
498 Kbytes
(User ROM area)
00FFC0
00FFFE
Interrupt vector table
16
Reserved area
Reserved area
Reserved area
Reserved area
Reserved area
Address matching detect
Reserved area
Reserved area
INT
INT
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
INT
INT
NMI
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
4
3
2
1
0
Fig. 3 Memory map of M37902FJCHP (Single-chip mode)
10
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000000
16
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
000013
000014
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
000021
000022
000023
000024
000025
000026
000027
000028
000029
00002A
00002B
00002C
00002D
00002E
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
Reserved area (Note)
16
Reserved area (Note)
Port P0 register
16
Port P1 register
16
16
Port P0 direction register
16
Port P1 direction register
16
Port P2 register
16
Port P3 register
Port P2 direction register
16
16
Port P3 direction register
16
Port P4 register
16
Port P5 register
16
Port P4 direction register
16
Port P5 direction register
16
Port P6 register
16
Port P7 register
16
Port P6 direction register
16
Port P7 direction register
16
Port P8 register
16
16
Port P8 direction register
16
16
Port P10 register
16
Port P11 register
16
Port P10 direction register
16
Port P11 direction register
16
16
16
16
16
A-D control register 0
16
A-D control register 1
16
A-D register 0
16
16
A-D register 1
16
16
A-D register 2
16
16
A-D register 3
16
16
A-D register 4
16
16
A-D register 5
16
16
A-D register 6
16
16
A-D register 7
16
16
UART0 transmit/receive mode register
16
UART0 baud rate register (BRG0)
16
UART0 transmit buffer register
16
16
UART0 transmit/receive control register 0
16
UART0 transmit/receive control register 1
16
UART0 receive buffer register
16
16
UART1 transmit/receive mode register
16
UART1 baud rate register (BRG1)
16
UART1 transmit buffer register
16
16
UART1 transmit/receive control register 0
16
UART1 transmit/receive control register 1
16
UART1 receive buffer register
16
Address (Hexadecimal notation)
Count start register
16
000040
000041
16
000042
000043
000044
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
One-shot start register
16
16
Up-down register
16
Timer A clock division select register
16
16
Timer A0 register
16
16
Timer A1 register
16
16
Timer A2 register
16
16
Timer A3 register
16
16
Timer A4 register
16
16
Timer B0 register
16
16
Timer B1 register
16
16
Timer B2 register
16
Timer A0 mode register
16
Timer A1 mode register
16
Timer A2 mode register
16
Timer A3 mode register
16
Timer A4 mode register
16
Timer B0 mode register
16
16
Timer B1 mode register
16
Timer B2 mode register
Processor mode register 0
16
16
Processor mode register 1
16
Watchdog timer register
Watchdog timer frequency select register
16
16
Particular function select register 0
Particular function select register 1
16
16
Particular function select register 2
16
Reserved area (Note)
16
Debug control register 0
Debug control register 1
16
16
Address comparison register 0
16
16
16
Address comparison register 1
16
16
16
3
interrupt control register
INT
16
INT
4
interrupt control register
A-D conversion interrupt control register
16
16
UART0 transmit interrupt control register
UART0 receive interrupt control register
16
16
UART1 transmit interrupt control register
16
UART1 receive interrupt control register
16
Timer A0 interrupt control register
16
Timer A1 interrupt control register
16
Timer A2 interrupt control register
16
Timer A3 interrupt control register
16
Timer A4 interrupt control register
16
Timer B0 interrupt control register
Timer B1 interrupt control register
16
16
Timer B2 interrupt control register
16
INT
0
interrupt control register
16
1
interrupt control register
INT
16
INT
2
interrupt control register
Fig. 7 Location of SFRs (1)
Note: Do not write to this address.
11
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
16
000080
000081
000082
000083
000084
000085
000086
000087
000088
000089
00008A
00008B
00008C
00008D
00008E
00008F
000090
000091
000092
000093
000094
000095
000096
000097
000098
000099
00009A
00009B
00009C
00009D
00009E
00009F
0000A0
0000A1
0000A2
0000A3
0000A4
0000A5
0000A6
0000A7
0000A8
0000A9
0000AA
0000AB
0000AC
0000AD
0000AE
0000AF
0000B0
0000B1
0000B2
0000B3
0000B4
0000B5
0000B6
0000B7
0000B8
0000B9
0000BA
0000BB
0000BC
0000BD
0000BE
0000BF
control register L
0
CS
control register H
16
CS
0
16
control register L
1
CS
control register H
16
CS
1
control register L
16
CS
2
control register H
2
CS
16
control register L
16
CS
3
control register H
16
3
CS
16
16
Area
16
16
Area
16
16
Area
16
16
Area
16
16
Port function control register
16
16
External interrupt input control register
16
External interrupt input read-out register
16
D-A control register
16
16
D-A register 0
16
16
D-A register 1
16
D-A register 2
16
16
Reserved area (Note)
16
Reserved area (Note)
16
Flash memory control register
16
16
Real-time output control register
16
Pulse output data register 0
16
16
Pulse output data register 1
16
16
16
16
16
16
16
16
16
Serial I/O pin control register
16
16
16
16
16
16
16
16
16
16
16
16
16
Reserved area (Note)
16
Reserved area (Note)
16
16
Clock control register
16
Reserved area (Note)
16
Reserved area (Note)
16
Reserved area (Note)
start address register
CS
0
start address register
CS
1
start address register
CS
2
start address register
CS
3
Address (Hexadecimal notation)
0000C0
16
0000C1
16
0000C2
16
0000C3
16
0000C4
16
0000C5
16
0000C6
16
0000C7
16
0000C8
16
0000C9
16
0000CA
16
0000CB
16
0000CC
16
0000CD
16
0000CE
16
0000CF
16
0000D0
16
0000D1
16
0000D2
16
0000D3
16
0000D4
16
0000D5
16
0000D6
16
0000D7
16
0000D8
16
0000D9
16
0000DA
16
0000DB
16
0000DC
16
0000DD
16
0000DE
16
0000DF
16
0000E0
16
0000E1
16
0000E2
16
0000E3
16
0000E4
16
0000E5
16
0000E6
16
0000E7
16
0000E8
16
0000E9
16
0000EA
16
0000EB
16
0000EC
16
0000ED
16
0000EE
16
0000EF
16
0000F0
16
0000F1
16
0000F2
16
0000F3
16
0000F4
16
0000F5
16
0000F6
16
0000F7
16
0000F8
16
0000F9
16
0000FA
16
0000FB
16
0000FC
16
0000FD
16
0000FE
16
0000FF
16
Note: Do not write to this address.
Fig. 8 Location of SFRs (2)
12
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has 13 registers and is shown in Figure 9. Each of these
registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists
of 16 bits and the low-order 8 bits can be used separately. Data
length flag m determines whether the register is used as 16-bit register or as 8-bit register. It is used as a 16-bit register when flag m is
“0” and as an 8-bit register when flag m is “1”. Flag m is a part of the
processor status register (PS) which is described later.
Data operations such as calculations, data transfer, input/output,
etc., are executed mainly through accumulator A.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the use
of accumulator B requires more instruction bytes and execution
cycles than accumulator A.
ACCUMULATOR E
Accumulator E is a 32-bit register and consists of accumulator A
(low-order 16 bits) and accumulator B (high-order 16 bits). It is used
for 32-bit data processing.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the low-order 8 bits can be
used separately. Index register length flag x determines whether the
register is used as 16-bit register or as 8-bit register. It is used as a
16-bit register when flag x is “0” and as an 8-bit register when flag x
is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register X is used as the index
register, the contents of this address are added to obtain the real address.
Index register X functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the low-order 8 bits can be
used separately. The index register length flag x determines whether
the register is used as 16-bit register or as 8-bit register. It is used as
a 16-bit register when flag x is “0” and as an 8-bit register when flag
x is “1”. Flag x is a part of the processor status register (PS) which is
described later.
In index addressing modes in which register Y is used as the index
register, the contents of this address are added to obtain the real address.
Index register Y functions as a pointer register which indicates an
address of data table in instructions MVP, MVN, RMPA (Repeat
MultiPly and Accumulate).
15 7 0
31
70
PG Program bank register PG
70
Fig. 9 Register structure
B
H
Accumulator B
Data bank register DTDT
B
L
Accumulator A
15 7 0
Accumulator E
1570
1570
15
1570
15 0
15 0
15 0
15
00000
A
H
A
H
B
H
X
H
H
Y
S
PC
DPR0 to DPR3
IPL2IPL1IPL
0
A
L
A
L
B
L
7
7
NVmxD I ZC
X
L
Y
L
0
0
Index register X
Index register Y
Stack pointer S
Program counter PC
Direct page registers DPR0 to DPR3
0
Processor status register PS
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
13
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative,
or stack pointer relative indirect indexed Y addressing mode.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order
16 bits of the next program memory address to be executed. There
is a bus interface unit between the program memory and the CPU,
so that the program memory is accessed through bus interface unit.
This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the high-order 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is increased
by 1. Also, when a carry or borrow occurs after adding or subtracting
the offset value to or from the contents of the program counter (PC)
using the branch instruction, the contents of the program bank register (PG) is increased or decreased by 1, so that programs can be
written without worrying about bank boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, the data bank register (DT) is used to specify a part of the
memory address. The contents of data bank register (DT) is used as
the high-order 8 bits of a 24-bit address. Addressing modes that use
the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit, absolute indexed X, absolute indexed Y, absolute bit relative, and stack pointer
relative indirect indexed Y.
DIRECT PAGE REGISTERS 0 to 3 (DPR0 to DPR3)
The direct page register is a 16-bit register. An addressing mode of
which name includes ‘direct’ generates an address of data to be accessed, regarding the contents of this register as the base address.
The 7900 Series has been expanded direct page registers up to 4
(DPR0 to DPR3), in comparison to the 7700 Series which has the
single direct page register. Accordingly, the 7900 Series’s direct ad-
dressing method which uses direct page registers differs from that of
the 7700 Series. However, the conventional direct addressing
method, using only DPR0, is still be selectable, in order to make use
of the 7700 Series software property. For more details, refer to the
section on the direct page.
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of
flags to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V , and
N.
The details of each bit of the processor status register are described
below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU after an arithmetic operation. This flag is also affected by shift and rotate instructions. This flag can be set and reset directly with the SEC
and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
The zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset
directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
watchdog timer, NMI, and software interrupt are disabled. This flag
is set to “1” automatically when an interrupt is accepted. It can be set
and reset directly with the SEI and CLI instructions or SEP and CLP
instructions.
___
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction
are performed as binary or decimal. Binary arithmetic is performed
when this flag is “0”. If it is “1”, decimal arithmetic is performed with
each word treated as 2- or 4- digit decimal. Arithmetic operation is
performed using four digits when data length flag m is “0” and with
two digits when it is “1”. Decimal adjust is automatically performed.
(Decimal operation is possible only with the ADC and SBC instructions.) This flag can be set and reset with the SEP and CLP instructions.
14
M37902FCCHP, M37902FGCHP, M37902FJCHP
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers.
The registers are used as 16-bit registers when flag x is “0” and as 8bit registers when it is “1”.
This flag can be set and reset with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit or
8-bit. The data length is 16 bits when flag m is “0” and 8 bits when it
is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag is valid when addition or subtraction is performed
with a word treated as a signed binary number. If data length flag m
is “0”, the overflow flag is set when the result of addition or subtraction is outside the range between –32768 and +32767. If data length
flag m is “1”, the overflow flag is set when the result of addition or
subtraction is outside the range between –128 and +127. It is reset
in all other cases. The overflow flag can also be set and reset directly
with the SEP, and CLV or CLP instructions.
Additionally, the overflow flag is set when a result of unsigned/signed
division exceeds the length of the register where the result is to be
stored; the flag is also set when the addition result is outside range
of –2147483648 to +2147483647 in the RMPA operation.
MITSUBISHI MICROCOMPUTERS
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, data’s bit 15 is
“1”. If data length flag m is “1”, data’s bit 7 is “1”.) It is reset in all other
cases. It can also be set and reset with the SEP and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and determines the priority of processor interrupts from level 0 to level 7.
Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher than
the processor interrupt priority . When an interrupt is enabled, the current processor interrupt priority level is saved in a stack and the processor interrupt priority level is replaced by the interrupt priority level
of the device requesting the interrupt. Refer to the section on interrupts for more details.
Note: Fix bits 11 to 15 of the processor status register (PS) to “0”.
15
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BANK
In order to effectively use the integrated hardware on the chip, this
CPU core uses an address generating method with a 24-bit address
split into high-order 8 bits and low-order 16 bits. In other words, the
64 Kbytes specified by the low-order 16 bits are one unit (referred to
as “bank”), and the address space is divided into 256 banks (016 to
FF16) specified by the high-order 8 bits.
In the program area on the address space, the bank is specified by
the program bank register (PG), and the address in the bank is
specified by the program counter (PC).
As for each bank boundary, when an overflow has occurred in PC,
the contents of PG are incremented by 1. When a borrow has occurred in PC, the contents of PG are decremented by 1. Under the
normal conditions, therefore, programming without concern for the
bank boundaries is possible. Furthermore, as for the data area on
the address space, the bank is specified by the data bank register
(DT), and the address in the bank is specified by the operation result
by using the various addressing modes (Note).
Note: Some addressing modes directly specify a bank.
DIRECT PAGE
The internal memory and control registers for internal peripheral devices, etc. are assigned to bank 016 (addresses 016 to FFFF16). The
direct page and direct addressing modes have been provided for the
effective access to bank 016. In the 7900 Series, two types of direct
addressing modes are available: the conventional direct addressing
mode which uses only DPR0, as in the 7700 Series, and the expanded direct addressing mode, which uses up to 4 direct page registers as selected by the user. The addressing mode is selected
according to the contents of bit 1 of the processor mode register 1.
This bit 1 is cleared to “0” at reset. (In other words, the conventional
direct addressing mode is selected.) However, once this bit 1 has
been set to “1” by software, this bit cannot be cleared to “0” again,
except by reset. That is to say , when one of these two direct addressing modes has been selected just after reset, the selected addressing mode cannot be switched to another one while the program is
running.
Refer to “7900 Series Software Manual” for details concerning the
various addressing modes which use the direct page area.
Instruction Set
The CPU core of the 7900 Series has an expanded instruction set
based on the existing 7700/7751 Series’ CPU core. In addition, its
source code (mnemonic) has the complete upper compatibility with
the 7700 Series instruction set.
For details concerning addressing modes and instruction set, refer to
“7900 Series Software Manual”.
■ Conventional direct addressing mode
The direct page area consists of 256-byte space. Its bank address is
“0016”, and the base address of its low-order 16-bit address is specified by the contents of the direct page register 0 (DPR0). In this conventional direct addressing modes, a value (1 byte) just after an
instruction code is regarded as an offset value for the DPR0 contents, and the CPU accesses each address in the direct page area.
■ Expanded direct addressing mode
The direct page area consists of four 64-byte spaces. Their bank
address is “0016”, and the four base addresses of their low-order 16bit addresses are respectively specified by the contents of four direct
page registers. In this expanded direct addressing mode, a value (1
byte) just after an instruction code is regarded as follows:
• High-order 2 bits: regarded as a selection field for DPR0 to DPR3.
• Low-order 6 bits: regarded as an offset value for the selected direct
page register.
Then, the CPU accesses each address in each direct page area:
16
MITSUBISHI MICROCOMPUTERS
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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BUS INTERFACE UNIT
Data transfer between the central processing unit (CPU) and internal memory, internal peripheral devices, or external areas is always
performed via the bus interface unit (BIU), which is located between
the CPU and the internal buses.
Figure 10 shows the BIU and the bus structure. The CPU and BIU
are connected by a dedicated bus, and any transfer between the
CPU and BIU is controlled by this dedicated bus.
On the other hand, data transfer between the BIU and internal peripheral devices uses the following internal common buses: 32-bit
code bus, 16-bit data bus, 24-bit address bus, and control signals.
The bus control method where the code bus and the data bus separate out (hereafter, this method is referred to as the separate code/
M37902
Central
Processing
Unit
(CPU)
CPU bus
Bus
Interface
Unit
(BIU)
Internal code bus (CB0 to CB31)
Internal data bus (DB0 to DB15)
Internal address bus (AD0 to AD23)
Internal control signal
data bus method) is employed in order to improve data transfer capabilities. As a result, the internal memory is connected to both the
code bus and the data bus, and registers of all other internal peripheral devices are connected only to the data bus.
Each width of external buses are as follows: a 24-bit address bus,
16-bit data bus.
The external data bus transfers instruction codes and data. When
the code or data access occurs for the external, the external access
is performed via the bus conversion circuit.
For details of the connection with the external devices, refer to the
section on the processor modes and chip select wait controller described later.
Internal buses
Internal
memory
Hold request
SFR : Special Function Register
❈ The CPU bus, internal bus, and external bus separate out independently.
Fig. 10 BIU and bus structure
Internal
peripheral
devices
(SFR)
conversion
circuit
Bus
External bus
A0 to A
23
D0 to D7 (LA0 to LA7)
8
to D
15
D
Control signal
HOLD
HLDA
External
devices
17
M37902FCCHP, M37902FGCHP, M37902FJCHP
BIU structure
The BIU consists of four registers shown in Figure 11. Table 1 lists
the functions of each register.
Table 1. Functions of each register
Name
Program address register
Instruction queue buffer
Data address register
Data buffer
Indicates a storage address for an instruction to be next taken into an instruction queue buffer.
Temporarily stores an instruction which has been taken from a memory. Consists of 10 bytes.
Indicates an address where data will be next read from or written to.
Temporarily stores data which has been read from internal memory, internal peripheral devices, and
external areas by the BIU; or temporarily stores data which is to be written to internal memory, internal
peripheral devices, and external areas by the CPU. Consists of 32 bits.
MITSUBISHI MICROCOMPUTERS
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Functions
Fig.11 Register structure of BIU
b23
b0
PA
b7 b0
Q0
Q9
b23 b0
DA
b31 b0
DQ
Program address register
Instruction queue buffer
Data address register
Data buffer
18
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BIU Functions
(1) Instruction prefetch
The BIU has ten instruction queue buffers; each buffer consists of 1
byte. When there is an opening in the bus and the instruction queue
buffer, an instruction code is read from the program memory (in other
words, the memory where a program is stored) and prefetched into
an instruction queue buffer. The prefetched instruction code is transferred from the BIU to the CPU, in response to a request from the
CPU, via a dedicated bus.
When a branch occurs as a result of a branch instruction (JMP, BRA,
etc.), subroutine call, or interrupt, the contents of the instruction
queue buffer are initialized and the BIU reads a new instruction from
the branch destination address.
Note that the operations of the BIU instruction prefetch also differ depending on the store addresses for instructions. The store addresses
for instructions to be prefetched are categorized as listed in Table 2.
(2) Data read operation
When executing an instruction for reading data from the internal
memory, internal peripheral devices, or external areas, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU reads the above data from the specified address,
passes it to the data buffer, and then, transfers it to the CPU.
[Instruction prefetch]
• Whether the address area locates in the internal area or the external area.
• When the address area locates in the external area
➀ Whether the external bus width = 16 bits or 8 bits:
(a) When the external bus width = 16 bits:
whether the start address for access locates at a 4byte boundary or at an 8-byte boundary.
(b) When the external bus width = 8 bits:
whether the start address for access locates at an
even address, a 4-byte boundary or at the 8-byte bound
ary.
➁ Whether the prefetch operation is generated by a branch, or
not.
➂ Number of waits
➃ Whether the burst ROM access is specified or not.
Table 2. Store addresses for instructions to be prefetched
Low-order 3 bits of store address for instruction
AD1 (A1)
X
0
0
AD0 (A0)
0
0
0
Even address
4-byte boundary
8-byte boundary
X: 0 or 1
AD2 (A2)
X
X
0
(3) Data write operation
When executing an instruction for writing data into the internal
memory, internal peripheral devices, or external area, at first, the
CPU informs the BIU’s data address register of the address where
the data has been located.
Next, the BIU passes the above data to the data buffer register, and
then, writes it into the specified address.
(4) Bus cycle
In order for the BIU to execute the above operations (1) through (3),
the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal
control signals must be appropriately controlled during data transfer
between the BIU and internal memory, internal peripheral devices,
external areas. This operation is called “bus cycle”. The bus cycle is
affected by the following conditions at instruction prefetch and data
access.
[Data Access]
• Whether the address area locates in the internal area or the external area.
• Length of data to be transferred: byte, word, double word
• When the address area locates in the external area:
➀ Whether the external bus width = 16 bits or 8 bits:
➁ Number of waits
The BIU controls the bus cycle depending on the above conditions.
Figures 12 to 16 show the bus cycle waveform examples for instruction prefetch and data access.
19
MITSUBISHI MICROCOMPUTERS
Access to internal area
Access to external area
When address locates at 4-byte boundary or when branched:
double consecutive access
When branched or at instruction
prefetch
When external data bus width = 16 bits When external data bus width = 8 bits
φ
BIU
Internal address bus
Internal code bus
CB
0
to CB
31
Code
φ
1
A
0
to A
23
D
0
to D
7
D
8
to D
15
ALE
RD
BLW
BHW
D
0
to D
7
D
0
to D
7
D
8
to D
15
D
8
to D
15
Address Address + 2
When address of instruction to be prefetched locates at 8-byte boundary:
quadruple consecutive access
φ
1
A
0
to A
23
D
0
to D
7
D
8
to D
15
ALE
RD
BLW
BHW
D
0
to D
7
D
0
to D
7
D
0
to D
7
D
0
to D
7
D
8
to D
15
D
8
to D
15
D
8
to D
15
D
8
to D
15
Address Address + 2
Address + 4 Address + 6
When address is even address or when branched:
double consecutive access
φ
1
A
0
to A
23
D
0
to D
7
ALE
RD
BLW
BHW
D
0
to D
7
D
0
to D
7
Address Address + 1
When address of instruction to be prefetched locates at 4-byte boundary or
8-byte boundary: quadruple consecutive access
φ
1
A
0
to A
23
D
0
to D
7
ALE
RD
BLW
BHW
D
0
to D
7
D
0
to D
7
D
0
to D
7
D
0
to D
7
Address Address + 1
Address + 2 Address + 3
Address
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 12 Bus cycle waveform example for instruction prefetch
20
8-bit
data
read
8-bit
data
written
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address Access starting from odd address
φ
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
BIU
Address
D0 to D7
Invalid
Address
D0 to D7
Internal address bus
Internal address bus
φ
BIU
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Internal data bus
DB0 to DB7
DB8 to DB15
Address
Address
Invalid
D8 to D
D8 to D
15
15
φ
BIU
16-bit
data
read
Access to internal area
16-bit
data
written
32-bit
data
read
32-bit
data
written
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
A0 to A23
D0 to D7
D8 to D15
φ
BIU
Internal address
bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
BIU
Internal address
bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
1
Address
Address
Address
Address
D8 to D
D8 to D
D0 to D7
D8 to D
D0 to D7
D8 to D
15
15
15
15
Address + 2
Address + 2
D0 to D7D0 to D7
D8 to D
D0 to D7D0 to D7
D8 to D
φ
BIU
D8 to D
D8 to D
15
15
Invalid
15
15
Address + 1
Address + 1
D0 to D7
D8 to D
D0 to D7
D8 to D
D0 to D7
Invalid
D0 to D7
15
15
Address + 3
D0 to D7
Invalid
Address + 3
D0 to D7
Internal address bus
Internal data bus
DB0 to DB7
DB8 to DB15
φ
1
A0 to A23
D0 to D7
D8 to D15
φ
BIU
Internal address
bus
Internal data bus
15
15
DB0 to DB7
DB8 to DB15
φ
Internal address
bus
Internal data bus
DB0 to DB7
DB8 to DB15
BIU
Address
Address
Address Address + 1
Invalid
D8 to D
Address Address + 1
D8 to D
Fig. 13 Bus cycle waveform example for data access (access to internal area)
21
8-bit
data
read
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address Access starting from odd address
φ
A0 to A
D0 to D
D8 to D
BHW
1
ALE
RD
BLW
23
7
15
Address
D0 to D
Invalid
7
φ
A0 to A
D0 to D
D8 to D
BHW
1
ALE
RD
BLW
23
7
15
Address
D8 to D
Invalid
15
φ
1
A0 to A
23
D0 to D
D8 to D
BHW
φ
A0 to A
D0 to D
D8 to D
BHW
φ
A0 to A
D0 to D
D8 to D
BHW
7
15
ALE
RD
BLW
1
23
7
15
ALE
RD
BLW
1
23
7
15
ALE
RD
BLW
8-bit
data
written
16-bit
External data bus width = 16 bits
data
read
16-bit
data
written
Address
D0 to D
Address
D7 to D
D8 to D
Address
D0 to D
D8 to D
φ
1
A0 to A
23
D0 to D
D8 to D
BHW
φ
A0 to A
D0 to D
D8 to D
BHW
φ
A0 to A
D0 to D
D8 to D
BHW
7
15
ALE
RD
BLW
1
23
7
15
ALE
RD
BLW
1
23
7
15
ALE
RD
BLW
7
0
15
7
15
Address
D8 to D
15
Address Address + 1
Invalid
D8 to D
15
D0 to D
Invalid
Address Address + 1
D0 to D
D8 to D
15
7
7
Fig. 14 Bus cycle waveform example for data access (access to external area) (1)
22
32-bit
data
read
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even address Access starting from odd address
φ
A0 to A
D0 to D
D8 to D
BHW
1
ALE
RD
BLW
23
7
15
Address Address + 2
D0 to D
D8 to D
7
15
D0 to D
D8 to D
7
15
φ
A0 to A
D0 to D
D8 to D
BLW
BHW
1
ALE
RD
23
7
15
Address Address + 1 Address + 3
Invalid
D8 to D
15
D0 to D
D8 to D
7
15
D0 to D
Invalid
7
φ
A0 to A
D0 to D
D8 to D
BLW
BHW
1
23
7
15
ALE
RD
φ
1
A0 to A
23
D0 to D
32-bit
External data bus width = 16 bits
data
written
D8 to D
BHW
7
15
ALE
RD
BLW
Address Address + 2
D0 to D
D8 to D
D0 to D
D8 to D
7
15
7
15
Fig. 15 Bus cycle waveform example for data access (access to external area) (2)
Address Address + 1 Address + 3
D0 to D
D8 to D
7
15
D8 to D
15
D0 to D
7
23
32/16/
8-bit
data
read
A0 to A
D0 to D
D8 to D
BHW
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Access starting from even or odd address
φ
1
ALE
RD
BLW
23
7
15
(Note)
(Note)
Address Address + 1 Address + 2 Address + 3
D0 to D
D0 to D
8-bit data access
16-bit data access
7
7
32-bit data access
D0 to D
7
D0 to D
7
φ
1
A0 to A
23
D0 to D
7
D8 to D
15
External data bus width = 8 bits
32/16/
8-bit
data
written
ALE
RD
BLW
BHW
(Note)
(Note)
Address Address + 1 Address + 2 Address + 3
D0 to D
D0 to D
8-bit data access
16-bit data access
7
7
32-bit data access
Note: When the voltage level at pin BYTE = “L”, functions as pins D8 to D15 are valid. However, when 8-bit width is selected
as the external bus width by the chip select wait controller, the functions as pins D
8 to D15 = floating, BHW = “H” output.) When the voltage level at pin BYTE = “H”, these pins function as programmable
(D
I/O port (P2, P3
3) pins.
Fig. 16 Bus cycle waveform example for data access (access to external area) (3)
D0 to D
7
D0 to D
7
8 to D15 and BHW become invalid.
24
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Number of bus cycles
Figure 17 shows the bus cycle waveform at access to the internal
area. Bit 7 of the processor mode register 1 (address 5F16) selects
the number of bus cycles for the internal ROM: 3φ or 2φ. (This bit 7 is
the internal ROM bus cycle select bit.) The internal RAM, SFRs (in-
1 bus cycle = 3φ (Note)
(Internal ROM bus cycle select bit = 0)
1 bus cycle = 3φ
φ
BIU
ROM
RAM
Internal address bus
Internal data bus
Internal code bus
Address
Data
Internal address bus
φ
BIU
ternal peripheral devices’ control registers) are always accessed with
1 bus cycle = 2φ. Figure 18 shows the bus cycle waveform at access
to the external area. The bus cycle select bits 0, 1 (See the note in
Figure 18.) select the number of the bus cycles for each CSi area
___
from 8 types of numbers.
1 bus cycle = 2φ
(Internal ROM bus cycle select bit = 1)
1 bus cycle = 2φ
φ
BIU
Internal address bus
Internal data bus
Internal code bus
1 bus cycle = 2φ
Address
Address
Data
SFR
Internal data bus
Internal code bus
Data
Note: When reprogramming the internal flash memory in the CPU reprogramming mode, select the bus cycle = 3φ.
Fig. 17 Bus cycle waveform at access to internal area
25
MITSUBISHI MICROCOMPUTERS
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SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle
select bit 0
0 0
0 1
1 0
Bus cycle select bit 1 = 0
Bus cycle 1φ + 1φ
1 bus cycle = 2φ
φ1
External address
External data bus
Bus cycle 1φ + 2φ
External address
External data bus
Bus cycle 1φ + 3φ
External address
External data bus
bus
CSi
BLW,BHW
ALE
bus
CSi
BLW,BHW
ALE
bus
CSi
BLW,BHW
ALE
RD
φ1
RD
φ1
RD
Address
Data
1 bus cycle = 3φ
Address
1 bus cycle = 4φ
Address
Data
Data
Bus cycle 2φ + 3φ
❈
External data bus
Bus cycle 2φ + 4φ
❈
External data bus
Bus cycle 3φ + 3φ
❈
External data bus
External address
External address
External address
bus
BLW,BHW
ALE
bus
BLW,BHW
ALE
bus
BLW,BHW
ALE
Bus cycle select bit 1 = 1
1 bus cycle = 5φ
2φ
φ1
Address
CSi
RD
1 bus cycle = 6φ
φ1
CSi
RD
1 bus cycle = 6φ
φ1
CSi
RD
❈
3φ
Data
❈
4φ2φ
Address
Data
3φ3φ
Address
Data
Bus cycle 2φ + 2φ
1 bus cycle = 4φ
φ1
External address
1 1
Notes 1: The bus cycle type is determined by the following bits:
• Areas out of area CS
• Area CS
External data bus
i : area CSi bus cycle select bit 0 (bits 0 and 1 at addresses 8016, 8216, 8416, 8616)
2: ❈ indicates the bus cycle, where the burst ROM access specification is enabled.
bus
CSi
RD
BLW,BHW
ALE
i : external bus cycle select bit 0 (bits 2 and 3 at address 5E16)
external bus cycle select bit 1 (bit 0 at address 5F
area CS
Address
i bus cycle select bit 1 (bit 3 at addresses 8116, 8316, 8516, 8716)
Fig. 18 Bus cycle types at access to external area
Data
Bus cycle 3φ + 4φ
φ1
External address
External data bus
16)
bus
BLW,BHW
ALE
CSi
RD
3φ
1 bus cycle = 7φ
4φ
Address
Data
26
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Recovery cycle
A recovery cycle which is equivalent to 1 or 2 cycles of φ1 can be inserted after each area CSi’s access cycle. Whether the recovery
cycle is inserted or not is determined by the recovery cycle insert
select bit of each CSi control register L (bit 6 at addresses 8016, 8216,
φ1
❈
A
0
to A
ALE
access
RD
At double consecutive
φ
❈❈
At instruction prefetch
A0 to A
23
ALE
access
RD
At quadruple consecutive
At data access
___
___
Recovery cycle = 1 cycle of φ1 Recovery cycle = 2 cycles of φ1
Recovery
Next access
Instruction prefetch
23
Address Address + 2
❈ When address locates at 4-byte boundary, or when branched.
1
Address Address + 2 Address + 4
❈❈ When address locates at 8-byte boundary.
Access cycle
φ
1
A0 to A
23
Address
ALE
RD,
BLW, BHW
cycle
Instruction prefetch
Recovery
Next access
cycle
cycle
cycle
Address + 6
Recovery
cycle
Next access
8416, 8616). Also, the number of the recovery cycles is selected by
the recovery-cycle-insert-number select bit of the processor mode
register 1 (bit 6 at address 5F16). Figure 19 shows a waveform example when a recovery cycle is inserted.
Next access
cycle
Next access
cycle
Recovery cycle
Address + 6
cycle
A0 to A
A0 to A
Instruction prefetch
φ
1
23
Address Address + 2
ALE
RD
φ
1
23
Address Address + 2 Address + 4
ALE
RD
Access cycle
φ
1
A0 to A
ALE
RD,
BLW, BHW
23
Address
Recovery cycle
Instruction prefetch
Recovery cycle
Next access
cycle
Notes 1: The recovery cycle insert is specified by the recovery cycle insert select bit and the recovery-cycle-insert-number select bit (bits 4 and 6 at address 5F16).
Recovery cycle insertion is valid only at access to area CS
2: The above is applied when 1 bus cycle = 2φ.
i.
Fig. 19 Waveform example when recovery cycle is inserted
27
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Burst ROM access
When ROM supporting the burst ROM access has been allocated to
___
area CSi, the burst ROM access can be specified. The burst ROM
access is specified by each burst ROM access select bit of the CSi
control register L (bit 5 at addresses 8016, 8216, 8416, 8616). The
burst ROM access is valid only when the external data bus width =
16 bits with an instruction prefetched. In the other cases, the normal
access is performed regardless of the contents of the burst ROM access select bit. The burst ROM access can be specified only in the
case of ❈ in Figure 18.
(a)
φ
1
RD
External address bus
(A
0
to A23)
External data bus
0
to D7)
(D
External data bus
(D8 to D15)
At quadruple consecutive accessAt double consecutive access
___
Address Address Address Address
Figure 20 shows a waveform example at burst ROM access.
When an instruction is prefetched from the burst ROM, 8 bytes are
fetched starting from an 8-byte boundary (the low-order 3 bits of address, A2, A1, A0 = “000”) in waveform (a). When branched, regardless of the 8-byte boundary of the branch destination address,
access starting from the 4-byte boundary (the low-order 2 bits of address, A1, A0 = “00”) is performed in waveform (b). Once the 8-byte
boundary has been selected, instructions will be prefetched in waveform (a) until a branch.
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Note: The above is applied when 1 bus cycle = 2φ.
(b)
φ
1
RD
External address bus
(A0 to A23)
External data bus
0
to D7)
(D
External data bus
8
to D15)
(D
Note: The above is applied when 1 bus cycle = 2φ.
Notes 1: The burst ROM access is selected by the burst ROM access select bit (bit 5 at addresses 80
2: The burst ROM access can be selected only in the case of ❈ in Figure 18.
Fig. 20 Waveform example at burst ROM access
Address Address
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
16
, 8216, 8416, 8616).
28
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Address output selection
As shown in Figure 21, the unnecessary state change of address
output pins (A0 to A23) can be avoided, without outputting an address
at access to the internal area.
When the address output select bit of the particular function select
register 1 (bit 4 at address 6316) is set to “1”, an address is output
only at access to the external area. Also, at access to the internal
Address output select bit = 0
Address output select bit = 1
(Address waveform changes only
when external access is generated.)
A0 to A
BLW,BHW
A0 to A
BLW,BHW
area, the address at the preceding access to the external area is retained. The address output start timing in this case is the half cycle
of φ1 later than that at the normal access (when the address output
select bit = “0”). For the bit structure of the particular function select
register 1, refer to the section on the standby function.
Also, at the normal access, an address is output at both of the access to the internal and external areas.
Access to
external area
Address
Address
φ
1
RD,
RD,
23
23
Access to
external area
Address
Access to
internal area
Unde-
fined
Address
Unde-
fined
Fig. 21 Waveform example depending on address output function selection
29
MITSUBISHI MICROCOMPUTERS
M37902FCCHP, M37902FGCHP, M37902FJCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
● Area multiplication
When area CS2’s external data bus width = 8 bits with the multiplexed bus select bit of the CS2 control register H (bit 5 at address
8516) = “1”, the external bus type can be changed to the multiplexed
bus type only at access to area CS2. In this case, the low-order 8 bits
___
___
Area CS2 bus
cycle select
bit 0
___
Bus cycle
select bit 0
Multiplexed bus select bit = 1
Bus cycle 2φ + 2φ
φ1
External address bus
At write, LA0/D0 to LA7/D7
0
1 1
At read, LA0/D0 to LA7/D7
CSi
RD,
BLW
ALE
Bus cycle 3φ + 3φ
φ1
External address bus
1
1 0
At write, LA0/D0 to LA7/D7
At read, LA0/D0 to LA7/D7
CSi
RD,
BLW
ALE
of an address (LA0 to LA7) are output, and the low-order 8 bits of
data (D0 to D7) are input/output with the time-sharing method, respectively.
Figure 22 shows a waveform example of area multiplication for each
bus cycle. Do not select the area multiplication function for a bus
cycle not shown in Figure 22.
1 bus cycle = 4φ
2φ 2φ
Address
LA0 to LA7
LA0 to LA7
LA0 to LA7
LA0 to LA7
D0 to D7
D0 to D7
1 bus cycle = 6φ
3φ3φ
Address
D0 to D7
D0 to D7
Bus cycle 3φ + 4φ
φ1
External address bus
1
Notes 1: The number of bus cycles is determined by the following bits:
Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 8516).
2: Do not select the area multiplication function for a bus cycle not shown in Figure 22.
1 1
• Area CS2 bus cycle select bit 0 (bits 0 and 1 at address 8416)
• Area CS2 bus cycle select bit 1 (bit 3 at address 8516)
At write, LA0/D0 to LA7/D7
At read, LA0/D0 to LA7/D7
CSi
RD,
BLW
ALE
Fig. 22 Waveform example of area multiplication for each bus cycle
30
LA0 to LA7
LA0 to LA7
1 bus cycle = 7φ
4φ3φ
Address
D0 to D7
D0 to D7
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