Mitsubishi M37735M4BXXXFP Datasheet
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37735M4BXXXFP is a single-chip microcomputer using the
7700 Family core. This single-chip microcomputer has a CPU and a
bus interface unit. The CPU is a 16-bit parallel processor that can be
an 8-bit parallel processor, and the bus interface unit enhances the
memory access efficiency to execute instructions fast. This
microcomputer also includes a 32 kHz oscillation circuit, in addition
to the ROM, RAM, multiple-function timers, serial I/O, A-D converter,
and so on.
FEATURES
●Number of basic instructions .................................................. 103
●Memory size ROM .................................................32 Kbytes
RAM................................................ 2048 bytes
●Instruction execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
●Single power supply ...................................................... 5 V ± 10 %
●Low power dissipation (at 25 MHz frequency)
............................................47.5 mW (Typ.)
●Interrupts ............................................................ 19 types, 7 levels
●Multiple-function 16-bit timer ................................................. 5 + 3
PIN CONFIGURATION (TOP VIEW)
1
RTS
/
1
1
1
1
CTS
/
4
P8
/CLK
5
P8
D
X
/R
6
P8
D
X
/T
7
P8
0
CS
/
0
P0
1
CS
/
1
P0
2
CS
/
2
P0
3
CS
/
3
P0
4
CS
/
4
P0
●Serial I/O (UART or clock synchronous) ..................................... 3
●10-bit A-D converter ............................................ 8-channel inputs
●12-bit watchdog timer
●Programmable input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68
●Clock generating circuit ........................................ 2 circuits built-in
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, and so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
16
RSMP
/
/A
5
6
P0
P0
17
/A
7
P0
8
/D
8
/A
0
P1
9
/D
9
/A
1
P1
10
/D
10
/A
2
P1
11
/D
11
/A
3
P1
12
/D
12
/A
4
P1
13
/D
13
/A
5
P1
14
/D
14
/A
6
P1
15
/D
15
/A
7
P1
0
/D
0
/A
0
P2
1
/D
1
/A
1
P2
2
/D
2
/A
2
P2
3
/D
3
/A
3
P2
P82/RXD0/CLKS
P8
0
/CTS0/RTS0/
P76/AN6/Xc
P75/AN5/
P74/AN4/RxD
P73/AN3/CLK
P72/AN2/CTS
P83/TXD
P81/CLK
CLKS
AV
V
AV
P77/AN7/Xc
AD
TRG
/TxD
P71/AN
60
59
62
61
64
63
65
0
66
0
67
0
68
1
69
V
CC
70
CC
71
REF
72
SS
73
V
SS
74
IN
75
OUT
76
2
77
2
78
2
79
2
80
1
3
IN
/TB1
6
P6
4
IN
/TB0
5
P6
5
2
NT
/I
4
P6
6
1
NT
/I
3
P6
1
0
/AN
0
P7
2
SUB
/φ
IN
/TB2
7
P6
55
58
56
57
52
53
54
51
M37735M4BXXXFP
7
0
NT
/I
2
P6
8
IN
/TA4
1
P6
9
OUT
/TA4
0
P6
10
3
KI
/
IN
/TA3
7
P5
11
2
KI
/
OUT
/TA3
6
P5
12
1
KI
/
IN
/TA2
5
P5
13
0
KI
/
OUT
/TA2
4
P5
14
IN
/TA1
3
P5
50
15
OUT
/TA1
2
P5
49
16
IN
/TA0
1
P5
47
45
48
46
20
17
19
18
OUT
P47 P46 P45 P44 P4
/TA0
0
P5
42
43
41
44
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
22
21
24
23
1
3
/φ
2
RDY
/
1
P4
P4
Outline 80P6N-A
P24/A4/D
P25/A5/D
P26/A6/D
P27/A7/D
P30/
WEL
P31/
WEH
P32/
ALE
P33/
HLDA
V
ss
E/RDE
X
OUT
X
IN
RESET
CNV
SS
BYTE
P40/
HOLD
4
5
6
7
1
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Bus(Even)
Data Bus(Odd)
BYTE
selection input
External data bus width
VREF
Reference
voltage input
AVCC
AVSS
(0V)
CNVss
SS
V
(0V)
VCC
Instruction Register(8)
Data Buffer DB
H(8)
Data Buffer DBL(8)
Instruction Queue Buffer Q
Instruction Queue Buffer Q
Instruction Queue Buffer Q2(8)
0(8)
1(8)
Incrementer(24)
Program Address Register PA(24)
Data Address Register DA(24)
Incrementer/Decrementer(24)
Program Counter PC(16)
Program Bank Register PG(8)
Data Bank Register DT(8)
Input Butter Register IB(16)
Address Bus
UART2(9)
UART1(9)
A-D Converter(10)
UART0(9)
P0(8)
P1(8)
P2(8)
P4(8) P3(4)
Input/Output
port P0
Input/Output
port P1
Input/Output
port P2
Input/Output
port P3
Input/Output
port P4
Processor Status Register PS(11)
Direct Page Register DPR(16)
RESET
Reset input
Stack Pointer S(16)
Index Register Y(16)
XCIN
XCOUT
Index Register X(16)
Accumulatcr B(16)
E
Enable output
XOUT
Clock output
Clock Generating Circuit
XIN
Clock input
Accumulator A(16)
Arithmetic Logic
M37735M4BXXXFP BLOCK DIAGRAM
Unit(16)
Timer TB2(16)
Watchdog Timer
Timer TA2(16)
Timer TA3(16)
Timer TA4(16)
RAM
ROM
Timer TB0(16)
Timer TB1(16)
Timer TA0(16)
Timer TA1(16)
2048 bytes
32 Kbytes
XCOUT
XCIN
P5(8) P6(8)
P7(8)
P8(8)
Input/Output
port P5
Input/Output
port P6
Input/Output
port P7
Input/Output
port P8
2
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONS OF M37735M4BXXXFP
Number of basic instructions 103
Instruction execution time 160 ns (the fastest instruction at external clock 25 MHz frequency)
Memory size
Input/Output ports
Multi-function timers
Serial I/O (UART or clock synchronous serial I/O) ✕ 3
A-D converter 10-bit ✕ 1 (8 channels)
Watchdog timer 12-bit ✕ 1
Interrupts
Clock generating circuit
Supply voltage 5 V ± 10%
Power dissipation 47.5 mW (at external clock 25 MHz frequency)
Input/Output characteristic
Memory expansion Maximum 1 Mbytes
Operating temperature range –20 to 85 °C
Device structure CMOS high-performance silicon gate process
Package 80-pin plastic molded QFP (80P6N-A)
Parameter Functions
ROM 32 Kbytes
RAM 2048 bytes
P0 – P2, P4 – P8 8-bit ✕ 8
P3 4-bit ✕ 1
TA0, TA1, TA2, TA3, TA4 16-bit ✕ 5
TB0, TB1, TB2 16-bit ✕ 3
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
Input/Output voltage 5 V
Output current 5 mA
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Pin Name Input/Output Functions
Vcc, Power source Apply 5 V ± 10% to Vcc and 0 V to Vss.
Vss
CNVss CNVss input Input This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory
_____
RESET Reset input Input When “L” level is applied to this pin, the microcomputer enters the reset state.
XIN Clock input Input
XOUT Clock output Output
_
E Enable output Output This pin functions as the enable signal output pin which indicates the access status in the internal
BYTE
External data
Input In the memory expansion mode or the microprocessor mode, this pin determines whether the
bus width
selection input
AVcc, Analog power Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
AVss source input
REF Reference Input This is reference voltage input pin for the A-D converter.
V
voltage input
0 – P07 I/O port P0 I/O In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so
P0
0 – P17 I/O port P1 I/O In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set
P1
0 – P27 I/O port P2 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
P2
0 – P33 I/O port P3 I/O In the single-chip mode, these pins have the same function as port P0. In the memory expansion
P3
0 – P47 I/O port P4 I/O In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
P4
0 – P57 I/O port P5 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also
P5
0 – P67 I/O port P6 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also
P6
0 – P77 I/O port P7 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins function as
P7
0 – P87 I/O port P8 I/O In addition to having the same functions as port P0 in the single-chip mode, these pins also
P8
expansion mode, and to Vcc for the microprocessor mode.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between X
IN and XOUT. When an external clock is used, the clock source should
be connected to the XIN pin, and the XOUT pin should be left open.
bus. In the memory expansion mode or the microprocessor mode, this pin functions as the RDE
signal output pin.
external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”
signal is input and an 8-bit width when “H” signal is input.
that each pin can be programmed for input or output. These ports are in the input mode when
reset.
In the memory expansion mode or the microprocessor mode, these pins output CS0 – CS4, RSMP
signals, and address (A16, A17).
to “L” in the memory expansion mode or the microprocessor mode and external data bus has a
16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When
the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output.
mode or the microprocessor mode, low-order data (D
(A0 – A7) is output .
mode or the microprocessor mode, WEL, WEH, ALE, and HLDA signals are output.
mode or the microprocessor mode, P40, P41 and P42 become HOLD and RDY input pins, and a
clock
φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip
mode. However, in the memory expansion mode, P42 can be selected as an I/O port.
function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3 ).
function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins
for timers B0 to B2. P67 also functions as a sub-clock φSUB output pin.
input pins for A-D converter. P7
7 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz)
P7
2 to P75 also function as I/O pins for UART2. Additionally, P76 and
oscillation circuit, respectively. When P7
a resonator or an oscillator between the both.
function as I/O pins for UART 0 and UART 1.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
___
___ ___ ____
0 – D7) is input/output or an address
___ ____ ____
____ ___
__ __
___ ___
6 and P77 are used as the XCOUT and XCIN pins, connect
4
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37735M4BXXXFP has the same fuanctions as the
M37735MHBXXXFP except for the memory allocation and the ROM
area modification function.
Refer to the section on the M37735MHBXXXFP.
MEMORY
The memory map is shown in Figure 1. The address space has a
capacity of 16 Mbytes and is allocated to addresses from 0
FFFFFF
16. The address space is divided by 64-Kbyte unit called bank.
The banks are numbered from 0
However, banks 10
16 – FF16 of the 7735 group cannot be accessed.
16 to FF16.
Built-in ROM, RAM and control registers for internal peripheral devices
are assigned to bank 0
The 32-Kbyte area from addresses 8000
ROM. Addresses FFD6
16.
16 to FFFF16 is the built-in
16 to FFFF16 are the RESET and interrupt
vector addresses and contain the interrupt vectors. Refer to the section
on interrupts for details.
The 2048-byte area allocated to addresses from 80
16 to 87F16 is the
built-in RAM. In addition to storing data, the RAM is used as stack
000000
16
Bank 0
16
00FFFF
16
010000
16
16 to
000000
00007F
000080
00087F
during a subroutine call or interrupts.
Peripheral devices such as I/O ports, A-D converter, serial I/O, timer,
and interrupt control registers are allocated to addresses from 0
7F
16.
Additionally, the internal ROM area can be modified by software. Refer
to the section on ROM area modification function for details.
A 256-byte direct page area can be allocated anywhere in bank 0
by using the direct page register (DPR). In the direct page addressing
mode, the memory in the direct page area can be accessed with two
words. Hence program steps can be reduced.
16
16
16
16
Internal RAM
2048 bytes
000000
00007F
16
Internal peripheral
devices
control registers
refer to Fig. 2 for
detail information
16
16 to
16
Bank 1
16
01FFFF
16
• • • • • • • • • • • • • • • • • • •
008000
16
FE0000
Bank FE
Bank FF
16
16
FEFFFF
16
FF0000
16
16
FFFFFF
16
00FFD6
00FFFF
Internal ROM
32 Kbytes
16
16
Notes 1. Internal ROM area can be modified. (Refer to the section on ROM area modification function.)
2. Banks 10
16
– FF16 cannot be accessed in the 7735 group.
Fig. 1 Memory map
00FFD6
00FFFE
Interrupt vector table
16
A-D/UART2 trans./rece.
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
/Key input
INT
1
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
16
RESET
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000000
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
000013
000014
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P8 direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
000021
000022
000023
000024
000025
000026
000027
000028
000029
00002A
00002B
00002C
00002D
00002E
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
Reserved area (Note)
Reserved area (Note)
A-D control register 0
A-D control register 1
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
UART 0 transmit/receive mode register
UART 0 baud rate register (BRG0)
UART 0 transmission buffer register
UART 0 transmit/receive control register 0
UART 0 transmit/receive control register 1
UART 0 receive buffer register
UART 1 transmit/receive mode register
UART 1 baud rate register (BRG1)
UART 1 transmission buffer register
UART 1 transmit/receive control register 0
UART 1 transmit/receive control register 1
UART 1 receive buffer register
Fig. 2 Location of internal peripheral devices and interrupt control registers
Address (Hexadecimal notation)
000040
000041
000042
Count start flag
One-shot start flag
000043
000044
Up-down flag
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
00005F
000060
000061
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
Watchdog timer register
Watchdog timer frequency selection flag
Reserved area (Note)
Memory allocation control register
UART 2 transmit/receive mode register
UART 2 baud rate register (BRG2)
UART 2 transmission buffer register
UART 2 transmit/receive control register 0
UART 2 transmit/receive control register 1
UART 2 receive buffer register
Oscillation circuit control register 0
Port function control register
Serial transmit control register
Oscillation circuit control register 1
A-D/UART 2 trans./rece. interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0
interrupt control register
INT1
interrupt control register
INT2
/Key input interrupt control register
Note. Do not write to this address.
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ROM AREA MODIFICATION FUNCTION
The internal ROM size and its address area of the M37735M4BXXXFP
can be modified by the memory allocation control register’s bit 0 shown
in Figure 3.
Figure 5 shows the memory allocation in which the internal ROM
size and its address area are modified.
Make sure to write data in the memory allocation control register as
the flow shown in Figure 4.
This ROM area modification function is valid in memory expansion
mode and single-chip mode.
Table 1 shows the relationship between memory allocation selection
76543210
ML
Note. Write to the memory allocation control register as the flow shown in Figure 4.
bits and address corresponding to chip-select signals CS0 and CS1.
When ordering a mask ROM, Mitsubishi Electric corp. produces the
mask ROM using the data within 32 Kbytes (addresses 008000
00FFFF
16). It is regardless of the selected ROM size (refer to MASK
ROM ORDER CONFIRMATION FORM.) Therefore, program “FF
to the addresses out of the selected ROM area in the EPROM which
you tender when ordering a mask ROM.
Address 00FFFF
16 of this microcomputer corresponds to the lowest
address of the EPROM which you tender.
0
Memory allocation control register
Address
63
16
Memory allocation selection bit
ROM size (ROM area)
0 : 32 Kbytes (addresses 008000
1 : 16 Kbytes (addresses 00C000
16
– 00FFFF16)
16
– 00FFFF16)
___ ___
16 –
16”
Fig. 3 Bit configuration of memory allocation control register
Writing data “5516” (LDM instruction)
Writing data “0016” or “0116” (LDM instruction)
• How to write in memory allocation control register
Fig. 4 How to write data in memory allocation control register
0
selection bit
ML
Next instruction
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
0
) = (0) (ML0) = (1)
(ML
ROM size : 32 kbytes ROM size : 16 Kbytes
000000
00007F
000080
00087F
008000
16
16
16
16
16
SFR
Internal RAM
2048 bytes
000000
00007F
000080
00087F
16
16
16
16
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
Internal RAM
2048 bytes
Internal ROM
00C000
00FFFF
010000
FFFFFF
32 Kbytes
16
16
16
00FFFF
010000
FFFFFF
16
16
16
16
Internal ROM
16 Kbytes
: External memory area
16
Note. Banks 10
to FF16 cannot be accessed in the 7735 Group.
Fig. 5 Memory allocation (modification of internal ROM area by memory allocation selection bit)
Table 1. Relationship between memory allocation selection bits and addresses corresponding to chip-select signals CS0 and CS1
Memory allocation select bit
ML0
0
1
Internal ROM area
00800016 – 00FFFF16
00C00016 – 00FFFF16
___
CS0
00088016 – 007FFF16
00088016 – 007FFF16
Access address
___ ___
___
CS1
01000016 – 03FFFF16
00800016 – 00BFFF16
01000016 – 03FFFF16
ADDRESSING MODES
The M37735M4BXXXFP has 28 powerful addressing modes. Refer
to the MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for the details of each addressing
mode.
MACHINE INSTRUCTION LIST
The M37735M4BXXXFP has 103 machine instructions. Refer to the
8
MITSUBISHI SEMICONDUCTORS DATA BOOK SINGLE-CHIP 16BIT MICROCOMPUTERS for details.
DATA REQUIRED FOR MASK ROM ORDERING
Please send the following data for mask orders.
(1) M37735M4BXXXFP mask ROM order confirmation form
(2) 80P6N mark specification form
(3) ROM data (EPROM 3 sets)
MITSUBISHI MICROCOMPUTERS
M37735M4BXXXFP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Conditions Ratings Unit
Vcc Power source voltage –0.3 to +7 V
AVcc Analog power source voltage –0.3 to +7 V
VI
Input voltage RESET, CNVss, BYTE –0.3 to +12 V
Input voltage P0
V
I
_____
0 – P07, P10 – P17, P20 – P27,
0 – P33, P40 – P47, P50 – P57,
P3
0 – P67, P70 – P77, P80 – P87,
P6
VREF, XIN
Output voltage
VO
P00 – P07, P10 – P17, P20 – P27,
0 – P33, P40 – P47, P50 – P57,
P3
0 – P67, P70 – P77, P80 – P87,
P6
_
XOUT, E
Pd Power dissipation Ta = 25 °C 300 mW
Topr Operating temperature –20 to +85 °C
stg Storage temperature –40 to +150 °C
T
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted)
Symbol Parameter
IN) : Operating 4.5 5.0 5.5
Vcc Power source voltage
AVcc Analog power source voltage Vcc V
Vss Power source voltage 0V
AVss Analog power source voltage 0 V
V
VIH
VIH
VIL
VIL
VIL
IH
High-level input voltage P0
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)
High-level input voltage P1
(in memory expansion mode and microprocessor mode)
Low-level input voltage P0
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode)
Low-level input voltage P1
(in memory expansion mode and microprocessor mode)
High-level peak output current P0
IOH(peak)
High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
IOH(avg)
P4
Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
IOL(peak)
IOL(peak)
Low-level peak output current P44 – P47, P50 – P53
Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
IOL(avg)
IOL(avg) Low-level average output current P44 – P47, P50 – P53 15 mA
f(XIN) Main-clock oscillation frequency (Note 4) 25 MHz
CIN) Sub-clock oscillation frequency 32.768 50 kHz
f(X
Notes 1. Average output current is the average value of a 100 ms interval.
2. The sum of I
the sum of I
the sum of I
the sum of I
3. Limits V
OL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
OH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
OL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and
OH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.
IH and VIL for XCIN are applied when the sub clock external input selection bit = “1”.
4. The maximum value of f(X
f(X
f(XIN) : Stopped, f(XCIN) = 32.768 kHz 2.7 5.5
0 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,
0 – P17, P20 – P27
0 – P07, P30 – P33, P40 – P47, P50 – P57, P60 – P67,
0 – P17, P20 – P27
0 – P07, P10 – P17, P20 – P27, P30 – P33,
0 – P47, P50 – P57, P60 – P67, P70 – P77,
P4
_____
_____
P80 – P87
0 – P47, P50 – P57, P60 – P67, P70 – P77,
P80 – P87
0 – P43, P54 – P57, P60 – P67, P70 – P77,
P4
P80 – P87
0 – P43, P54 – P57, P60 – P67, P70 – P77,
P4
P80 – P87
IN) = 12.5 MHz when the main clock division selection bit = “1”.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
–0.3 to Vcc + 0.3 V
–0.3 to Vcc + 0.3 V
Min. Typ. Max.
Limits
0.8 Vcc
0.8 Vcc
0.5 Vcc
0
0
0
0.16Vcc
Vcc
Vcc
Vcc
0.2Vcc
0.2Vcc
–10
–5
10
20
Unit
V
V
V
V
V
V
V
mA
mA
mA
mA
5
mA
9
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