Mitsubishi M37536E8SP Datasheet
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7536 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7536 Group has a USB, 8-bit timers, and an A-D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
Basic machine-language instructions....................................... 69
•
The minimum instruction execution time.......................... 0.34 µs
•
•
•
•
•
(at 6 MHz oscillation frequency for the shortest instruction)
Memory size
ROM..................................................................... 8K to 16K bytes
RAM ....................................................................256 to 384 bytes
Programmable I/O ports........................................................... 33
Interrupts ....................................................14 sources, 8 vectors
Timers ............................................................................ 8-bit ✕ 3
PIN CONFIGURATION (TOP VIEW)
P14/CNTR0
P15
P16
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
P4
P41
REF
V
RESET
CNVSS
Vcc
XIN
XOUT
VSS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Serial I/O1 ................................ used only for Low Speed in USB
•
Serial I/O2 ...................................................................... 8-bit ✕ 1
•
A-D converter ................................................ 10-bit ✕ 8 channels
•
Clock generating circuit ............................................. Built-in type
•
(connect to external ceramic resonator or quartz-crystal oscillator )
Watchdog timer ............................................................ 16-bit ✕ 1
•
Power source voltage
•
At 6 MHz X
...................................................................................4.1 to 5.5 V
Power dissipation ............................................ 30 mW (standard)
•
Operating temperature range ................................... –20 to 85 °C
•
IN oscillation frequency at ceramic resonator
APPLICATION
Input device for personal computer peripherals
42
41
40
M37536M4-XXXSP
M37536E8SP
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/SDATA
2/SCLK
P1
P1
1/TXD/D+
P10/RXD/DP07
P06
P0
5
P04
P03
P02
P01
P00
USBVREFOUT
P3
7/INT0
P3
6(LED6)/INT1
P35(LED5)
4(LED4)
P3
P3
3(LED3)
2(LED2)
P3
P31(LED1)
P30(LED0)
(USB/UART)
(Clock-synchronized)
Package type:42P4B
Fig. 1 Pin configuration of M37536M4-XXXSP,M37536E8SP
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR0
P15
P16
P20/AN0
1/AN1
P2
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
P40
P41
V
REF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
M37536RSS
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/SDATA
P12/SCLK
1/TXD/D+
P1
P10/RXD/DP07
P06
P05
P04
P03
P02
P01
P00
USBV
REFOUT
P37/INT0
6(LED6)/INT1
P3
P35(LED5)
4(LED4)
P3
P3
3(LED3)
P3
2(LED2)
P31(LED1)
P30(LED0)
Fig. 2 Pin configuration of M37536RSS
2
Outline 42S1M
FUNCTIONAL BLOCK
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
X
IN OUT
X
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
21
RESET
16
V
CC
18
17
CNV
SS
CNTR
0
P1(7)
P2(8)
P3(8)
19 20
V
REF
0
INT
0
USBV
REFOUT
INT
1
P4(2)
SI/O1(8)
USB(LS)
SI/O2(8)
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
I/O port P4
Key-on wakeup
Clock input
Clock output
Reset input
13 14 15
2427 25 23262829 22
857412 1011 9
30
3141242 3940
P0(8)
38 36 34 3237 35 33 31
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 42P4B)
Fig. 3 Functional block diagram
3
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
VREF
USBVREFOUT
CNVss
RESET
XIN
XOUT
P00–P07
P10/RxD/DP11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Name
Power source
Analog reference
voltage
USB reference
voltage output
CNVss
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function
•Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•7-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12, P13.
•When using the USB function, input level of ports P10 and
P11 becomes USB input level, and output level of them
becomes USB output level.
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P36, P37).
•CMOS 3-state output structure
•P30 to P36 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
Function expect a port function
•Key-input (key-on wake up
interrupt input) pins
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A-D converter
•Interrupt input pins
4
GROUP EXPANSION
Mitsubishi plans to expand the 7536 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Memory size
ROM/PROM size ..................................................8 K to 16 K bytes
RAM size................................................................256 to 384 bytes
Package
42P4B ................................................... 42-pin plastic molded SDIP
42SIM...................................... 42-pin shrink ceramic PIGGY BACK
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM size
(Byte)
16K
8K
M37536E8
M37536M4
0
128
256 384
RAM size
(Byte)
Note. Products under development: the development schedule and specification
may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37536M4-XXXSP
M37536E8SP
M37536RSS
(P) ROM size (bytes)
ROM size for User ()
8192 (8062)
16384 (16254)
RAM size
(bytes)
256
384
384
Package
42P4B
42P4B
42S1M
Remarks
Mask ROM version
One Time PROM version (blank)
Emulator MCU
5
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7536 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL and DIV instructions cannot be used.
The WIT and STP instructions can be used.
The central processing unit (CPU) has the six registers.
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 5 Structure of CPU mode register
b7 b0
CPU mode register
(CPUM: address 003B
After releasing reset
Wait until ceramic oscillator clock is
stabilized.
16
)
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
Not available
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “0” when read)
(Do not write “1” to these bits )
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
0 1 : f(φ) = f(X
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
IN
)/2 (High-speed mode)
IN
)/8 (Middle-speed mode)
IN
) (Double-speed mode)
Start with a built-in ring oscillator ( Note)
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Note. After releasing reset the operation starts by starting a ring oscillator automatically.
Do not use a ring oscillator at ordinary operation.
Fig. 6 Switching method of CPU mode register
6
Switch to other mode except a ring oscillator
(Select one of 1/1, 1/2, and 1/8)
Main routine
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
256
384
address
XXXX
013F16
01BF16
16
Zero page
The 256 bytes from addresses 0000
16 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF00
16 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
RAM
000016
004016
010016
XXXX
044016
YYYY16
ZZZZ16
SFR area
16
Reserved area
Not used
Reserved ROM area
(128 bytes)
Zero page
ROM area
ROM capacity
(bytes)
8192
16384
Fig. 7 Memory map diagram
address
YYYY
E00016
C00016
ROM
FF0016
address
16
ZZZZ
E08016
C08016
16
FFEC16
FFFE16
FFFF16
Interrupt vector area
Reserved ROM area
Special page
7
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
Port P0 (P0)
16
Port P0 direction register (P0D)
16
Port P1 (P1)
16
Port P1 direction register (P1D)
16
Port P2 (P2)
16
Port P2 direction register (P2D)
16
Port P3 (P3)
16
Port P3 direction register (P3D)
16
Port P4 (P4)
16
Port P4 direction register (P4D)
16
16
16
16
16
16
16
16
16
16
16
16
16
Pull-up control register (PULL)
16
Port P1P3 control register (P1P3C)
16
Transmit/Receive buffer register (TB/RB)
16
USB status register (USBSTS)/UART status register (UARTSTS)
16
Serial I/O1 control register (SIO1CON)
16
UART control register (UARTCON)
16
Baud rate generator (BRG)
16
USB data toggle synchronization register ( TRSYNC)
16
USB interrupt source discrimination register 1 (USBIR1)
16
USB interrupt source discrimination register 2 (USBIR2)
16
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
USB interrupt control register (USBICON)
16
USB transmit data byte number set register 0 (EP0BYTE)
16
USB transmit data byte number set register 1 (EP1BYTE)
16
USBPID control register 0 (EP0PID)
16
USBPID control register 1 (EP1PID)
16
USB address register (USBA)
16
USB sequence bit initialization register (INISQ1)
16
16
USB control register (USBCON)
Prescaler 12 (PRE12)
16
Timer 1 (T1)
16
Timer 2 (T2)
16
Timer X mode register
16
(TX)
(PREX)
Prescaler X
16
Timer X
16
Timer count source set register (TCSS)
16
16
Serial I/O2 control register (SIO2CON)
16
Serial I/O2 register (SIO2)
16
16
16
A-D control register (ADCON)
16
A-D conversion register (low-order) (ADL)
16
A-D conversion register (high-order) (ADH)
16
16
MISRG
16
Watchdog timer control register (WDTCON)
16
Interrupt edge selection register
16
CPU mode register (CPUM)
16
Interrupt request register 1 (IREQ1)
16
16
Interrupt control register 1 (ICON1)
16
16
(TM)
(INTEDGE)
Fig. 8 Memory map of special function register (SFR)
8
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds
to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
b7 b0
[Pull-up control] PULL
By setting the pull-up control register (address 001616), ports P0 and
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 001716), a CMOS
input level or a TTL input level can be selected for ports P10, P12,
P13, P35, P36 and P37 by program.
Pull-up control register
16
(PULL: address 0016
P00 pull-up control bit
P0
1
pull-up control bit
P0
2
, P03 pull-up control bit
P0
4
– P07 pull-up control bit
P3
0
– P33 pull-up control bit
P3
4
pull-up control bit
P3
5
, P36 pull-up control bit
P3
7
pull-up control bit
)
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 9 Structure of pull-up control register
b7 b0
Fig. 10 Structure of port P1P3 control register
0: Pull-up off
1: Pull-up on
Initial value: FF
Port P1P3 control register
(P1P3C: address 0017
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
6/INT1 input level selection bit
P3
0 : CMOS level
1 : TTL level
P1
0,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
16
16)
9
Table 3 I/O port function table
Pin
P00–P07
P10/RxD/DP11/TxD/D+
P12/SCLK
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL level.
Name
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O individual
bits
•CMOS compatible input level
•CMOS 3-state output
•USB input/output level when
selecting USB function
•CMOS compatible input level
•CMOS 3-state output
(Note)
I/O format
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A-D conversion input
External interrupt input
Related SFRs
Pull-up control register
Serial I/O1 control
register
Serial I/O2 control
register
Timer X mode register
A-D control register
Interrupt edge selection
register
Diagram No.Input/output
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(7)
(8)
(9)
(10)
10
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0
Pull-up control
Direction
register
Data bus
(3) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
Port latch
To key input interrupt
1
P-channel output disable bit
Transmit enable bit
Direction
register
Port latch
generating circuit
(2) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
0
Receive enable bit
Direction
register
Port latch
-
+
Serial I/O1 input
D- input
D- output
USB output enable
(internal signal)
USB differential input
0
,P12,P13 input
P1
level selection bit
Serial I/O1 output
D+ output
USB output enable
(internal signal)
(4) Port P1
Data bus
＊P1
2
S
CLK
pin selection bit
Direction
register
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 11 Block diagram of ports (1)
D+ input
0
,P12,P13 input
P1
level selection bit
(5) Port P1
Signals during the
S
DATA
S
Data bus
3
DATA
output action
pin selection bit
Direction
register
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
DATA
pin
S
selection bit
P1
0
,P12,P13 input
level selection bit
11
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P1
4
Data bus
Pulse output mode
(8) Ports P30 – P3
Data bus
Direction
register
Port latch
Timer output
5
Pull-up
Direction
register
Port latch
CNTR
0
interrupt input
control
(7) Ports P20 – P2
Data bus
(9) Port P36, P3
Data bus
7
Port latch
7
Direction
register
Port latch
Direction
register
A-D conversion input
Analog input pin selection bit
control
Pull-up
7
/INT0 input
P3
level selection bit
(10) Ports P1
Data bus
5, P16
, P4
Direction
register
Port latch
Fig. 12 Block diagram of ports (2)
0, P41
interrupt input
INT
₎
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
P1
When the TTL level is selected, there is no hysteresis characteristics.
₎
12
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR0 and A-D interrupt sources
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT1 interrupt sources
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 4 Interrupt vector address and priority
Interrupt source
Reset (Note 2)
UART receive
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
INT1
INT0
Timer X
Key-on wake-up
Timer 1
Timer 2
Serial I/O2
CNTR0
A-D conversion
BRK instruction
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Priority
Vector addresses (Note 1)
High-order
FFFD16
1
FFFB16
2
FFF916
3
FFF716
4
FFF516
5
FFF316
6
FFF116
7
FFEF16
8
FFED16
9
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
of INT1 input
At detection of either rising or falling edge
of INT0 input
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR0 input
At completion of A-D conversion
At BRK instruction execution
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
selectable)
Non-maskable software interrupt
13
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
MITSUBISHI MICROCOMPUTERS
7536 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 13 Interrupt control
b7 b0
BRK instruction
Reset
Interrupt edge selection register
(INTEDGE : address 003A
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O1 or INT1 interrupt selection bit
0 : Serial I/O1
1 : INT
Timer X or key-on wake up interrupt selection bit
0 : Timer X
1 : Key-on wake up
Timer 2 or serial I/O2 interrupt selection bit
0 : Timer 2
1 : Serial I/O2
CNTR
0 : CNTR
1 : AD converter
1
0
or AD converter interrupt selection bit
16
)
0
Interrupt request
b7 b0
b7 b0
Interrupt request register 1
(IREQ1 : address 003C
UART receive/USB IN token interrupt request bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt request bit
INT
0
Timer X or key-on wake up interrupt request bit
Timer 1 interrupt request bit
Timer 2 or serial I/O2 interrupt request bit
CNTR
Not used (returns “0” when read)
Interrupt control register 1
(ICON1 : address 003E16)
UART receive/USB IN token interrupt enable bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt enable bit
INT
0
Timer X or key-on wake up interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 or serial I/O2 interrupt enable bit
CNTR
Not used (returns “0” when read)
(Do not write “1” to this bit)
Fig. 14 Structure of interrupt-related registers
14
16
)
interrupt request bit
0
or AD converter interrupt request bit
interrupt enable bit
0
or AD converter interrupt enable bit
1
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : Interrupts disabled
1 : Interrupts enabled
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