PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M37280MF–XXXSP and M37280MK-XXXSP are single-chip
microcomputers designed with CMOS silicon gate technology. They
have a OSD function and a data slicer function, so it is useful for a
channel selection system for TV with a closed caption decoder.
The feautures of the M37280EKSP is similar to those of the
M37280MK-XXXSP except that the chip has a built-in PROM which
can be written electrically . The difference between M37280MK-XXXSP
and M37280MF-XXXSP are the ROM size and RAM size. Accordingly, the following descriptions will be for the M37280MK-XXXSP.
2. FEATURES
●Number of basic instructions .................................................... 71
●Memory size
ROM ..................... 60K bytes (M37280MF-XXXSP)
80K bytes (M37280MK-XXXSP,
M37280EKSP)
RAM .....................1024 bytes (M37280MF-XXXSP)
1472 bytes (M37280MK-XXXSP,
M37280EKSP)
ROM correction memory............................ 64 bytes
●Minimum instruction execution time
.........................................0.5 µs (at 8 MHz oscillation frequency)
●Power source voltage ................................................. 5 V ± 10 %
●Subroutine nesting ............................................. 128 levels (Max.)
●Interrupts ....................................................... 19 types, 16 vectors
●8-bit timers .................................................................................. 6
●Programmable I/O ports (Ports P0, P1, P2, P30, P31) ............. 26
●Input ports (Ports P40–P46, P63, P64, P70–P72) ...................... 12
●Output ports (Ports P32, P47, P5, P60–P62, P65–P67) .............. 16
●12 V withstand ports ................................................................... 8
●LED drive ports ........................................................................... 2
●Serial I/O ............................................................8-bit ✕ 1 channel
●Multi-master I2C-BUS interface .............................. 1 (2 systems)
●A-D converter (8-bit resolution)....................................8 channels
●PWM output circuit......................................................... 8-bit ✕ 8
●Power dissipation
In high-speed mode .........................................................165 mW
(at VCC = 5.5V, 8 MHz oscillation frequency, CRT on, and Data
slicer on)
In low-speed mode .........................................................0.33 mW
(at VCC = 5.5V, 32 kHz oscillation frequency)
●ROM correction function
●Closed caption data slicer
●OSD function
Display characters .... 32 characters ✕ 16 lines + RAM font (1 character)
Kinds of characters ......... 510 kinds + 62 kinds +1 kind
(Coloring unit) (a character) (a dot) (a dot)
Triple layer function.......................................................................
2 layers selected from CC/CDOSD/OSD mode + RAM font layer
Character display area.............. CC/CDOSD mode: 16 ✕ 26 dots
Kinds of character sizes.................... CC mode/RAM font: 4 kinds
Kinds of character colors ..............................................................
64 colors (4 adjustment levels for each R, G, B)
Coloring unit............ dot, character, character background, raster
Blanking output OUT1, OUT2
Display position
Horizontal: 256 levels Vertical :1024 levels
(RAM font can be set independently)
Attribute ........................................................................................
CC mode: smooth italic, underline, flash, automatic solid space
OSD mode: border, shadow
Window/Blank function
(CC/OSD mode)(CDOSD mode)(RAM font)
OSD mode/RAM font: 16 ✕ 20 dots
OSD/CDOSD mode: 14 kinds
3. APPLICA TION
TV with a closed caption decoder
4. PIN CONFIGURATION
Refer to page 3.
5. BLOCK DIAGRAM
Refer to page 4.
6. PERFORMANCE OVERVIEW
Refer to pages 5 and 6.
7. PIN DESCRIPTION
Refer to pages 7 to 11.
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
TABLE OF CONTENTS
8. PIN CONFIGURATION ................................................................................................................................................................................... 3
9. FUNCTIONAL BLOCK DIAGRAM .................................................................................................................................................................. 4
10. PERFORMANCE OVERVIEW...................................................................................................................................................................... 5
11. PIN DESCRIPTION....................................................................................................................................................................................... 7
12. FUNCTIONAL DESCRIPTION.................................................................................................................................................................... 12
12.1 CENTRAL PROCESSING UNIT (CPU) ........................................................................................................................................... 12
12.2 MEMORY ......................................................................................................................................................................................... 13
12.3 INTERRUPTS .................................................................................................................................................................................. 21
12.4 TIMERS............................................................................................................................................................................................ 26
12.5 SERIAL I/O....................................................................................................................................................................................... 30
12.6 MULTI-MASTER I2C-BUS INTERFACE .......................................................................................................................................... 33
12.7 PWM OUTPUT CIRCUIT ................................................................................................................................................................. 46
12.8 A-D CONVERTER............................................................................................................................................................................ 50
12.9 ROM CORRECTION FUNCTION .................................................................................................................................................... 54
12.10 DATA SLICER ................................................................................................................................................................................ 55
12.11 OSD FUNCTIONS.......................................................................................................................................................................... 66
13. SOFTWARE RUNAWAY DETECT FUNCTION ......................................................................................................................................... 117
14. RESET CIRCUIT........................................................................................................................................................................................118
15. CLOCK GENERATING CIRCUIT............................................................................................................................................................... 119
15.1 OSCILLATION CONTROL..............................................................................................................................................................119
16. DISPLAY OSCILLATION CIRCUIT ........................................................................................................................................................... 122
17. AUTO-CLEAR CIRCUIT............................................................................................................................................................................ 122
18. ADDRESSING MODE ............................................................................................................................................................................... 122
19. MACHINE INSTRUCTIONS ..................................................................................................................................................................... 122
20. PROGRAMMING NOTES......................................................................................................................................................................... 122
21. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................ 123
22. RECOMMENDED OPERATING CONDITIONS........................................................................................................................................ 123
23. ELECTRIC CHARACTERISTICS ............................................................................................................................................................. 124
24. ANALOG R, G, B OUTPUT CHARACTERISTICS.................................................................................................................................... 126
25. A-D CONVERETER CHARACTERISTICS ............................................................................................................................................... 126
26. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS .................................................................................................................... 127
27. DATA REQUIRED FOR MASK ORDERS ................................................................................................................................................. 128
28. PROM PROGRAMMING METHOD.......................................................................................................................................................... 128
29. MASK CONFIRMATION FORM................................................................................................................................................................ 129
30. MARK SPECIFICATION FORM................................................................................................................................................................ 135
31. APPENDIX ................................................................................................................................................................................................ 136
32. PACKAGE OUTLINE ................................................................................................................................................................................ 176
M37280EKSP
Rev. 1.0
2
PRELIMINARY
7
4
Notice: This is not a final specification.
Some paramentic limits are subject to change.
8. PIN CONFIGURATION
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
HSYNC
VSYNC
P40AD4
1/INT2
P4
P42/TIM2
P43/TIM3
P24/AD3
5/AD2
P2
P26/AD1
P27/AD5
P00/PWM
P50/PWM
P01/PWM5
P47
P02/PWM6
P51
P17/SIN/R0
P32
P44/INT1
P56
P45/SOUT
P57
P46/SCLK
AVCC
HLF/AD6
P72/(SIN)
P71/VHOLD
P70/CVIN
CNVSS
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
M37280EKSP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P52/R/R1
64
P53/G/G1
63
4/B/B1
P5
62
P55/OUT1
61
P04/PWM0
60
P05/PWM1
59
0
P6
58
57
P06/PWM2
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P61
P07/PWM3
P62
P20
P21
P22
P23
P10/OUT2
P65
P1
1/SCL1
P66
P12/SCL2
P67
P1
3/SDA1
P14/SDA2
5/G0
P1
P16/INT3/B0
P03/PWM7
P30/AD7
P31/AD8
RESET
4/OSC2/XCOUT
P6
P63/OSC1/XCIN
VCC
M37280MF-XXXSP, M37280MK-XXXSP,
Fig. 8.1 Pin Configuration (Top View)
Rev. 1.0
Outline 64P4B
3
PRELIMINARY
Clock input
Clock output
XINX
OUT
Reset input
AVCCVCCVSSCNVSSPins for data slicer
Clock output for OSD/
sub-clock output
Input ports P6
3
, P6
4
OSC1
OSC2
Clock input for
OSD/sub-clock input
P1 (8)
Multi-master
I
2
C-BUS interface
P3 (3)
SDA1
SCL2
SCL1
SDA2
P2 (8)
P0 (8)
P4 (8)
S
IN
S
CLK
S
OUT
SI/O (8)
P6 (8)
INT1
INT2
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
P5 (8)
OUT1
B
G
R
H
SYNC
V
SYNC
A-D
converter
8-bit
PWM circuit
8-bit
arithmetic
and
logical unit
Accumulator
A (8)
Timer 6
T6 (8)
Timer 5
T5 (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
TIM2
Data slicer
Instruction
register (8)
Instruction
decoder
Control signal
OSD circuit
Processor
status
register
PS (8)
Stack
pointer
S (8)
Index
register
Y (8)
Index
register
X (8)
ROM
Program
counter
PC
L
(8)
Progam
counter
PC
H
(8)
RAM
Data bus
Clock
generating
circuit
303136
RESET
243332
29
CV
IN
282725
26
V
HOLD
RVCO
HLF
34
35
Address bus
361740414243454749109875051525355575960391513112321196543616263642
1
I/O ports
P3
0
, P3
1
I/O port P1
I/O port P2
I/O port P0
Input ports P4
0
–P4
6
Output port P5
Sync
signal input
Output port P4
7
20
2216125658
44
Output ports
P6
0
–P6
2
, P6
5
–P4
7
14
18
Output port
P3
2
INT3
PWM7
374854
46
Input ports P7
0 –
P7
2
A-D converter
SI/O
P7 (3)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
9. FUNCTIONAL BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Fig. 9.1 Functional Block Diagram of M37280
4
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
10. PERFORMANCE OVERVIEW
Table 10.1 Performance Overview
Parameter
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output
ports
Serial I/O
Multi-master I2C-BUS interface
A-D converter
PWM output circuit
Timers
Subroutine nesting
Interrupt
Clock generating circuit
Data slicer
ROM
M37280MF-XXXSP
M37280MK-XXXSP, M37280EKSP
RAM
M37280MF-XXXSP
M37280MK-XXXSP, M37280EKSP
ROM correction memory
OSD ROM (character font)
OSD ROM (color dot font)
OSD RAM (SPRITE)
OSD RAM (character)
P00–P02, P04–P07
P03
P10, P15–P17
P11–P14
P2
P30, P31
P32
P40–P44
P45, P46
P47
P50, P51, P56, P57
P52–P55
P60–P62, P65–P67
P63
P64
P70–P72
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
60K bytes
80K bytes
1024 bytes
1472 bytes
64 bytes
20400 bytes
9672 bytes
120 bytes
1536 bytes
I/O
I/O
I/O
I/O
I/O
I/O
Output
Input
Input
Output
Output
Output
Output
Input
Input
Input
7-bit ✕ 1 (N-channel open-drain output structure, can be used as 8-bit PWM
output pins)
1-bit ✕ 1 (CMOS input/output structure, can be used as 14-bit PWM output
pin)
4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,
INT input pin, serial input pin)
4-bit ✕ 1 (N-channel open-drain output structure, can be used as multimaster I2C-BUS interface)
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)
2-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)
1-bit ✕ 1 (N-channel open-drain output structure)
5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock input
pins)
2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,
can be used as serial I/O pins)
1-bit ✕ 1 (N-channel open-drain output structure)
4-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pin)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins)
6-bit ✕ 1 (N-channel open-drain output structure)
1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin)
1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as
sub-clock output pin, OSD clock output pin)
3-bit ✕ 1 (can be used as data slicer input/output, serial input pin)
8-bit ✕ 1
1 (2 systems)
8 channels (8-bit resolution)
8-bit ✕ 8
8-bit timer ✕ 6
128 levels (maximum)
<19 types>
External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,
OSD interrupt ✕ 1, Multi-master I2C-BUS interface interrupt ✕ 1,
Data slicer interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, SPRITE OSD interrupt
✕ 1, VSYNC interrupt ✕ 1, A-D conversion interrupt ✕ 1, BRK instruction
interrupt ✕ 1
2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator)
Built in
Rev. 1.0
5
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Table 10.2 Performance Overview
Parameter
OSD function
Power source voltage
Power
dissipation
Operating temperature range
Device structure
Package
In high-speed
mode
In low-speed
mode
In stop mode
Number of display characters
Character display area
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal,
vertical)
OSD ON
(Analog output)
OSD ON
(Digital output)
OSD OFF
OSD OFF
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Functions
Data slicer
ON
Data slicer
OFF
Data slicer OFF
Data slicer
OFF
32 characters ✕ 16 lines
CC mode: 16 ✕ 26 dots (dot structure: 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
EXOSD mode: 16 ✕ 26 dots
SPRITE display: 16 ✕ 20 dots
CC/OSD mode: 510 kinds
CDOSD mode: 62 kinds
SPRITE display: 1 kind
CC mode: 2 kinds
OSD/CDOSD mode: 14 kinds
SPRITE display: 8 kinds
CC/CDOSD mode: 8 kinds (R, G, B, OUT1, OUT2))
OSD mode: 15 kinds (R, G, B, OUT1, OUT2)
SPRITE display: 8 kinds (R, G, B, OUT1)
256 levels (horizontal) ✕ 1024 levels (vertical)
SPRITE display: 2048 ✕ 1024
5V ± 10%
275 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz)
165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 27 MHz )
82.5 mW typ. ( at oscillation frequency f(XIN) = 8 MHz)
0.33 mW typ. ( at oscillation frequency f(XCIN) = 32 kHz, f(XIN) = stop)
0.055 mW ( maximum )
–10 °C to 70 °C
CMOS silicon gate process
64-pin shrink plastic molded DIP
Rev. 1.0
6
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
11. PIN DESCRIPTION
Table 11.1 Pin Description
Pin Name Functions
VCC,
AVCC,
VSS
CNVSS
RESET
XIN
XOUT
P00/
PWM4–
P02/PWM6,
P03/PWM7,
P04/
PWM0–
P07/PWM3
P10/OUT2,
P11/SCL1,
P12/SCL2,
P13/SDA1,
P14/SDA2,
P15/G0,
P16/INT3/
B0,
P17/SIN/R0
P20–P23
P24/AD3–
P26/AD1,
P27/AD5
P30/AD7,
P31/AD8
P32
P40/AD4,
P41/INT2,
P42/TIM2,
P43/TIM3,
P44/INT1,
P45/SOUT,
P46/SCLK
P47
Power source
CNVSS
Reset input
Clock input
Clock output
I/O port P0
8-bit PWM output
I/O port P1
OSD output
Multi-master
I2C-BUS interface
External interrupt
input
Serial I/O data
input
I/O port P2
Analog input
I/O port P3
Analog input
Output port P3
Input port P4
Analog input
External interrupt
input
External clock input
Serial I/O data
output
Serial I/O
synchronous clock
input/output
Output port P4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Input/
Output
Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS.
Input
Input
Input
Output
I/O
Output
I/O
Output
Output
Input
Input
I/O
Input
I/O
Input
Output
Input
Input
Input
Input
Output
I/O
Output
Connected to VSS.
To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT.
If an external clock is used, the clock source should be connected to the XIN pin and the
XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output. See
notes at end of Table for full details of port P0 functions.
Pins P00–P03 and P04–P07 are also used as 8-bit PWM output pins PWM4–PWM7 and
PWM0–PWM3 respectively. The output structure of PWM0–PWM6 is N-channel open-drain
output. And the output structure of PWM7 is CMOS output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain
output.
Pin P10, P15–P17 are also used as OSD output pins OUT2, G0, B0, R0, respectively. The
output structure is CMOS output.
Pin P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I2C-BUS interface is used. The output structure is N-channel open-drain output.
Pin P16 is also used as extemal interrupt input pin INT3.
Pin P17 is also used as serial I/O data input pin SIN.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P24–P26, P27 are also used as analog input pins AD3–AD1, AD5 respectively.
Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0. The
output structure is CMOS output.
Pins P30, P31 are also used as analog input pins AD7, AD8 respectively.
Ports P32 is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P40–P46 are a 7-bit input port.
Pin P40 is also used as analog input pin AD4.
Pins P41, P44 are also used as external interrupt input pins INT2, INT1.
Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively.
Pin P45 is used as serial I/O data output pin SOUT. The output structure is N-channel open-
drain output.
Pin P46 is used as serial I/O synchronous clock input/output pin SCLK. The output structure
is N-channel open-drain output.
Port P47 is a 1-bit output port. The output structure is N-channel open-drain output.
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Rev. 1.0
7
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Table 11.2 Pin Description (continued)
Pin Name Functions
P50/PWM7,
P51,
P52/R/R1,
P53/G/G1,
P54/B/B1,
P55/OUT1,
P56, P5
P60–P62,
P65–P67
P63/OSC1/
XCIN,
P64/OSC2/
XCOUT
P70/CVIN,
P71/VHOLD,
P72/(SIN)
HLF/AD6
HSYNC
VSYNC
Output port P5
PWM output
OSD output
7
Output port P6
Input port P6
Clock input for OSD
Clock output for OSD
Sub-clock output
Sub-clock input
Input port P7
Input for data
slicer
Serial I/O data input
Analog input
HSYNC input
VSYNC input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Input/
Output
Output
Output
Output
Output
Input
Input
Output
Output
Input
Input
Input
Input
Input
Input
Input
Port P5 is a 4-bit output port. The output structure of P50, P51, P56 and P57 is N-channel
open-drain output, that of P52–P55 is CMOS output.
Pin P50 is also used as 8-bit PWM output pin PWM7. The output structure is N-channel
open-drain output.
Pins P52–P55 are also used as OSD output pins R/R1, G/G1, B/B1, OUT1 respectively. At
R, G, B output, the output structure is analog output. At R1, G1, B1 and OUT1 output, the
output structure is CMOS output.
Ports P60–P62 and P65–P67 are 6-bit output ports. The output structure is N-channel opendrain output.
Ports P63 and P64 are 2-bit input port.
Pin P63 is also used as OSD clock input pin OSC1.
Pin P64 is also used as OSD clock output pin OSC2. The output structure is CMOS output.
Pin P64 is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
Pin P63 is also used as sub-clock input pin XCIN.
Ports P70–P72 are 3-bit input port.
Pins P70, P71 are also used as data slicer input pins CVIN, VHOLD respectively . When using
data slicer, input composite video signal through a capacitor. Connect a capacitor between
VHOLD and VSS.
Pins P72 is also used as serial I/O data input pin SIN.
When using data slicer , connect a filter using of a capacitor and a resistor between HLF and
VSS.
This is an analog input pin AD6 .
This is a horizontal synchronous signal input for OSD.
This is a vertical synchronous signal input for OSD.
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Note : As shown in the memory map (Figure 12.2.1), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register
(address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register
are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port
latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previouslyoutput value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float,
so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Rev. 1.0
8
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Ports P03, P10, P15–P17, P2, P30, P31
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
Ports P0
Data bus
0–P02, P04–P07
Direction register
Port latch
Direction register
Port latch
CMOS output
Ports P03, P10, P15–P17,
P2, P3
0, P31
Note : Each port is also used as follows :
P0
0 : PWM7
P1
0 : OUT2
P1
5 : G0
P1
6 : INT3/B0
P1
7 : SIN/R0
P2
4–P26 : AD3–AD1
P2
7 : AD5
P3
0 : AD7
P3
1 : AD8
N-channel open-drain output
0–P02, P04–P07
Ports P0
Note : Each port is also used as follows :
P0
0–P02 : PWM4–PWM6
P0
4–P07 : PWM0–PWM3
Ports P11–P14
Data bus
Fig. 11.1 I/O Pin Block Diagram (1)
Rev. 1.0
Direction register
Port latch
N-channel open-drain output
Port P11-P14
Note : Each port is also used as follows :
P1
1 : SCL1
P1
2 : SCL2
P1
3 : SDA1
P1
4 : SDA2
9
PRELIMINARY
t
t
Notice: This is not a final specification.
Some paramentic limits are subject to change.
S
OUT
, S
CLK
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
H
SYNC
Ports P4
, V
SYNC
Internal circui
0
–P4
4
Direction register
Port P5
5
Schmidt input
SYNC, VSYNC
H
Internal circui
Input
Ports P40–P44
Note : Each port is also used as below :
P4
0 : AD4
P4
1 : INT2
P4
2 : TIM2
P4
3 : TIM3
P4
4 : INT1
N-channel open-drain output
Ports P45, P46
Note : Each pin is also used
as follows :
P4
5 : SOUT
P46 : SCLK
CMOS output
Port P5
5
Note : Port P55 is also used
as pin OUT1.
Data bus
Ports P32, P47, P51, P56, P57,
P6
Port P5
0
–P62, P65–P6
Data bus
0
Data bus
7
Ports latch
Ports latch
N-chanel open drain output
Ports P3
2, P47, P51, P56, P57,
P6
0–P62, P65–P67
N-chanel open drain output
Port P5
0
Note : Port P50 is also used
as pin PWM7.
Fig. 11.2 I/O Pin Block Diagram (2)
10
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Ports P52–P5
Fig. 11.3 I/O Pin Block Diagram (3)
4
Internal circuit
Output
Ports P5
2–P54
Note : Each port is also used
as below :
P5
2 : R/R1
P5
3 : G/G1
P5
4 : B/B1
Rev. 1.0
11
PRELIMINARY
0
B
After reset
W
2
4
0
e
s
(CM0, CM1)
bit (CM2) (See note)
age
00516
0
WRWRWRWRW
selection bit (CM5)
GH d
e
7
0
W
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12. FUNCTIONAL DESCRIPTION
12.1. CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6b5b4b3b2b1b
1
1
CPU mode register (CM) [Address 00FB16]
Nam
Processor mode bits
0, 1
Stack page selection
3,
Fix these bits to “1.”
12.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
Function
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
0: 0 page
1: 1 p
R
R
1
1
Fig. 12.1.1 CPU Mode Register
XCOUT drivability
Main Clock (XIN–XOUT)
stop bit
(CM6)
Internal system clock
selection bit
(CM7)
Note: This bit is set to “1” after the reset release.
0: LOW drive
1: HI
0: Oscillating
1: Stopped
0: XIN–XOUT selected
(high-speed mode)
1: X
CIN–XCOUT selected
(low-speed mode)
riv
R
12
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.2 MEMORY
12.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
12.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
12.2.3 ROM
The M37280MF-XXXSP has 60K-byte program area. The M37280MK
-XXXSP has 56K-byte program area and 24K-byte data-dedicated
area. For the M37280EKSP, the two area (60K, 24K + 56K) can be
swithed each other by setting the bank control register.
12.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
12.2.5 OSD ROM
ROM for display is used for storing character data.
0000
16
00BF
16
00C0
RAM
(1472 bytes)
for
M37280MK-XXXSP
and M37280EKSP
OSD RAM (SPRITE)
OSD RAM (character)
RAM
(1024 bytes)
for
M37280MF-
XXXSP
(120 bytes)
(See note 1)
(1536 bytes)
(See note 2)
00FF
0100
0200
0258
02C0
02FF
0300
053F
06FF
0700
07A7
0800
0FFF
1000
16
SFR1 area
16
16
16
SFR2 area
16
Not used
16
16
16
16
Not used
16
16
16
Not used
16
16
16
12.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
12.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
12.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
12.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
10000
16
Not used
10800
157FF
18000
1ACFF
16
16
Not used
16
16
Zero page
OSD ROM
(character font)
(20400 bytes)
ROM correction memory (64 bytes)
Block 1 : addresses 02C0
Block 2 : addresses 02E0
16 to
02DF
16 to
02FF
OSD ROM
(color dot font)
(9672 bytes)
16
16
Fig. 12.2.1 Memory Map
Rev. 1.0
ROM
(60K bytes)
FF00
FFDE
FFFF
16
16
16
Interrupt vector area
1B000
Expansion ROM
(20K bytes)
for
M37280MK-XXXSP
Special page
Notes 1: Refer to Table 12.11.3 OSD RAM (SPRITE).
and M37280EKSP
2: Refer to Tables 12.11.4 and 2.11.5 OSD RAM (character).
1C000
1D000
1E000
1F000
1FFFF
Not used
16
Bank 11
16
Bank 12
16
Bank 13
16
Bank 14
16
Bank 15
16
13
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.2.10 Expansion ROM (only M37280MKXXXSP/M37280EKSP)
The M37280MK-XXXSP/M37280EKSP can use 5-bank (total 20K
bytes) expansion ROM (4K bytes each bank) by setting the bank
register.
The expansion ROM is assigned to address 1B00016 to 1FFFF16.
The contents of each bank in the expansion ROM are read by setting
the bank register and accessing addresses 100016 to 1FFF16. As the
expansion ROM is not programmable, use it as data-dedicated area.
When using the expansion ROM area, the internal ROM at addresses
100016 to 1FFF16 (extra area) is not also programmable.
Notes 1: When using the expansion ROM (BK7 = “1”), the ROM correction
function do not operate for addresses 1000
2:When using the emulator MCU (M37280ERSS), as addresses 1000
to FFFF16 can be emulated by setting bit 7 of the bank control register to “0,” the expansion ROM cannot be used. Addresses 2000
FFFF
16 can be emulated by setting it to “1.” The data in specified
area by the bank selection bits can be read by accessing addresses
1000
16 to 1FFF16.
3:When using the emulator MCU, the expansion ROM and the extra
area cannot be emulated by setting bit 7 of the bank control register
to “1.” Therefore, write the data to this area before using.
4:For the M37280MK-XXXSP, fix bit 7 of the bank control register to
“1.” For M37280MF-XXXSP, fix the address 00ED
16 to 1FFF16.
16 to
16 to “0016.”
16
Bank Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Fig. 12.2.2 Bank Control Register
Bank control register (BK) [Address 00ED
B Name Functions
0
Bank
to
selection bits
3
(BK0 to BK3)
Fix these bits to “0”.
4, 5
6, 7 Bank control
bits
(BK6, BK7)
Bank number is selected (bank 11 to 15)
Bank ROM Address 1000
b6
b7
0
✕
10
11
Not used
Used
Used
access
Read out from extra area
(programmable)
Read out the data
from area specified by
the bank selection bits
Read out from extra area
(data-dedicated)
16]
16 level
After reset R
0RW
0RW
0RW
W
14
Rev. 1.0
PRELIMINARY
)
)
)
(P1)
)
)
)
)
)
r
)
)
)
)
)
)
(P7)
(
)
(
)
OUT1
OUT2
OC16
OC17
OC14
OC15
OC12
OC13
OC10
OC11
BC10
BC11
BC12
BC13
BC14
BC15
BC16
BC20
BC21
BC22
BC23
BC24
BC25
BC26
BC30
BC31
BC32
BC33
BC34
BC35
BC36
BC40
BC41
BC42
BC43
BC44
BC45
BC46
BC50
BC51
BC52
BC53
BC54
BC55
BC56
BC60
BC61
BC62
BC63
BC64
BC65
BC66
BC70
BC71
BC72
BC73
BC74
BC75
BC76
BC80
BC81
BC82
BC83
BC84
BC85
BC86
BC90
BC91
BC92
BC93
BC94
BC95
BC96
BC100
BC101
BC102
BC103
BC104
BC105
BC106
BC110
BC111
BC112
BC113
BC114
BC115
BC116
BC120
BC121
BC122
BC123
BC124
BC125
BC126
HP16
HP17
HP14
HP15
HP12
HP13
HP10
HP11
T3CS
BC130
BC131
BC132
BC133
BC134
BC135
BC136
BC140
BC141
BC142
BC143
BC144
BC145
BC146
BC150
BC151
BC152
BC153
BC154
BC155
BC156
BC160
BC161
BC162
BC163
BC164
BC165
BC166
P6IM
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
■ SFR1 area (addresses C016 to DF16)
Bit allocation
:
Name
:
: No function bit
: Fix to this bit to “0”
0
: Fix to this bit to “1”
1
Address
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
Registe
Port P0 (P0
Port P0 direction register (D0
Port P1
Port P1 direction register (D1
Port P2 (P2
Port P2 direction register (D2
Port P3 (P3
Port P3 direction register (D3
Port P4 (P4
Port P4 direction register (D4
Port P5 (P5
OSD port control register (PF
Port P6 (P6
Port P7
OSD control register 1 (OC 1
Horizontal position register (HP
Block control register 1 (BC1)
Block control register 2 (BC2)
Block control register 3 (BC
Block control register 4 (BC
Block control register 5 (BC
Block control register 6 (BC
Block control register 7 (BC
Block control register 8 (BC8)
Block control register 9 (BC
Block control register 10 (BC
Block control register 11 (BC
Block control register 12 (BC
Block control register 13 (BC13)
Block control register 14 (BC
Block control register 15 (BC
Block control register 16 (BC
)
3
)
4
)
5
)
6
)
7
)
9
10
11
12
14
15
16
b7 b0 b7 b0
0
)
)
)
)
)
)
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
State immediately after reset
: “0” immediately after reset
Function bit
do not write to “1”
do not write to “0”
Bit allocation State immediately after reset
RGB
R0GB
2BIT
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
?
0016
?
00
?
0016
?
0016
?
0
0016
?
0016
?
00?00??0
0016
0016
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
16
Fig. 12.2.3 Memory Map of Special Function Register 1 (SFR1) (1)
Rev. 1.0
15
M37280MF–XXXSP, M37280MK–XXXSP
Data slicer control register 1 (DSC1)
A-D conversion register (AD)
A-D control register (ADCON)
Timer mode register 1 (TM1)
Timer mode register 2 (TM2)
I2C clock control register (S2)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Data slicer control register 2 (DSC2)
r
(
)
State immediately after reset
(
)
TM20
TM21
TM22
TM23
TM24
TM10
TM11
TM12
TM13
TM14
OSDR
OSDE
TM25
TM15
TM16
TM17
TM26
TM27?SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
BSEL0
BSEL1
CCR0
CCR1
CCR2
CCR3
CCR4ACK
R
TM56R
TM56E
TM56S
ADIN0
ADIN1
ADIN2
ADVREF
ADSTR
10BIT
DSC10
DSC11
DSC12
DSC20
DSC23
DSC24
DSC25
CRD3
CRD4
CRD5
CRD6
CRD7
DPS3
DPS4
DPS5
DPS6
DPS7
CPS0
CPS3
CPS4
CPS5
CPS1
CPS2
CPS6
CPS7
CDH10
CDH13
CDH14
CDH15
CDH11
CDH12
CDH16
CDH17
CDL10
CDL13
CDL14
CDL15
CDL11
CDL12
CDL16
CDL17
FAST
E
ACK
CDH20
CDH23
CDH24
CDH25
CDH21
CDH22
CDH26
CDH27
CDL20
CDL23
CDL24
CDL25
CDL21
CDL22
CDL26
CDL27
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR1 area (addresses E016 to FF16)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Bit allocation
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Address
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16
Registe
Caption data register 1 (CD1)
Caption data register 2 (CD2)
Caption data register 3 (CD3)
Caption data register 4 (CD4)
Caption Position register (CPS)
Data slicer test register 2
Data slicer test register 1
Sync signal counter register (HC)
Clock run-in detect register (CRD)
Data clock position register (DPS)
Bank control register (BK)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
I2C data shift register (S0)
I2C address register (S0D)
I2C status register (S1)
I2C control register (S1D)
CPU mode register (CM)
:
Function bit
:
Name
: No function bit
: Fix to this bit to “0”
0
do not write to “1”
: Fix to this bit to “1”
1
do not write to “0”
Bit allocation
b7
0
00
0
00
0
CM7 CM5CM6
BIT
ADR
ADE
0
SAD
MOD
VSCR
IN2RIICR
VSCE
b0
00
0
0016
0016
HC0HC3HC4HC5 HC1HC2
0
10
BK0BK3 BK1BK2BK6BK7
D1D2D3D4D5D6D7 D0
RBW
LRBAD0AASALPINBBTRXMST
BC0BC1BC2ESOALS
CK
CKEIICE
CM2
SIOR
00
TM1RTM2RTM3RTM4R
DSR
TM1ETM2ETM3ETM4E
IN1EDSESIOEIN2E
101
CK0 IN1R
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
State immediately after reset
b7
0016
0?0? 0 ???
0016
0016
0016
0016
0000?00 0
0016
0016
??00??? ?
0016
0916
?
0016
?
000?001 0
FF16
0716
FF16
0716
0016
0016
0016
00 0 010 0?
0016
0016
3C16
0016
0016
0016
0016
b0
Fig. 12.2.4 Memory Map of Special Function Register 1 (SFR2) (2)
16
Rev. 1.0
M37280MF–XXXSP, M37280MK–XXXSP
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
)
)
)
)
)
)
)
)
Interrupt input polarity register (IP)
)
)
Clock control register (CS)
(
)
)
)
)
I/O polarity control register (PC)
r
(
)
(
)
)
g
)
ROM correction address 1 (high-order)
ROM correction enable register (RCR)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
ROM correction address 1 (low-order)
0
5PW6PN3
INT3
AD/INT3
AD/INT3
INT3
AD/INT3
INT3
AD/INT3
INT3
AD/INT3
INT3
AD/INT3
TB20
TB21
BB20
BB21
0
OC30
OC31
OC32
BB17
BB16
BB15
BB14
BB13
BB12
BB11
BB10
TB17
TB16
TB15
TB14
TB13
TB12
TB11
TB10
OC27
OC25
OC24
OC23
OC12
OC21
OC20
OC33
OC34
INT3
AD/INT3
OC26
RCR0
RCR1
OC35
OC36
OC37
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR2 area (addresses 20016 to 21F16)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Bit allocation
:
Function bit
Name
:
: No function bit
: Fix to this bit to “0”
0
do not write to “1”
: Fix to this bit to “1”
1
do not write to “0”
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
State immediately after reset
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
Address Registe
2001
2011
2021
2031
2041
2051
2061
2071
PWM0 register (PWM0
PWM1 register (PWM1
PWM2 register (PWM2
PWM3 register (PWM3
PWM4 register (PWM4
PWM5 register (PWM5
PWM6 register (PWM6
PWM7 register (PWM7
2081
2091
20A1
20B1
PWM mode register 1 (PN
PWM mode register 2 (PW
20C16
20D16
20E1
20F1
2101
2111
Test register
2121
2131
2141
2151
Serial I/O mode register (SM
Serial I/O register (SIO
OSD control re
2161
2171
2181
2191
21A1
21B1
21C16
21D16
21E1
21F1
Raster color register (RC
OSD control register 3(OC3)
Timer 5 (TM5
Timer 6
TM6
Top border control register 1 (TB1)
Bottom border control register 1 (BB1)
Top border control register 1 (TB2)
Bottom border control register 1 (BB2)
ister 2(OC2
b7 b0 b7 b0
?
?
?
?
?
?
?
?
?
?
Bit allocation State immediately after reset
PW7
PN4
PN
PW
PW1PW2PW3PW4PW
0016
0016
0016
0016
0016
0016
SEL
SEL
SEL
SEL
POL
POL3
POL
SM6
POL
00
0016
POL2POL1
RE1RE2RE3RE5
0016
0016
RE1RE2RE3RE5
SM0RE1RE2RE3SM4RE5
SM1SM2SM3SM5
0016
0016
?
0016
SEL
SEL
SEL
0
00
POL
POL
POL
0
RC3RC4
RE1RE2
CS0CS1CS2
PC0RE1RE2RE3PC4RE5
PC1PC2PC5PC6PC7
RC0RE1RE2RE3RE5
RC1RC2
RE1RE2RE3
0016
8016
0016
0016
0716
FF16
?
?
?
?
Fig. 12.2.5 Memory Map of Special Function Register 2 (SFR2) (1)
Rev. 1.0
17
M37280MF–XXXSP, M37280MK–XXXSP
Vertical position register 1
(VP111)
Vertical position register 13(VP13)
Vertical position register 17 (VP17)
Vertical position register 15(VP15)
Vertical position register 16 (VP16)
Vertical position register 11(VP11)
Vertical position register 12(VP12)
Vertical position register 19 (VP19)
Vertical position register 1
(VP110)
Vertical position register 14(VP14)
Vertical position register 1
(VP112)
Vertical position register 18 (VP18)
Vertical position register 23 (VP23)
Vertical position register 27 (VP27)
Vertical position register 25 (VP25)
Vertical position register 26 (VP26)
Vertical position register 21 (VP21)
Vertical position register 29 (VP29)
Vertical position register 2
(VP210)
Vertical position register 24 (VP24)
Vertical position register 2
(VP212)
Vertical position register 28 (VP28)
Vertical position register 22 (VP22)
Vertical position register 2
(VP211)
r
State immediately after reset
(
)
Vertical position register 2
(VP214)
Vertical position register 2
(VP213)
Vertical position register 2
(VP216)
Vertical position register 2
(VP215)
Vertical position register 1
(VP113)
Vertical position register 1
(VP114)
Vertical position register 1
(VP115)
Vertical position register 1
(VP116)
VP112
VP113
VP114
VP115
VP116
VP117
VP122
VP123
VP124
VP125
VP126
VP127
VP132
VP133
VP134
VP135
VP136
VP137
VP142
VP143
VP144
VP145
VP146
VP147
VP152
VP153
VP154
VP155
VP156
VP157
VP162
VP163
VP164
VP165
VP166
VP167
VP172
VP173
VP174
VP175
VP176
VP177
VP182
VP183
VP184
VP185
VP186
VP187
VP192
VP193
VP194
VP195
VP196
VP197
VP1102
VP1103
VP1104
VP1105
VP1106
VP1107
VP1112
VP1113
VP1114
VP1115
VP1116
VP1117
VP111
VP121
VP131
VP141
VP151
VP161
VP171
VP181
VP191
VP1101
VP1111
VP1121
VP1122
VP1123
VP1124
VP1125
VP1126
VP1127
VP210
VP211
VP220
VP221
VP230
VP231
VP240
VP241
VP250
VP251
VP260
VP261
VP270
VP271
VP280
VP281
VP290
VP291
VP2100
VP2101
VP2110
VP2111
VP2120
VP2121
VP110
VP120
VP130
VP140
VP150
VP160
VP170
VP180
VP190
VP1100
VP1110
VP1120
VP2130
VP2131
VP2140
VP2141
VP2150
VP2151
VP2160
VP2161
VP1142
VP1143
VP1144
VP1145
VP1146
VP1147
VP1152
VP1153
VP1154
VP1155
VP1156
VP1157
VP1162
VP1163
VP1164
VP1165
VP1166
VP1167
VP1140
VP1150
VP1160
VP1141
VP1151
VP1161
VP1131
VP1132
VP1133
VP1134
VP1135
VP1136
VP1137
VP1130
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR2 area (addresses 22016 to 23F16)
Address
22016
22116
22216
22316
22416
22516
22616
22716
22816
22916
22A16
22B16
22C16
22D16
22E16
22F16
23016
23116
23216
23316
23416
23516
23616
23716
23816
23916
23A16
23B16
23C16
23D16
23E16
23F16
Registe
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Bit allocation
:
Function bit
:
Name
: No function bit
: Fix to this bit to “0”
0
(do not write to “1”)
: Fix to this bit to “1”
1
do not write to “0”
Bit allocation
b7 b0 b7 b0
10
11
12
13
14
15
16
10
11
12
13
14
15
16
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
State immediately after reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Fig. 12.2.6 Memory Map of Special Function Register 2 (SFR2) (2)
18
Rev. 1.0
M37280MF–XXXSP, M37280MK–XXXSP
State immediately after reset
r
CR12
CR13
CR14
CR15
CR16
CR22
CR23
CR24
CR25
CR26
CR32
CR33
CR34
CR35
CR36
CR42
CR43
CR44
CR45
CR46
CR52
CR53
CR54
CR55
CR56
CR62
CR63
CR64
CR65
CR66
CR72
CR73
CR74
CR75
CR76
CR92
CR93
CR94
CR95
CR96
CR102
CR103
CR104
CR105
CR106
CR112
CR113
CR114
CR115
CR116
CR11
CR21
CR31
CR41
CR51
CR61
CR71
CR91
CR101
CR111
CR121
CR122
CR123
CR124
CR125
CR126
CR10
CR20
CR30
CR40
CR50
CR60
CR70
CR90
CR100
CR110
CR120
CR142
CR143
CR144
CR145
CR146
CR152
CR153
CR154
CR155
CR156
CR140
CR150
CR141
CR151
CR131
CR132
CR133
CR134
CR135
CR136
CR130
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
■ SFR2 area (addresses 24016 to 25816)
Address
24016
24116
24216
24316
24416
24516
24616
24716
24816
24916
24A16
24B16
24C16
24D16
24E16
24F16
25016
25116
25216
25316
25416
25516
25616
25716
25816
Registe
Color pallet register 1 (CR1)
Color pallet register 2 (CR2)
Color pallet register 3 (CR3)
Color pallet register 4 (CR4)
Color pallet register 5 (CR5)
Color pallet register 6 (CR6)
Color pallet register 7 (CR7)
Color pallet register 9 (CR9)
Color pallet register10 (CR10)
Color pallet register 11 (CR11)
Color pallet register 12 (CR12)
Color pallet register 13 (CR13)
Color pallet register 14 (CR14)
Color pallet register 15 (CR15)
Left border control register 1 (LB1)
Left border control register 2 (LB2)
Right border control register 1 (RB1)
Right border control register 2 (RB2)
SPRITE vertical position register 1 (VS1)
SPRITE vertical position register 2 (VS2)
SPRITE horizontal position register 1 (HS1)
SPRITE horizontal position register 2 (HS2)
SPRITE OSD control register (SC)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Bit allocation
:
Function bit
:
Name
: No function bit
: Fix to this bit to “0”
0
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Bit allocation
b7 b0 b7 b0
LB12LB13LB14LB15LB16LB17
VS12VS13VS14VS15VS16VS17
HS12HS13HS14HS15HS16HS17
HS22
SC2SC3SC4SC5
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
?
after reset
State immediately after reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
LB10LB11
LB20LB21LB22
RB10RB11RB12RB13RB14RB15RB16RB17
RB20RB21RB22
VS10VS11
VS20VS21
HS10HS11
HS20HS21
SC0SC1
0116
0016
FF16
0716
?
0016
?
???00000
0016
Fig. 12.2.7 Memory Map of Special Function Register 2 (SFR2) (3)
Rev. 1.0
19
PRELIMINARY
Name
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Bit allocation
:
Function bit
:
: No function bit
: Fix to this bit to “0”
0
?
(do not write to “1”)
: Fix to this bit to “1”
1
(do not write to “0”)
Register
b7
Processor status register (PS)
Program counter (PCH)
Program counter (PCL)
Fig. 12.2.8 Internal State of Processor Status Register and Program Counter at Reset
Bit allocation State immediately after reset
b0
b7
I ZCDBTVN???????
State immediately after reset
: “0” immediately after reset
0
: “1” immediately after reset
1
: Indeterminate immediately
after reset
1
Contents of address FFFF16
Contents of address FFFE16
b0
Rev. 1.0
20
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.3 INTERRUPTS
Interrupts can be caused by 19 different sources consisting of 3 external, 14 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 12.3.1. Reset is also included in the table because its operation is similar to an interrupt.
When an interrupt is accepted,
① The contents of the program counter and processor status regis
ter are automatically stored into the stack.
➁ The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
➂ The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 12.3.2 to 12.3.6 show
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 12.3.1 shows interrupt control.
12.3.1 Interrupt Causes
(1) VSYNC and OSD Interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1, INT2 Interrupts
The INT1 and INT2 interrupts are external interrupt inputs, the
system detects that the level of a pin changes from LOW to HIGH
or from HIGH to LOW, and generates an interrupt request. The
input active edge can be selected by bits 3 and 4 of the interrupt
input polarity register (address 021216) : when this bit is “0,” a
change from LOW to HIGH is detected; when it is “1,” a change
from HIGH to LOW is detected. Note that both bits are cleared to
“0” at reset.
(3) Timer 1 to 4 Interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
Table 12.3.1 Interrupt Vector Addresses and Priority
Priority
Reset
1
OSD interrupt
2
INT1 interrupt
3
Data slicer interrupt
4
Serial I/O interrupt
5
Timer 4 • SPRITE OSD interrupt
6
f(XIN)/4096 interrupt
7
VSYNC interrupt
8
Timer 3 interrupt
9
Timer 2 interrupt
10
Timer 1 interrupt
11
A-D convertion • INT3 interrupt
12
INT2 interrupt
13
Multi-master I2C-BUS interface interrupt
14
Timer 5 • 6 interrupt
15
BRK instruction interrupt
16
Note : Switching a source during a program causes an unnecessary interrupt occurs. Accordingly, set a source at initializing of program.
Interrupt Source
Vector Addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Software switch by software (See note)
Active edge selectable
Software switch by software (See note)/
When selecting INT3 interrupt, active edge selectable.
Active edge selectable
Software switch by software (See note)
Non-maskable (software interrupt)
Rev. 1.0
21
PRELIMINARY
t
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(4) Serial I/O Interrupt
This is an interrupt request from the clock synchronous serial I/O
function.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
(5) f(XIN)/4096 • SPRITE OSD Interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.”
The SPRITE OSD interrupt occurs at the completion of SPRITE
display.
Since f(XIN)/4096 interrupt and SPRITE OSD interrupt share the
same vector, an interrupt source is selected by bit 5 of the SPRITE
OSD control register (address 025816).
(6) Data Slicer Interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS Interface Interrupt
This is an interrupt request related to the multi-master I2C-BUS
interface.
(8) A-D Conversion • INT3 Interrupt
The A-D conversion interrupt occurs at the completion of A-D
conversion.
The INT3 is an external input,the system detects that the level of
a pin changes from LOW to HIGH or from HIGH to LOW, and
generates an interrupt request. The input active edge can be
selected by bit 6 of the interrupt input polarity register (address
021216) : when this bit is “0,” a change from LOW to HIGH is
detected; when it is “1,” a change from HIGH to LOW is detected.
Note that this bit is cleared to “0” at reset.
Since A-D conversion interrupt and the INT3 interrupt share the
same vector, an interrupt source is selected by bit 7 of the interrupt interval determination control register (address 021216).
Interrupt request bi
Interrupt enable bit
Interrupt disable flag I
Fig. 12.3.1 Interrupt Control
BRK instruction
Reset
Interrupt
request
(9) Timer 5 • 6 Interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10) BRK Instruction Interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Rev. 1.0
22
PRELIMINARY
After reset
0 : No interrupt request issued
)
q
)
q
)
q
)
(
)
q
)
A-D conversion • INT3
0 : No interrupt request issued
0 : No interrupt request issued
0 : No interrupt request issued
0 : No interrupt request issued
0 : No interrupt request issued
0 : No interrupt request issued
,
After reset
q
)
0 : No interrupt request issued
q
)
q
)
q
)
5
0 : No interrupt request issued
0 : No interrupt request issued
0 : No interrupt request issued
✽
✽
W
f(XIN)/4096 • SPRITE OSD
0 : No interrupt request issued
2
0 : No interrupt request issued
6
q
)
0 : No interrupt request issued
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt request register 1 (IREQ1) [Address 00FC
16]
Fig. 12.3.2 Interrupt Request Register 1
Interrupt Request Register 2
B Name Functions
Timer 1 interrupt
0
request bit (TM1R
Timer 2 interrupt
1
re
uest bit (TM2R
Timer 3 interrupt
2
uest bit (TM3R
re
Timer 4 interrupt
3
re
uest bit (TM4R
OSD interrupt request
4
bit
OSDR
SYNC interrupt
V
5
re
uest bit (VSCR
6
interrupt request bit (ADR)
Nothing is assigned. This bit is a write disable bit.
7
When this bit is read out
✽: “0” can be set by software, but “1” cannot be set.
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
the value is “0.”
RW
0
0
0
0
0
0
0
0
✽
R
✽
R
✽
R
✽
R
✽
R
✽
R
✽
R
—
R
b7 b6b5b4b3 b2b1b0
0
Fig. 12.3.3 Interrupt Request Register 2
Interrupt request register 2 (IREQ2) [Address 00FD
B Name Functions
INT1 interrupt
0
uest bit (IN1R
re
Data slicer interrupt
1
re
uest bit (DSR
Serial I/O interrupt
2
uest bit (SIOR
re
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
3
interrupt request bit (CKR)
INT2 interrupt
4
uest bit (IN2R
re
Multi-master I
C-BUS
interrupt request bit (IICR)
1 : Interrupt request issued
1 : Interrupt request issued
1 : Interrupt request issued
Timer 5 • 6 interrupt
uest bit (TM56R
re
Fix this bit to “0.”
7
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
16
]
RW
0
0
0
0
0
0
0
0
✽
R
✽
R
✽
R
R
✽
R
R
✽
R
R
Rev. 1.0
23
PRELIMINARY
After reset
(
)
0 : Interrupt disabled
(
)
(
)
(
)
0 : Interrupt disabled
0 : Interrupt disabled
0 : Interrupt disabled
7
,
(
)
0 : Interrupt disabled
5
(
)
0 : Interrupt disabled
6
A-D conversion • INT3
0 : Interrupt disabled
After reset
(
)
0 : Interrupt disabled
(
)
(
)
(
)
0 : Interrupt disabled
0 : Interrupt disabled
0 : Interrupt disabled
f(XIN)/4096 • SPRITE OSD
0 : Interrupt disabled
5
0 : Interrupt disabled
6
(
)
0 : Interrupt disabled
7
(
)
0 : Timer 5
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Control Register 1
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt control register 1 (ICON1) [Address 00FE
16]
Fig. 12.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3 b2b1b0
B Name Functions
Timer 1 interrupt
0
enable bit
Timer 2 interrupt
1
enable bit
Timer 3 interrupt
2
enable bit
Timer 4 interrupt
3
enable bit
OSD interrupt enable bit
4
OSDE
VSYNC interrupt enable
bit
interrupt enable bit (ADE)
Nothing is assigned. This bit is a write disable
bit. When this bit is read out
Interrupt control register 2 (ICON2) [Address 00FF
TM1E
TM2E
TM3E
TM4E
VSCE
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
the value is “0.”
0
0
0
0
0
0RW
0RW
0
16]
RW
RW
RW
RW
RW
RW
R—
Fig. 12.3.5 Interrupt Control Register 2
24
B Name Functions
INT1 interrupt
0
enable bit
Data slicer interrupt
1
enable bit
Serial I/O interrupt
2
enable bit
3
interrupt enable bit (CKE)
INT2 interrupt enable
4
bit
IN2E
Multi-master I2C-BUS interface
interrupt enable bit (IICE)
Timer 5 • 6 interrupt
enable bit
Timer 5 • 6 interrupt
switch bit
IN1E
DSE
SIOE
TM56E
TM56S
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Interrupt enabled
1 : Timer 6
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0RW
0RW
0RW
Rev. 1.0
PRELIMINARY
e
s
R
W
0 to 2
R
RWRWR
W
R
W
R
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt input polarity register (IP) [Address 0212
16]
Fig. 12.3.6 Interrupt Input Polarity Register
B Nam
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are “0.”
3
INT1 polarity switch bit
(POL1)
INT2 polarity switch bit
4
(POL2)
5
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is “0.”
6
INT3 polarity switch bit
(POL3)
7 A-D conversion • INT3
interrupt source selection
bit (AD/INT3SEL)
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : INT3 interrupt
1 : A-D conversion interrupt
Function
After reset
0
0
0
0
0
0
—
—
Rev. 1.0
25
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.4 TIMERS
This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4,
timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer
latch. The timer block diagram is shown in Figure 12.4.3.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses
021A16 and 021B16 : timers 5 and 6), the value is also set to a timer ,
simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
12.4.1 Timer 1
Timer 1 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/4096 or f(XCIN)/4096
• External clock from the P42/TIM2 pin
The count source of timer 1 is selected by setting bits 5 and 0 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
12.4.2 Timer 2
Timer 2 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 1 overflow signal
• External clock from the TIM2 pin
The count source of timer 2 is selected by setting bits 4 and 1 of
timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
12.4.3 Timer 3
Timer 3 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XCIN)
• External clock from the TIM3 pin
The count source of timer 3 is selected by setting bit 0 of timer mode
register 2 (address 00F516) and bit 6 at address 00C716. Either f(XIN)
or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
12.4.5 Timer 5
Timer 5 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 2 overflow signal
• Timer 4 overflow signal
The count source of timer 3 is selected by setting bit 6 of timer mode
register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). When overflow of timer 2 or 4 is a count source for
timer 5, either timer 2 or 4 functions as an 8-bit prescaler. Either
f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
12.4.6 Timer 6
Timer 6 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• Timer 5 overflow signal
The count source of timer 6 is selected by setting bit 7 of timer mode
register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit
7 of the CPU mode register. When timer 5 overflow signal is a count
source for timer 6, timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN)✽ /16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN)✽ /16 is not selected as the timer 3 count source.
So set both bit 0 of timer mode register 2 (address 00F516) and bit 6
at address 00C716 to “0” before execution of the STP instruction
(f(XIN)✽ /16 is selected as the timer 3 count source). The internal
STP state is released by timer 4 overflow in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
✽ : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes
f(XCIN).
The structure of timer-related registers is shown in Figures 12.4.1
and 12.4.2.
12.4.4 Timer 4
Timer 4 can select one of the following count sources:
• f(XIN)/16 or f(XCIN)/16
• f(XIN)/2 or f(XCIN)/2
• f(XCIN)
The count source of timer 3 is selected by setting bits 1 and 4 of
timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
26
Rev. 1.0
PRELIMINARY
After reset
234
0: f(XIN)/16 or f(X
)/16 (Note)
0: f(XIN)/16 or f(X
)/16 (See note)
5
0: f(XIN)/4096 or f(X
)/4096 (See note)
6
7
0: f(XIN)/16 or f(X
)/16 (See note)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Timer Mode Register 1
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer mode register 1 (TM1) [Address 00F4
16]
B
0
1
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Name Functions
Timer 1 count source
selection bit 1 (TM10)
Timer 2 count source
selection bit 1 (TM11)
Timer 1 count
stop bit (TM12)
Timer 2 count stop bit
(TM13)
Timer 2 count source
selection bit 2 (TM14)
Timer 1 count source
selection bit 2 (TM15)
Timer 5 count source
selection bit 2 (TM16)
Timer 6 internal count
source selection bit
(TM17)
1: Count source selected by bit 5 of TM1
0: Count source selected by bit 4 of TM1
1: External clock from TIM2 pin
0: Count start
1: Count stop
0: Count start
1: Count stop
1: Timer 1 overflow
1: External clock from TIM2 pin
0: Timer 2 overflow
1: Timer 4 overflow
1: Timer 5 overflow
CIN
CIN
CIN
CIN
R
0
0
0
0
0
0WR
0WR
0WR
W
WR
WR
WR
WR
WR
Fig. 12.4.1 Timer Mode Register 1
Rev. 1.0
27
PRELIMINARY
After reset
0
4
0
230
005
0
6
0
W
7
0: f(XIN)/16 or f(X
)/16 (See note)
b0
(b6 at address 00C716)
External clock from TIM3 pin
b4 b1
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Timer Mode Register 2
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Timer mode register 2 (TM2) [Address 00F5
16]
B
0
Timer 3 count source
selection bit (TM20)
1,
Timer 4 count source
selection bits
(TM21, TM24)
Timer 3 count stop bit
(TM22)
Timer 4 count stop bit
(TM23)
Timer 5 count stop bit
(TM25)
Timer 6 count stop bit
(TM26)
Timer 5 count source
selection bit 1
(TM27)
Note: Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Name Functions
0 0 : f(XIN)/16 or f(XCIN)/16 (See note)
1 0: f(X
01:
11 :
0 0 : Timer 3 overflow signal
0 1 : f(X
1 0 : f(X
1 1 : f(X
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Count start
1: Count stop
1: Count source selected by bit 6
CIN)
IN)/16 or f(XCIN)/16 (See note)
IN)/2 or f(XCIN)/2 (See note)
CIN)
CIN
of TM1
RW
RW
RW
RW
RW
RW
RW
R
Fig. 12.4.2 Timer Mode Register 2
28
Rev. 1.0
PRELIMINARY
2
3
Notice: This is not a final specification.
Some paramentic limits are subject to change.
X
CIN
X
IN
TIM
CM7
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
1/4096
1/2
TM15
1/8
TM10
TM12
TM14
TM11
TM13
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 1
interrupt request
8
8
Timer 2
interrupt request
8
TIM
Selection gate : Connected to
black side at
reset
TM1 : Timer mode register 1
TM2 : Timer mode register 2
T3CS : Timer 3 count source
switch bit (address 00C7
CM : CPU mode register
TM21
8
FF
16
T3CS
TM20
TM22
TM21
TM24
TM23
TM27
TM25
16
)
TM16
Timer 3 latch (8)
8
Timer 3 (8)
Timer 4 latch (8)
8
Timer 4 (8)
Timer 5 latch (8)
8
Timer 5 (8)
8
8
07
16
8
8
8
8
Reset
STP instruction
Timer 3
interrupt request
Timer 4
interrupt request
Timer 5
interrupt request
Timer 6 latch (8)
8
TM17
TM26
Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Timer 6 (8)
8
Timer 6
interrupt request
Fig. 12.4.3 Timer Block Diagram
Rev. 1.0
29
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 12.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as ports P1 and P7.
Bit 2 of the serial I/O mode register (address 021316) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT
and SCLK pins for serial I/O, set the corresponding bits of the port P4
direction register (address 00C916) to “0.” To use SIN pin for serial
I/O, set the corresponding bit of the port P1 direction register (address 00C316) to “0.”
XCIN
1/2
IN
X
SCLK
1/2
CM7
1/2
Synchronous
circuit
SM2
Serial I/O counter (8)
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
Data bus
Frequency divider
1/2
1/81/4 1/16
SM1
SM0
Selection gate: Connect to
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
black side at
reset.
SOUT
SIN
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 12.5.1 Serial I/O Block Diagram
SM5 : LSB
MSB
Serial I/O shift register (8)
(Note)
(Address 021416)
8
30
Rev. 1.0
PRELIMINARY
k
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 021416), and the transfer
clock goes “H” forcibly. At each falling edge of the transfer clock after
the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
Synchronous cloc
External clock : The an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 500kHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 12.5.2. When using an external clock for transfer, the external clock must be held at HIGH for
initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also,
be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to
the serial I/O register with the bit managing instructions, such as SEB
and CLB.
2:When an external clock is used as the synchronous clock, write trans-
mit data to the serial I/O register when the transfer clock input level is
HIGH.
Transfer clock
Serial I/O register
write signal
Serial I/O output
Serial I/O input
Fig. 12.5.2 Serial I/O Timing (for LSB first)
SOUT
S
IN
Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
D0 D1 D2 D3 D4 D5 D6 D7
(Note)
Interrupt request bit is set to “1”
Rev. 1.0
31
PRELIMINARY
After reset
b1 b0
W
4
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Serial I/O Mode Register
b7b6 b5b4b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Serial I/O mode register (SM) [Address 0213
16]
B Name Functions
0, 1 Internal synchronous
clock selection bits
(SM0, SM1)
Synchronous clock
2
selection bit (SM2)
Port function
3
selection bit (SM3)
Port function
selection bit (SM4)
Transfer direction
5
selection bit (SM5)
S
IN pin switch bit
6
(SM6)
Nothing is assigned. This bit is a write disable bit.
7
When this bit is read out, the value is “0.”
0 0: f(XIN)/8 or f(XCIN)/8
0 1: f(X
IN)/16 or f(XCIN)/16
1 0: f(X
IN)/32 or f(XCIN)/32
1 1: f(X
IN)/64 or f(XCIN)/64
0: External clock
1: Internal clock
0: P11, P13
1: SCL1, SDA1
0: P12, P14
1: SCL2, SDA2
0: LSB first
1: MSB first
0: P1
7 is SIN pin.
1: P7
2 is SIN pin.
RW
0 RW
0
RW
0
RW
0
R
0
RW
0
RW
0R—
Fig. 12.5.3 Serial I/O Mode Register
Rev. 1.0
32
PRELIMINARY
BSEL1
BSEL0
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 12.6.1 shows a block diagram of the multi-master I2C-BUS
interface and T able 12.6.1 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C
control register, the I2C status register and other control circuits.
I2C address register (S0D)
b7 b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Table 12.6.1 Multi-master I2C-BUS Interface Functions
Item
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
Format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Communication mode
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note : We are not responsible for any third party’s infringement of patent rights
or other rights attributable to the use of the control function (bits 6 and 7
2
of the I
C control register at address 00F916) for connections between
2
the I
C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
Serial
data
(SDA)
Serial
clock
(SCL)
Noise
elimination
circuit
Noise
elimination
circuit
Data
control
circuit
AL
circuit
BB
circuit
Clock
control
circuit
Address comparator
b7
2
I C data shift register
S0
b7 b0
FAST
ACK
ACK
BIT
I2C clock control register (S2)
CCR4 CCR3 CCR2 CCR1 CCR0
MODE
Clock division
b0
Internal data bus
System clock
b7
MST TRX BB PIN
AL AAS AD0 LRB
2
I C status
register
(S1)
b7 b0
10BIT
ALS
SAD
I2C control register (S1D)
(φ)
BC2 BC1 BC0
ESO
Bit counter
b0
Fig. 12.6.1 Block Diagram of Multi-master I2C-BUS Interface
Rev. 1.0
33
M37280MF–XXXSP, M37280MK–XXXSP
B
After reset
Indeterminate
e
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the
ESO bit of the I2C control register (address 00F916) is “1.” The bit
counter is reset by a write instruction to the I2C data shift register.
When both the ESO bit and the MST bit of the I2C status register
(address 00F816) are “1,” the SCL is output by a write instruction to
the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Note: To write data into the I2C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
2
I C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C data shift register 1 (S0) [Address 00F616]
Nam
0
D0 to D7
to
7
Note:
To write data into the I C data shift register after setting the MST bit to
“0” (slave mode), keep an interval of 8 machine cycles or more.
Fig. 12.6.2 Data Shift Register
Functions
This is an 8-bit shift register to store
receive data and write transmit data.
2
RW
RW
Rev. 1.0
34
M37280MF–XXXSP, M37280MK–XXXSP
B
After reset
W
W
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.6.2 I2C Address Register
The I2C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: Read/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I2C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 12.6.3 I2C Address Register
I2C address register (S0D) [Address 00F716]
Name Functions
0
Read/write bit
(RBW)
1
Slave address
to
(SAD0 to SAD6)
7
0: Read
1: Write
The address data transmitted from
the master is compared with the
contents of these bits.
R
0
R—
0
R
Rev. 1.0
35
PRELIMINARY
Standard clock
B
s
After reset
W
High speed
Setup disabled
Setup disabled
Setup disabled
Setup disabled
400 (See note)
500/CCR value
1000/CCR value
32.3
Setup value of
WRWRWRW
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6.3 I2C Clock Control Register
The I2C clock control register (address 00FA16) is used to set ACK
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL Mode Specification Bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
(3) Bit 6: ACK Bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
(4) Bit 7: ACK Clock Bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated
by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission.
If data is written during transmission, the I
that data cannot be transmitted normally.
2
C clock generator is reset, so
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
2
C clock control register (S2) [Address 00FA16]
I
0
SCL frequency control bits
to
(CCR0 to CCR4)
4
56SCL mode
specification bit
(FAST MODE)
ACK bit
(ACK BIT)
7
ACK clock bit
(ACK)
Note: At 400 kHz in the high-speed clock mode, the duty is as below .
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Name Function
CCR4–CCR0
00 to 02
05
...
1D
1E
1F
0: Standard clock mode
1: High-speed clock mode
0: ACK is returned.
1: ACK is not returned.
0: No ACK clock
1: ACK clock
mode
100
83.3 16606
17.2 34.5
16.6 33.3
16.1
(at φ = 4 MHz, unit : kHz)
clock mode
33303
25004
R
0
R
0
0
0
Fig. 12.6.4 I2C Address Register
Rev. 1.0
36
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6.4 I2C Control Register
The I2C control register (address 00F916) controls the data communication format.
(1) Bits 0 to 2: Bit Counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
(2) Bit 3: I2C Interface Use Enable Bit (ESO)
This bit enables usage of the multimaster I2C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C
status register at address 00F816 ).
• Writing data to the I2C data shift register (address 00F616) is dis-
abled.
SCL
Multi-master
I2C-BUS
interface
SDA
(3) Bit 4: Data Format Selection Bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a general call (refer to “12.6.5 I2C Status Register ,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recognized.
(4) Bit 5: Addressing Format Selection Bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set
to “1,” the 10-bit addressing format is selected, all the bits of the I2C
address register are compared with address data.
(5) Bits 6 and 7:Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 12.6.5).
“0”
“1” BSEL0
“0”
SCL1/P1
“1” BSEL1
SCL2/P12
“0”
“1” BSEL0
SDA1/P1
“0”
“1” BSEL1
SDA2/P14
1
3
Note: When using multi-master I2C-BUS interface, set bits 3 and
4 of the serial I/O mode register (address 021316) to “1.”
Moreover, set the corresponding direction register to “1” to
use the port as multi-master I2C-BUS interface.
Fig. 12.6.5 Connection Port Control by BSEL0 and BSEL1
Rev. 1.0
37
PRELIMINARY
B
s
After reset
W
WRWRWRWRW
Notice: This is not a final specification.
Some paramentic limits are subject to change.
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
C control register (S1D) [Address 00F916]
I
Fig. 12.6.6 I2C Control Register
Name Function
Bit counter
0
(Number of transmit/recieve
to
bits)
2
(BC0 to BC2)
3I2C-BUS interface use
enable bit (ESO)
4 Data format selection
bit(ALS)
5 Addressing format selection
bit (10BIT SAD)
6, 7Connection control bits
2
between I C-BUS interface
and ports
(BSEL0, BSEL1)
b2 b1 b0
0 0 0: 8
0 0 1: 7
0 1 0: 6
0 1 1: 5
1 0 0: 4
1 0 1: 3
1 1 0: 2
1 1 1: 1
0: Disabled
1: Enabled
0: Addressing format
1: Free data format
0: 7-bit addressing format
1: 10-bit addressing format
b7 b6 Connection port (See note)
0 0: None
0 1: SCL1, SDA1
1 0: SCL2, SDA2
1 1: SCL1, SDA1, SCL2, SDA2
R
0
R
0
0
0
0
Rev. 1.0
38
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6.5 I2C Status Register
The I2C status register (address 00F816) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to.
(1) Bit 0: Last Receive Bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data
is input. The state of this bit is changed from “1” to “0” by executing a
write instruction to the I2C data shift register (address 00F616).
(2) Bit 1: General Call Detecting Flag (AD0)
This bit is set to “1” when a general call✽ whose address data is all
“0” is received in the slave mode. By a general call of the master
device, every slave device receives control data after the general
call. The AD0 bit is set to “0” by detecting the STOP condition or
START condition.
✽General call: The master transmits the general call address “0016”
to all slaves.
(3) Bit 2: Slave Address Comparison Flag (AAS)
This flag indicates a comparison result of address data.
■ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
• The address data immediately after occurrence of a START con-
dition matches the slave address stored in the high-order 7 bits
of the I2C address register (address 00F716).
• A general call is received.
■ In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
• When the address data is compared with the I2C address regis-
ter (8 bits consists of slave address and RBW), the first bytes
match.
■ The state of this bit is changed from “1” to “0” by executing a write
instruction to the I2C data shift register (address 00F616).
(4) Bit 3: Arbitration Lost✽ detecting flag (AL)
n the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”, arbitration is judged to have been
lost, so that this bit is set to “1.” At the same time, the TRX bit is set to
“0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” When arbitration
is lost during slave address transmission, the TRX bit is set to “0” and
the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another
master device.
✽Arbitration lost: The status in which communication as a master is
disabled.
(5) Bit 4: I2C-BUS Interface Interrupt Request Bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal is sent to the CPU. The PIN bit
is set to “0” in synchronization with a falling edge of the last clock
(including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock
generation is disabled. Figure 12.6.8 shows an interrupt request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Executing a write instruction to the I2C data shift register (address
00F616).
• When the ESO bit is “0”
• At reset
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
• In the slave reception mode, with ALS = “1” and immediately after
completion of address data reception
(6) Bit 5: Bus Busy Flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a ST ART condition is disabled by the START condition
duplication prevention function (Note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
ESO bit of the I2C control register (address 00F916) is “0” and at
reset, the BB flag is kept in the “0” state.
(7) Bit 6: Communication Mode Specification Bit (transfer direc-
tion specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is “0” in
the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
Rev. 1.0
39
PRELIMINARY
7
B
s
After reset
W
Indeterminate
W
W
L
Q
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) Bit 7: Communication Mode Specification Bit (master/slave
specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
• At reset
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816]
Note:The START condition duplication prevention function disables the ST ART
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
Fig. 12.6.7 I2C Status Register
Name Function
0
Last receive bit (LRB)
(See note)
1
General call detecting flag
(AD0) (See note)
2
Slave address comparison
flag (AAS) (See note)
3
Arbitration lost detecting flag
(AL) (See note)
2
4
C-BUS interface interrupt
I
request bit (PIN)
5
Bus busy flag (BB)
6,
Communication mode
specification bits
(TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
SC
PIN
0 : Last bit = “0 ”
1 : Last bit = “1 ”
0 : No general call detected
1 : General call detected
0 : Address match
1 : Address mismatch
0 : Not detected
1 : Detected
0 : Interrupt request issued
1 : No interrupt request issued
0 : Bus free
1 : Bus busy
b7 b6
0 0 : Slave recieve mode
0 1 : Slave transmit mode
1 0 : Master recieve mode
1 1 : Master transmit mode
(See note)
(See note)
(See note)
(See note)
R
R—
0
R—
0
R—
0
R—
0
RW
0
R
0
R
IICIR
Fig. 12.6.8 Interrupt Request Signal Generation Timing
Rev. 1.0
40
M37280MF–XXXSP, M37280MK–XXXSP
Set time for
Reset time for
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 12.6.9 for the START condition
generation timing diagram, and Table 12.6.2 for the START condition/STOP condition generation timing table.
12.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00F916) is “1,”
execute a write instruction to the I2C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 12.6.10
for the STOP condition generation timing diagram, and Table 12.6.2
for the START condition/STOP condition generation timing table.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
I2C status register
write signal
SCL
SDA
BB flag
Fig. 12.6.9 START Condition Generation Timing Diagram
I2C status register
write signal
SCL
SDA
BB flag
Setup
time
Setup
time
Setup
time
Hold time
BB flag
Hold time
BB flag
Fig. 12.6.10 STOP Condition Generation Timing Diagram
Table 12.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Setup time
Hold time
Set/reset time
for BB flag
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
Standard Clock Mode
4.25 µs (17 cycles)
5.0 µs (20 cycles)
3.0 µs (12 cycles)
High-speed Clock Mode
1.75 µs (7 cycles)
2.5 µs (10 cycles)
1.5 µs (6 cycles)
Rev. 1.0
41
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 12.6.11 and Table 12.6.3. Only when the 3 conditions of Table
12.6.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
SCL release time
SCL
SDA
(START condition)
SDA
(STOP condition)
Fig. 12.6.11 ST ART Condition/ST OP Condition Detect T iming Dia-
gram
T able 12.6.3 ST ART Condition/STOP Condition Detect Conditions
Standard Clock Mode
6.5 µs (26 cycles) < SCL
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num-
ber of φ cycles.
release time
Setup
time
Setup
time
Hold time
Hold time
High-speed Clock Mode
1.0 µs (4 cycles) < SCL
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
release time
12.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective address communication formats is described below.
(1) 7-bit Addressing Format
T o meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C
control register (address 00F916) to “0.” The first 7-bit address data
transmitted from the master is compared with the high-order 7-bit
slave address stored in the I2C address register (address 00F716).
At the time of this comparison, address comparison of the RBW bit of
the I2C address register (address 00F716) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 12.6.12, (1) and (2).
(2) 10-bit Addressing Format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I2C control register (address 00F916) to “1.” An address comparison
is made between the first-byte address data transmitted from the
master and the 7-bit slave address stored in the I2C address register
(address 00F716). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address
00F716) and the R/W bit which is the last bit of the address data
transmitted from the master is made. In the 10-bit addressing mode,
the R/W bit which is the last bit of the address data not only specifies
the direction of communication for control data but also is processed
as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I2C status register (address 00F816) is set to “1.” After
the second-byte address data is stored into the I2C data shift register
(address 00F616), make an address comparison between the second-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I2C address register (address 00F716) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I2C address register (address 00F716). For the data transmission format when the 10-bit addressing format is selected, refer to
Figure 12.6.12, (3) and (4).
42
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
the I2C clock control register (address 00FA16).
➂ Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
➃ Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄ Set the address data of the destination of transmission in the high-
order 7 bits of the I2C data shift register (address 00F616) and set
“0” in the least significant bit.
➅ Set “F016” in the I2C status register (address 00F816) to generate
a STAR T condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
➆ Set transmit data in the I2C data shift register (address 00F616). At
this time, an SCL and an ACK clock automatically occurs.
➇ When transmitting control data of more than 1 byte, repeat step ➆.
➈ Set “D016” in the I2C status register (address 00F816). After this, if
ACK is not returned or transmission ends, a STOP condition will
be generated.
12.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
➀ Set a slave address in the high-order 7 bits of the I2C address
register (address 00F716) and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
in the I2C clock control register (address 00FA16).
➂ Set “1016” in the I2C status register (address 00F816) and hold the
SCL at the HIGH.
➃ Set a communication enable status by setting “4816” in the I2C
control register (address 00F916).
➄ When a START condition is received, an address comparison is
made.
➅ •When all transmitted address are“0” (general call):
AD0 of the I2C status register (address 00F816) is set to “1”and
an interrupt request signal occurs.
•When the transmitted addresses match the address set in ➀:
ASS of the I2C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I2C status register (address 00F816) are set
to “0” and no interrupt request signal occurs.
➆ Set dummy data in the I2C data shift register (address 00F616).
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
Rev. 1.0
43
PRELIMINARY
A
s
A
s
A
A
r
A
A
A
s
A
A
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
S Slave address
(1) A master-transmitter transmits data to a slave-receiver
(2) A master-receiver receives data from a slave-transmitte
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition P : STOP condition
A : ACK bit R/W : Read/Write bit
Sr : Restart condition
7 bits “0” 1 to 8 bits 1 to 8 bit
S Slave address
7 bits “1” 1 to 8 bits 1 to 8 bit
Slave address
S
1st 7 bits
7 bits “0” 8 bits 1 to 8 bits
Slave address
S
1st 7 bits
7 bits “0” 8 bits 7 bit
R/W
R/W
R/W R/W
Data A Data A/A PR/W
Data A Data AP
Slave address
2nd byte
Slave address
2nd byte
Fig. 12.6.12 Address Data Communication Format
12.6.12 Precautions when using multi-master I2C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I2C-BUS
interface are described below.
•I2C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
•I2C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
intended. It is because hardware changes the read/write bit (RBW)
______
at the above timing.
•I2C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I2C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the ST ART condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0–BC2) at the above timing.
•I2C clock control register (S2)
The read-modify-write instruction can be executed for this register.
Data
Slave address
Sr
1st 7 bits
From master to slave
From slave to master
Data A/A P
1 to 8 bits
1 to 8 bits
Data
Data
1 to 8 bits“1”
P
(2) START condition generating procedure using multi-master
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➄).
•
•
LDA — (Taking out of slave address value)
SEI (Interrupt disabled)
BBS 5,S1,BUSBUSY
(BB flag confirming and branch process)
BUSFREE:
STA S0 (Writing of slave address value)
LDM #$F0, S1
(Trigger of ST ART condition generating)
CLI (Interrupt enabled)
•
•
BUSBUSY:
CLI (Interrupt enabled)
•
•
➁Use “STA,” “STX” or “STY” of the zero page addressing instruction
for writing the slave address value to the I2C data shift register.
➂Use “LDM” instruction for setting trigger of START condition gener-
ating.
➃Write the slave address value of above ➁ and set trigger of START
condition generating of above ➂ continuously shown the above
procedure example.
➄Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
Rev. 1.0
44
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(3) RESTART condition generating procedure
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➅.)
Execute the following procedure when the PIN bit is “0.”
•
•
LDM #$00, S1 (Select slave receive mode)
LDA — (Taking out of slave address value)
SEI (Interrupt disabled)
STA S0 (Writing of slave address value)
LDM #$F0, S1 (Trigger of RESTART condition generating)
CLI (Interrupt enabled)
•
•
➁Select the slave receive mode when the PIN bit is “0.” Do not write
“1” to the PIN bit. Neither “0” nor “1” is specified for the writing to
the BB bit.
The TRX bit becomes “0” and the SDA pin is released.
➂The SCL pin is released by writing the slave address value to the
I2C data shift register. Use “STA,” “STX” or “STY” of the zero page
addressing instruction for writing.
➃Use “LDM” instruction for setting trigger of RESTART condition gen-
erating.
➄Write the slave address value of above ➂ and set trigger of RE-
START condition generating of above ➃ continuously shown the
above procedure example.
➅Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) STOP condition generating procedure
➀Procedure example (The necessary conditions of the generating
procedure are described as the following ➁ to ➃.)
•
•
SEI (Interrupt disabled)
LDM #$C0, S1 (Select master transmit mode)
NOP (Set NOP)
LDM #$D0, S1 (Trigger of STOP condition generating)
CLI (Interrupt enabled)
•
•
➁Write “0” to the PIN bit when master transmit mode is select.
➂Execute “NOP” instruction after setting of master transmit mode.
Also, set trigger of STOP condition generating within 10 cycles after selecting of master trasmit mode.
➃Disable interrupts during the following two process steps:
• Select of master transmit mode
• Trigger of STOP condition generating
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an
instruction to set the MST and TRX bits to “0” from “1” simultaneously .
It is because it may enter the state that the SCL pin is released and
the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the
same as above.
(6) Process of after STOP condition generat-
ing
Do not write data in the I2C data shift register S0 and the I2C status
register S1 until the bus busy flag BB becomes “0” after generating
the STOP condition in the master mode. It is because the STOP
condition waveform might not be normally generated. Reading to the
above registers do not have the problem.
Rev. 1.0
45
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.7 PWM OUTPUT CIRCUIT
This microcomputer is equipped with eight 8-bit PWMs (PWM0–
PWM7). PWM0–PWM7 have the same circuit structure and an 8-bit
resolution with minimum resolution bit width of 4 µs and repeat period of 1024 µs (for f(X
Figure 12.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM7 us-
IN) divided by 2 as a reference signal.
ing f(X
12.7.1 Data Setting
When outputting PWM0–PWM7, set 8-bit output data to the PWMi
register (i means 0 to 7; addresses 0200
12.7.2 Transmitting Data from Register to PWM
circuit
Data transfer from the PWM register to the PWM circuit is executed
at writing data to the register.
The signal output from the PWM output pin corresponds to the contents of this register.
IN) = 8 MHz) .
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
16 to 020716).
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
12.7.3 PWM Operation
The following explains PWM operation.
First, set the bit 0 of PWM mode register 1 (address 020A
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM3 are also used as pins P0
also used as pins P0
3 respectively. Set the corresponding bits of the port P0 direction
P0
register to “1” (output mode). And select each output polarity by bit 3
of PWM mode register 1 (address 020A
PWM mode register 2 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 12.7.2 shows the PWM timing. One cycle (T) is composed of
8
) segments. The 8 kinds of pulses, relative to the weight of
256 (2
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 12.7.2 (a). The PWM outputs waveform which is the
logical sum (OR) of pulses corresponding to the contents of bits 0 to
7 of the PWM register. Several examples are shown in Figure 12.7.2
(b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected
by changing the contents of the PWM register. A length of entirely
HIGH cannot be output, i.e. 256/256.
0–P02, and PWM7 is also used as pin P50 and
4–P07, PWM4–PWM6 are
16). Then, set bits 7 to 0 of
16) to “0”
12.7.4 Output after Reset
At reset, the output of port P0 is in the high-impedance state, port
0 outputs Low, and the contents of the PWM register and the PWM
P5
circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
46
Rev. 1.0
PRELIMINARY
N
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Data bus
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM timing
1/2XI
PN0
PWM0 register
(Address 0200
b7 b0
16)
generating
circuit
8
PWM circuit
PWM1 register (Address 020116)
PWM2 register (Address 020216)
PWM3 register (Address 020316)
PWM4 register (Address 020416)
PWM5 register (Address 020516)
PWM6 register (Address 020616)
POL
P0
PW0
P05
PW1
P06
PW2
P07
PW3
P00
PW4
P01
PW5
P02
PW6
P50 PWM7
D04
4
D05 PWM1
D06 PWM2
D07 PWM3
D00 PWM4
D01
D02
PWM0
PWM5
PWM6
PW7
3
D0
P03
PN4
PN
: PWM mode register 1 [address 020A16]
PW
: PWM mode register 2 [address 020B
P0
: Port P0 register [address 00C0
D0
: Port P0 direction register [address 00C1
PWM7
16]
16]
16]
Selection gate:
Connected to
black side at
reset.
Inside of
Fig. 12.7.1 PWM Block Diagram
is as same contents with the others.
PWM7 register (Address 020716)
Rev. 1.0
47
PRELIMINARY
(a) Pulses showing the weight of each bit
1
3
5
7
9
20304050607080
90
100
110
120
130
140
150
160
170
180
190
200
210
220
230
240
250
255
4
122028
36445260687684
92
100
108
116
124
132
140
148
156
164
172
180
188
196
204
212
220
228
236
244
252
8
16
48
80
112
144
176
208
2402440
567288
104
120
136
152
168
184
200
216
232
248
3296160
22464192
Bit 7
2
6
10
14
182226
303438
42
46
50
54
58
62667074788286909498102
106
110
114
118
122
126
130
134
138
142
146
150
154
158
162
166
170
174
178
182
186
190
194
198
202
206
210
214
218
222
226
230
234
238
242
246
250
254
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
128
Bit 0
PWM output
t = 4 µs T = 1024 µs
f(X
IN) = 8 MHz
(b) Example of 8-bit PWM
t
0016 (0)
0116 (1)
1816
(24)
FF16 (255)
T = 256 t
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 12.7.2 PWM Timing
Rev. 1.0
48
PRELIMINARY
0
B
W
0
e
s
e
ese bits are read out,
ues are “0
selection b
0)
Cou
source sto
selection b
3)
0
ega
y
W
0
W
0
W
e
ese bits are read out,
ues are “0
0
After reset
340
selection b
0)
0 outpu
selection b
)
outpu
selection b
3)
3 outpu
selection b
)
outpu
selection b
5)
5 outpu
selection b
)
outpu
00000
0
selection b
6)
6 outpu
0
outpu
selection b
)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
PWM Mode Register 1
b7b6b5b4b3b2b1b
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PWM mode register 1 (PN) [Address 020A16]
Fig. 12.7.3 PWM Mode Register 1
PWM Mode Register 2
b7b6 b5b4b3 b2b1b0
Nam
PWM counts source
0
it (PN
Nothing is assigned. These bits are write disable bits.
1, 2
Wh
n th
PWM output polarity
3
it (PN
P0
3
4
/PWM7 output
selection bit (PN4)
0 : Count source supply
1 :
0 : Positive polarity
1 : N
0 : P03output
1 : PWM7 output
Function
nt
the val
tive polarit
p
.”
5 to 7 Nothing is assigned. These bits are write disable bits.
Wh
n th
PWM mode register 2 (PW) [Address 020B
B
0
Name Functions
P0
4
/PWM0 output
it (PW
1
P05/PWM1 output
it (PW1
P06/PWM2 output
2
it (PW2
7
/PWM3 output
P0
it (PW
P0
0
/PWM4 output
it (PW4
P0
1
/PWM5 output
5
it (PW
P0
2
/PWM6 output
6
it (PW
7
P5
0
/PWM7 output
it (PW7
the val
0 : P04output
1 : PWM
0 : P05output
1 : PWM1
0 : P06output
1 : PWM2
0 : P07output
1 : PWM
0 : P00output
1 : PWM4
0: P01output
1: PWM
0: P02output
1: PWM
0: P50output
1: PWM7
.”
16
]
t
t
t
t
t
t
t
t
After reset R
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
—
R
R
R
—
Fig. 12.7.4 PWM Mode Register 2
Rev. 1.0
49
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.8 A-D CONVERTER
12.8.1 A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.
12.8.2 A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 2 to 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and V
not using the A-D converter, the resistor ladder can be cut off from
the internal V
power dissipation.
CC by setting this bit to “0,” accordingly providing low-
A-D control register
(address 00EF
CC. When
b7 b0
16
)
3
12.8.3 Comparison Voltage Generator (Resistor Ladder)
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the reference voltage V
ref.
12.8.4 Channel Selector
The channel selector connects an analog input pin, selected by bits
2 to 0 of the A-D control register, to the comparator.
12.8.5 Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “V
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Data bus
ref” is stored in the A-D conversion register. The A-D con-
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
Fig. 12.8.1 A-D Comparator Block Diagram
Channel selector
Comparator
A-D control circuit
A-D conversion register
Switch tree
Resistor ladder
VSSV
8
(address 00EE16)
CC
A-D conversion
interrupt request
50
Rev. 1.0
PRELIMINARY
B
Notice: This is not a final specification.
Some paramentic limits are subject to change.
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D control register (ADCON) [Address 00EF16]
Fig. 12.8.2 A-D Control Register
Name Functions
0
Analog input pin selection
to
bits
2
(ADIN0 to ADIN2)
A-D conversion completion
3
bit (ADSTR)
V
CC
connection selection bit
4
(ADVREF)
Fix this bit to “0.”
5
Nothing is assigned. This bit is a write disable bit.
6
When this bit is read out, the value is indeterminate.
Fix this bit to “0.”
7
b2 b1 b0
0 0 0 : AD1
0 0 1 : AD2
0 1 0 : AD3
0 1 1 : AD4
1 0 0 : AD5
1 0 1 : AD6
1 1 0 : AD7
1 1 1 : AD8
0: Conversion in progress
1: Convertion completed
0: OFF
1: ON
After reset
0
1
0
0
Indeterminate
0
RW
RW
RW
RW
RW
R—
RW
Rev. 1.0
51
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.8.6 Conversion Method
➀Set bit 7 of the interrupt input polarity register (address 021216) to
“1” to generate an interrupt request at completion of A-D conversion.
➁Set the A-D conversion · INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion · INT3 interrupt reguest bit is not set to “0” automatically).
➂When using A-D conversion interrupt, enable interrupts by setting
A-D conversion · INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
➃Set the V
resistor ladder.
➄Select analog input pins by the analog input selection bit of the A-
D control register.
➅Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion register
during the A-D conversion.
➆Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, the state (“1”) of A-D conversion ·
INT3 interrupt reguest bit, or the occurrence of an A-D conversion
interrupt.
➇Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC connec-
CC connection selection bit to “1” to connect VCC to the
tion selection bit to “0” between steps ➆ and ➇.
12.8.7 Internal Operation
When the A-D conversion starts, the following operations are automatically performed.
➀ The A-D conversion register is set to “00
➁ The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “V
At this point, V
➂ Bit 7 is determined by the comparison results as follows.
When V
When V
With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum of 50 machine cycles (12.5 µs at f(X
version result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time as A-D
conversion completion, the A-D conversion · INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
Table 12.8.1 Expression for V
A-D conversion register contents “n”
Note: VREF indicates the reference voltage (= Vcc).
ref is compared with the analog input voltage “VIN .”
ref < VIN : bit 7 holds “1”
ref > VIN : bit 7 becomes “0”
IN) = 8 MHz) after it starts, and the con-
ref and VREF
(decimal notation)
0
1 to 255
16.”
ref” is input to the comparator.
Vref (V)
0
VREF
~(n |0.5)
256
Contents of A-D conversion register Reference voltage (V
A-D conversion start
1st comparison start
2nd comparison start
3rd comparison start
8th comparison start
00000000
1
0000000
1000000
1
12
1234567
100000
1
REF
2
REF
V
–
512
V
V
V
2
V
REF
V
±±
2
V
REF
V
±±±
2
.......
A-D conversion completion
(8th comparison completion)
Fig. 12.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion
12345678
Digital value corresponding to
analog input voltage.
: Value determined by mth (m = 1 to 8) result
m
REF
REF
4
REF
4
REF
4
ref
)
[V]
0
V
REF
–±
512
V
V
V
±
256
REF
8
REF
8
REF
V
REF
–
512
.....
REF
V
–
512
52
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.8.8 Definition of A-D Conversion Accuracy
The definition of A-D conversion accuracy is described below (refer
to Figure 12.8.4).
(1) Relative Accuracy
•Zero transition error (V
The deviation of the input voltage at which A-D conversion output
data changes from “0” to “1,” from the corresponding ideal A-D
conversion characteristics between 0 and V
V0T =
• Full-scale transition error (VFST)
The deviation of the input voltage at which A-D conversion output
data changes from “255” to “254,” from the corresponding ideal AD conversion characteristics between 0 and V
VFST =
• Non-linearity error
The deviation of the actual A-D conversion characteristics, from the
ideal A-D conversion characteristics between V
Non-linearity error =
0T)
(V
0 – 1/2 ✕ VREF/256)
1LSB
(V
REF – 3/2 ✕ VREF/256) – V254
1LSB
Vn – (1LSB ✕ n + V0)
1LSB
REF.
[LSB]
REF.
[LSB]
0 and V254.
[LSB]
• EDifferential non-linearity error
The deviation of the input voltage required to change output data
by “1,” from the corresponding ideal A-D conversion characteristics between 0 and V
(2) Absolute Accuracy
• EAbsolute accuracy error
The deviation of the actual A-D conversion characteristics, from the
ideal A-D conversion characteristics between 0 and V
Absolute accuracy error =
Note: The analog input voltage “Vn” at which A-D conversion output data
changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure
12.8.4) :
1LSB with respect to relative accuracy =
A with respect to absolute accuracy =
1LSB
REF.
(Vn+1 – Vn) – 1LSB
1LSB
Vn – 1LSBA ✕ (n + 1/2)
1LSB
A
V254 – V0
254
REF.
VREF
256
[LSB]Differential non-linearity error =
[LSB]
[V]
[V]
Output code
09
16
08
16
07
16
06
16
05
16
04
16
03
16
02
16
01
16
00
16
0
Absolute accuracy
+ 2LSB
Ideal A-D conversion
characteristics
Limitless resolution A-D
conversion characteristics
– 2LSB
20 40 80 100 120 140 160 180 200 220
60
Analog input voltage (mV)
Fig. 12.8.4 Definition of A-D Conversion Accuracy
Rev. 1.0
53
M37280MF–XXXSP, M37280MK–XXXSP
After reset
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses (2 blocks)
can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes
✕ 2 blocks.
Block 1 : addresses 02C016 to 02DF16
Block 2 : addresses 02E016 to 02FF16
Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the
ROM data address in the ROM correction address, the main program branches to the correction program stored in the ROM memory
for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3
bytes) are necessary at the end of the correction program. When the
blocks 1 and 2 are used in series, the above instruction is not needed
at the end of the block 1.
The ROM correction function is controlled by the ROM correction
enable register.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Fig. 12.9.1 ROM Correction Address Registers
020C16ROM correction address 1 (high-order)
020D
020E
020F
16ROM correction address 1 (low-order)
16ROM correction address 2 (high-order)
16ROM correction address 2 (low-order)
Notes 1: Specify the first address (op code address) of each
instruction as the ROM correction address.
2:Use the JMP instruction (total of 3 bytes) to return from
the correction program to the main program.
3:Do not set the same ROM correction address to blocks 1
and 2.
4:For the M37280MK-XXXSP and M37280EKSP, when using the ex-
pansion ROM (BK7 = “1”), the ROM correction function do not operate used for addresses 1000
16 to1FFF16. Note that on programming.
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021016]
B
0
1 Block 2 enable bit (RCR1) 0: Disabled
2, 3
Name Functions
Block 1 enable bit (RCR0)
Fix these bits to “0.”
0: Disabled
1: Enabled
1: Enabled
RW
0
RW
0
RW
0
RW
4
to
7
Fig. 12.9.2 ROM Correction Enable Register
54
Nothing is assigned. These bits are write disable bits. When
these bits are read out, the values are “0.”
0
R—
Rev. 1.0
PRELIMINARY
r
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10 DATA SLICER
This microcomputer includes the data slicer function for the closed
caption decoder (referred to as the CCD). This function takes out the
caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync
chip’s polarity negative is input to the CVIN pin.
Composite
video
signal
HOLD
V
1000 pF
0.1 µF
1 MΩ
Low-pass
filter
Reference
voltage
generating
circuit
470Ω
Clamping
circuit
Comparator
CV
IN
Sync slice
circuit
+
–
560 pF
1 µF
H
SYNC
When the data slicer function is not used, the data slicer circuit and
the timing signal generating circuit can be cut off by setting bit 0 of
the data slicer control register 1 (address 00E016) to “0.” These settings can realize the low-power dissipation.
1 kΩ
200 pF
Sync pulse counter
register
(address 00E9
HLF
Synchronizing
signal counter
Data slicer control register 2
Synchronizing
separation
circuit
(address 00E1
Data slicer control register 1
(address 00E0
16
)
16
)
Timing signal
generating
circuit
Data slicer ON/OFF
Clock run-in
determination
circuit
Clock run-in defect register
Data slice line
specification
circuit
(address 00EA
16
)
16
)
External circuit
Note : Make the length of wiring which is connected
to V
HOLD
, HLF, and CVINpin as short as
possible so that a leakage current may not
be generated when mounting a resistor or a
capacitor on each pin.
Caption data register 2
(address 00E3
Caption data register 4
(address 00E5
Data bus
Fig. 12.10.1 Data Slicer Block Diagram
Rev. 1.0
Start bit detecting
circuit
Caption position register
(address 00E6
16
)
Data clock
generating circuit
Data clock position register
(address 00EB
16-bit shift register
Interrupt request
generating circuit
high-order low-orde
Caption data register 1
16
)
16
)
(address 00E2
Caption data register 3
(address 00E416)
16
)
16
)
Data slicer
interrupt
request
55
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.10.1 Notes When not Using Data Slicer
When bit 0 of data slicer control register 1 (address 00E016) is “0,”
terminate the pins as shown in Figure 12.10.2.
<When data slicer circuit and timing signal generating circuit is in OFF state>
Apply the same voltage as VCC to
AVCC pin.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
AVCC
24
M37280EKSP
Apply HLF pin VCC or VSS level.
Apply VHOLD pin VCC or VSS level.
VCC or VSS
VCC or VSS
25
27
HLF
VHOLD
Pull-up CVIN pin to VCC through
a resistor of 5 kΩ or more.
Fig. 12.10.2 Termination of Data Slicer Input/Output Pins when Data Slicer Circuit and Timing Generating Circuit Is in OFF State
When both bits 0 and 2 of data slicer control register 1 (address
00E016) are “1,” terminate the pins as shown in Figure 12.10.3.
VCC or VSS
28
CVIN
<When using a reference clock generated in timing signal generating circuit as OSD clock>
Apply the same voltage as VCC to AVCC pin.
Connect the same external circuit as when
using data slicer to HLF pin.
1 kΩ
200pF1 µF
24
25
AVCC
HLF
Leave VHOLD pin open.
Pull-up CVIN to VCC through a resistor
5 kΩ or more
Open
of 5 kΩ or more.
Fig. 12.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit Is in ON State
56
27
28
VHOLD
CVIN
Rev. 1.0
M37280MF–XXXSP, M37280MK–XXXSP
Reference clock source
Data slicer and timing signal
3 to
Selection bit of data slice reference
After reset
W
R
W
Indeterminate
Indeterminate
Indeterminate
Vertical synchronous signal
Indeterminate
B
After reset
s
e
Indeterminate
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Figures 12.10.4 and 12.10.5 the data slicer control registers.
Data Slicer Control Register 1
b7b6 b5b4b3b2b1b0
00
000
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Data slicer control register 1(DSC1) [Address 00E0
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
16
]
Fig. 12.10.4 Data Slicer Control Register 1
Data Slicer Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
00
B
00
generating circuit control bit (DSC10)
Name Functions
0: Stopped
1: Operating
1 0: F2
voltage generating field (DSC11)
2
selection bit (DSC12)
1: F1
0: Video signal
1: H
SYNC
signal
Fix these bits to “0.”
R
RW
0RW
0R
W
0RW
7
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
sep
V
sep
H
F2:
sep
V
Data slicer control register 2 (DSC2) [Address 00E1
Nam
0
Caption data latch
completion flag 1
(DSC20)
0: Data is not latched yet and a
clock-run-in is not determined.
1: Data is latched and a
clock-run-in is determined.
Function
16
]
R—
Fig. 12.10.5 Data Slicer Control Register 2
Rev. 1.0
Fix this bit to “0.”
1
2
Test bit
3 0: F2
Field determination
flag(DSC23)
4 0: Method (1)
(V
sep
) generating method
selection bit (DSC24)
5 0: Match
V-pulse shape
determination flag (DSC25)
Fix this bit to “0.”
6
Test bit
7
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1:
sep
V
sep
H
F2:
sep
V
Read-only
1: F1
1: Method (2)
1: Mismatch
Read-only
0R
W
R—
R—
0RW
R—
0R
W
R—
57
M37280MF–XXXSP, M37280MK–XXXSP
s
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.10.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync chip part of the composite video
signal input from the CVIN pin. The low-pass filter attenuates the noise
of clamped composite video signal. The CVIN pin to which composite
video signal is input requires a capacitor (0.1 µF) coupling outside.
Pull down the CVIN pin with a resistor of hundreds of kiloohms to 1
MΩ. In addition, we recommend to install externally a simple lowpass filter using a resistor and a capacitor at the CVIN pin (refer to
Figure 12.10.1).
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Composite
Measure “L” period
Timing
signal
12.10.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter.
12.10.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
(1)Horizontal Synchronous Signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
(2)Vertical Synchronous Signal (Vsep)
As a Vsep signal generating method, it is possible to select one of
the following 2 methods by using bit 4 of the data slicer control
register 2 (address 00E116).
•Method 1 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a Vsep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists, a Vsep signal is generated in synchronization
with the rising of the timing signal (refer to Figure12.10.6).
Figure 12.10.6 shows a Vsep generating timing. The timing signal
shown in the figure is generated from the reference clock which the
timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 12.10.7, when the A level matches the B level, this
bit is “0.” In the case of a mismatch, the bit is “1.”
Vsep signal
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Fig. 12.10.6 Vsep Generating Timing (method 2)
Rev. 1.0
58
M37280MF–XXXSP, M37280MK–XXXSP
A
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.10.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronous signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronous signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 1 (address
00E016) to “1.”
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The HSYNC signal can be used as a
count source instead of the composite sync signal. However, when
the HSYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 2 of data slicer
control register 1 (address 00E016).
For the pins HLF, connect a resistor and a capacitor as shown in
Figure 12.10.1. Make the length of wiring which is connected to these
pins as short as possible so that a leakage current may not be generated.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Composite
sync signal
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Bit 5 of DSC2
0
1
1
B
Note: It takes a few tens of milliseconds until the reference clock becomes
stable after the data slicer and the timing signal generating circuit are
started. In this period, various timing signals, H
nals become unstable. For this reason, take stabilization time into consideration when programming.
sep signals and Vsep sig-
Fig. 12.10.7 Determination of V-pulse Waveform
Rev. 1.0
59
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.6 Data Slice Line Specification Circuit
(1) Specification of Data Slice Line
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 12.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 12.10.8 shows
the signals in the vertical blanking interval. Figure 12.10.9 shows
the structure of the caption position register.
(2) Specification of Line to Set Slice Voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 7). The
field to generate slice voltage is specified by bit 1 of data slicer
control register 1. The line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to
Table 12.10.1).
(3) Field Determination
The field determination flag can be read out by bit 3 of data slicer
control register 2. This flag charge at the falling edge of Vsep.
Video signal
Composite
video signal
V
H
sep
sep
Count value to be set in the caption position register (“0F
H
sep
Composite video
signal
Window for
deteminating
clock-run-in
Vertical blanking interval
1 appropriate line is set by
the caption position register
(when setting line 19)
16
” in this case)
Clock run-in Start bit + 16-bit data
Start bit
Line 21
Magnified drawing
Fig. 12.10.8 Signals in Vertical Blanking Interval
60
Rev. 1.0
PRELIMINARY
r
Indeterminate
After reset
e
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Caption Position Registe
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Caption Position Register (CPS) [Address 00E6
16]
Fig. 12.10.9 Caption Position Register
Table 12.10.1 Specification of Data Slice Line
b7
CPS
b6
Field and Line to Be Sliced Data
• Both fields of F1 and F2
0
• Line 21 and a line specified by bits 4 to 0 of CPS
0
(total 2 lines) (See note 2)
• Both fields of F1 and F2
0
• A line specified by bits 4 to 0 of CPS
1
(total 1 line) (See note 3)
1
• Both fields of F1 and F2
0
• Line 21 (total 1 line)
• Both fields of F1 and F2
1
• Line 21 and a line specified by bits 4 to 0 of CPS
1
(total 2 lines) (See note 2)
Notes 1: DSC1 is data slicer control register 1.
CPS is caption position register.
2:Set “00
16” to “1016” to bits 4 to 0 of CPS.
3:Set “00
16” to “1F16” to bits 4 to 0 of CPS.
B
0
Caption position
to
bits(CPS0 to CPS4)
4
5 0: Data is not latched yet and a
Caption data latch
completion flag 2
(CPS5)
6, 7 Refer to the corresponding
Slice line mode
specification bits
(in 1 field) (CPS6, CPS7)
1: Data is latched and a
Table (Table 12.10.1).
FunctionsNam
clock-run-in is not determined.
clock-run-in is determined.
Field and Line to Generate Slice V oltage
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• A line specified by bits 4 to 0 of CPS
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC1
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC1
• Line 21 and a line specified by bits 4 to 0 of CPS
(total 2 lines) (See note 2)
RW
0
RW
R—
0R
W
Rev. 1.0
61
PRELIMINARY
R
W
B
After reset
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.7 Reference Voltage Generating Circuit
and Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
(1) Reference Voltage Generating Circuit
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the
data slice line specification circuit. Connect a capacitor between
the VHOLD pin and the VSS pin, and make the length of wiring as
short as possible so that a leakage current may not be generated.
(2) Comparator
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the reference voltage generating circuit, and converts the composite video
signal into a digital value.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00EA
12.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit.
The detection of a start bit is described below.
➀ A sampling clock is generated by dividing the reference clock output by the timing signal.
➁ A clock run-in pulse is detected by the sampling clock.
➂ After detection of the pulse, a start bit pattern is detected from the
comparator output.
12.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00EA16). Read out
these bits after the occurrence of a data slicer interrupt (refer to
“12.10.12 Interrupt Request Generating Circuit”).
Figure 12.10.10 shows the structure of clock run-in detect register.
16]
Fig. 12.10.10 Clock Run-in Detect Register
0
Test bits
to
2
3
Clock run-in detection
to
bit(CRD3 to CRD7)
7
FunctionsName
Read-only
Number of reference clocks to
be counted in one clock run-in
pulse period.
0
R—
0R—
Rev. 1.0
62
M37280MF–XXXSP, M37280MK–XXXSP
t
s
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.10.10 Data Clock Generating Circuit
This circuit generates a data clock synchronized with the start bit
detected in the start bit detecting circuit. The data clock stores caption data to the 16-bit shift register. When the 16-bit data has been
stored and the clock run-in determination circuit determines clock
run-in, the caption data latch completion flag is set. This flag is reset
at a falling of the vertical synchronous signal (Vsep).
Data Clock Position Register
b7 b6 b5 b4 b3 b2 b1 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
010
Data clock position register (DPS) [Address 00EB
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
16]
Fig. 12.10.11 Data Clock Position Register
B
01
1,2 Fix this bit to “0.“
3
4
to
7
Name
Fix these bits to “1.“
Data clock position set
bits (DPS3 to DPS7)
Function
After rese
RW
RW
0RW
1RW
0
Rev. 1.0
63
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.11 16-bit Shift Register
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00E516). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00E416), respectively. These registers
are reset to “0” at a falling of Vsep. Read out data registers 1 and 2
after the occurrence of a data slicer interrupt (refer to “12.10.12 Interrupt Request Generating Circuit”).
Table 12.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Slice Line Specification Mode
CPS
bit 7
0
0
1
1
CPS: Caption position register
DSC2: Data slicer control register 2
bit 6
0
1
0
1
Contents of Caption Data Latch Completion Flag Contents of 16-bit Shift Register
Completion Flag 1
(bit 0 of DSC2)
Line 21
A line specified by
bits 4 to 0 of CPS
Line 21
Line 21
Completion Flag 2
A line specified by
bits 4 to 0 of CPS
A line specified by
bits 4 to 0 of CPS
12.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 12.10.3 are generated by
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
(bit 5 of CPS)
16-bit data of line 21
Invalid
Invalid
16-bit data of a line specified
16-bit data of line 21
16-bit data of line 21
Caption Data
Registers 1, 2
by bits 4 to 0 of CPS
Caption Data
Registers 3, 4
16-bit data of a line specified by
bits 4 to 0 of CPS
Invalid
Invalid
16-bit data of a line specified by
bits 4 to 0 of CPS
Table 12.10.3 Occurence Sources of Interrupt Request
Caption position register
b7
0
1
b6
0
1
0
1
After slicing line 21
After a line specified by bits 4 to 0 of CPS
After slicing line 21
After slicing line 21
Occurence Souces of Interrupt Request at End of Data Slice Line
64
Rev. 1.0
PRELIMINARY
W
r
R
R
R
W
t
e
r
)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.13 Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/213 or
f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
Sync Pulse Counter Registe
b7 b6 b5 b4 b3 b2 b1 b0
Sync pulse counter register (HC) [Address 00E9
B
0
Count value (HC0 to HC4)
to
4
5
Count source (HC5) 0: HSYNC signal
Nothing is assigned. These bits are write disable bits.
6, 7 0
When these bits are read out, the values are “0.”
The latch value can be obtained by reading out the sync pulse counter
register (address 00E916). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 020816).
Figure 12.10.12 shows the structure of the sync pulse counter and
Figure 12.10.13 shows the synchronous signal counter block diagram.
16]
FunctionsNam
1: Composite sync signal
After rese
Indeterminate
R
—
0
—
Fig. 12.10.12 Sync Pulse Counter Register
13
f(XIN)/2
Composite
sync signal
HSYNC signal
Selection gate : connected to black
side when reset.
b5
Reset
5-bit counte
Latch (5 bits
Counter
Sync pulse
counter register
Data bus
Fig. 12.10.13 Synchronous Signal Counter Block Diagram
Rev. 1.0
65
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
12.11 OSD FUNCTIONS
Table 12.11.1 outlines the OSD functions.
This OSD function can display the following: the block display (32
characters ✕ 16 lines), the SPRITE display. And besides, the function can display the both display at the same time. There are 3 display modes and they are selected by a block unit. The display modes
are selected by block control register i (i = 1 to 16).
The features of each mode are described below.
Table.12.11.1 Features of Each Display Style
Display style
Parameter
CC mode
(Closed caption mode)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
OSD mode
(On-screem display mode)
Block display
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
CDOSD mode
(Color dot on-screen
display mode)
SPRITE display
Number of display characters 32 characters ✕ 16 lines
Dot structure
Kinds of characters
Font memory ROM
Kinds of character sizes
Attribute
Character font
coloring
Character
background coloring
Display layer
OSD output
Display expansion
(multiline display)
Notes1: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
Pre-divide
ratio (Note)
Dot size
2: The character size is specified with dot size and pre-divide ratio (refer to “2.11.3 Dot Size”).
16 ✕ 20 dots
(Character sidplay area:
510 kinds
4 kinds
✕ 1, ✕ 2
1T
C
✕ 1/2H,
1T
C
✕ 1H
Smooth italic,
under line,
flash
1 screen: 8 kinds (per character unit)
Max. 64 kinds
Possible
(a character unit, 1 screen: 4 kinds,
Max. 64 kinds)
Layer 1
Possible (a screen unit, max 64 kinds)Raster coloring
Auto solid space functionFunction
16 ✕ 26 dots)
Analog R, G, B output (each 4 adjustment levels : 64 colors), Digital OUT1, OUT2 output
16 ✕ 20 dots
✕ 1, ✕ 2, ✕ 3
Border
1 screen: 15 kinds (per character unit)
Max. 64 kinds
Possible
(a character unit,1 screen: 15 kinds,
Max. 64 kinds)
Layer 1 and layer 2 Layer 3 (with highest priority)
Triple layer OSD function, window function, blank funtion
Possible
16 ✕ 26 dots
62 kinds
14 kinds
1T
C
✕ 1/2H,
1T
C
✕ 1H,
1.5T
C
✕ 1/2H,
1.5T
C
✕ 1H,
2T
C
✕ 2H,
3T
C
✕ 3H
1 screen: 8 kinds (per dot unit)
1 screen: 15 kinds
(only specified dots are colored
Max. 64 kinds
per character unit)
1 character
16 ✕ 20 dots
1 kind
RAM
8 kinds
✕ 1, ✕ 2
1T
C
✕ 1/2H,
1T
C
✕ 1H,
2T
C
✕ 2H,
3T
C
✕ 3H
1 screen: 8 kinds (per dot unit)
Max. 64 kinds
66
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows
multiple lines (16 lines or more) to be displayed on the screen by
interrupting the display each time one line is displayed and rewriting
data in the block for which display is terminated by software.
OSD mode
16 dots
20 dots
Figure 12.11.1 shows the configuration of OSD character display area.
Figure 12.11.2 shows the block diagram of the OSD circuit. Figure
12.11.3 shows the OSD control register 1. Figure 12.11.4 shows the
block control register i.
CC mode
16 dots
✽
✽
✽
20 dots
26 dots
✽: Displayed only in cc mode.
←Blank area
←Underline area
←Blank area
CDOSD mode
16 dots
26 dots
Fig. 12.11.1 Configuration of OSD Character Display Area
Rev. 1.0
67
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Clock for OSD
OSC1 OSC2
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
H
SYNCVSYNC
Data slicer clock
Display
oscillation
circuit
OSD control circuit
RAM for OSD (SPRITE)
16 dots ✕ 20 dots ✕ 3 planes
Shift register
OSD RAM
18 bits ✕ 32 characters ✕ 16 lines
OSD ROM (charater font)
16 dots ✕ 20 dots ✕ 510 characters
Control register for OSD
OSD port control register
OSD control register 1
Horizontal position register
Block control register i
OSD control register 2
Clock control register
I/O polarity control register
Raster color register
OSD control register 3
Top border control register 1, 2
Bottom border control register 1, 2
Vertical position register 1i, 2i
Color pallet register i
Left border control register 1, 2
Right border control register 1, 2
SPRITE vertical position registers 1, 2
SPRITE horizontal position registers 1, 2
SPRITE OSD control register
(address 00CB
(address 00CE
(address 00CF
(addresses 00D0
(address 0215
(address 0216
(address 0217
(address 0218
(address 0219
16
16
16
16
16
(addresses 021C
(addresses 021D
(addresses 0220
(addresses 0241
0249
(addresses 0250
(addresses 0252
(addresses 0254
(addresses 0256
(addresses 0258
16
)
16
)
16
)
16
)
)
)
)
)
16
16
16
16
16
16
16
16
16
16
, 025116)
, 025316)
, 025516)
, 025716)
)
to 00DF16)
, 021E16)
, 021F16)
to 023F16)
to 024716,
to 024F16)
Shift register
Shift register
OSD ROM (color dot font)
16 dots ✕ 26 dots ✕ 3 planes ✕
62 characters
Shift register
Data bus
Fig. 12.11.2 Block Diagram of OSD Circuit
R G
Output circuit
B
OUT1 OUT2
Rev. 1.0
68
PRELIMINARY
0 : Color signal of character background
After reset
0 : All-blocks display off
(
0 : All bordered
Automatic solid space
(
W
(
)
6, 7
0 0: Logic sum (OR) of layer 1’s
(
)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
OSD Control Register 1
b7b6b5b4 b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD control register 1 (OC1) [Address 00CE
16]
B Name
OSD control bit
0
(OC10) (See note 1)
Scan mode selection
1
bit
OC11)
Border type selection
2
bit
OC12)
Flash mode selection
3
bit
OC13
4
control bit (OC14)
5
Vertical window/blank
control bit (OC15)
Layer mixing control
bits (OC16, OC17)
See note 3
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next VSYNC.
2:Shadow border is output at right and bottom side of the font.
3:OUT2 is always ORed, regardless of values of these bits.
1 : All-blocks display on
0 : Normal scan mode
1 : Bi-scan mode
1 : Shadow bordered (See note 2)
1 : Color signal of character background
0 : OFF
1 : ON
1 : ON
b7 b6
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
Functions
part does not flash
part flashes
color and layer 2’s color
R
W
0
RW
0
RW
0
RW
0
R
RW
0
0RW0 : OFF
0RW
Fig. 12.11.3 OSD Control Register 1
Rev. 1.0
69
PRELIMINARY
0
Indeterminate
B
s
After reset
WRW
Indeterminate
W
Indeterminate
W
Indeterminate
Indeterminate
W
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Block Control Register i
b7b6b5b4b3b2b1b
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Block control register i (BCi) (i=1 to 16) [Addresses 00D016 to 00DF16]
Name Function
0, 1 Display mode
selection bits
(BCi0, BCi1)
b1 b0 Functions
0 0 Display OFF
0 1 OSD mode
1 0 CC mode
1 1 CDOSD mode
2 Border control bit
(BCi2)
3, 4Dot size selection
bits
(BCi3, BCi4)
5, 6Pre-divide ratio
selection bit
(BCi5, BCi6)
7
Nothing is assigned. This bit is a write disable bit.
0 : Border OFF
1 : Border ON
b6 b5 b4 b3 Pre-divide Dot size
0
0
0
1
1
1
1
1
ratio
0
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
✕ 1
1
0
1
✕ 2
0
1
0
1
0
✕ 3
1
0
1
When this bit is read out, the value is indeterminate.
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1.5Tc ✕ 1/2H (See note 3)
1.5Tc ✕ 1H (See note 3)
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
R
R
R
R
R—
Notes 1: Tc : OSD clock cycle divided in pre-divide circuit
2: H : HSYNC
3: This character size is available only in Layer 2. At this time, set layer 1’s
pre-divide ratio = ✕ 2, layer 1’s horizontal dot size = 1Tc.
Fig. 12.11.4 Block Control Register i (i = 1 to 16)
Rev. 1.0
70
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.1 Triple Layer OSD
Three built-in layers of display screens accommodate triple display
of channels, volume, etc., closed caption, and sprite displays within
layers 1 to 3.
The layer to be displayed in each block is selected by bit 0 or 1 of the
OSD control register 2 for each display mode (refer to Figure 12.11.7).
Layer 3 always displays the sprite display.
Table 12.11.2 Mixing Layer 1 and Layer 2
Block
Parameter
Display mode
Pre-divide ratio
Dot size
Horizontal display start position
Vertical display start position
Block in Layer 1
CC, OSD, CDOSD mode
✕ 1, ✕ 2 (CC mode)
✕ 1 to ✕ 3 (OSD, CDOSD mode)
1TC ✕ 1/2H, 1TC ✕ 1H
(CC mode)
1TC ✕ 1H, 1TC ✕ 1/2H,
2TC ✕ 2H, 3TC ✕ 3H
(OSD, CDOSD mode)
Arbitrary
However, when dot size is 2TC ✕ 2H or 2TC ✕ 3H, set difference between vertical display position of
layer 1 and that of layer 2 as follows.
•2TC ✕ 2H: 2H Units
•3TC ✕ 3H: 3H Units
When the layer 1 block and the layer 2 block overlay, the screen is
composed (refer to Figure 12.11.5) with layer mixing by bit 6 or 7 of
the OSD control register 1, as shown in Figure 12.11.3. Layer 3
always takes display priority of layers 1 and 2.
Notes 1: When mixing layer 1 and layer 2, note Table 12.11.2.
2:OUT2 is always ORed, regardless of values of bits 6, 7 of the OSD
control register 1. And besides, even when OUT2 (layer 1 or layer 2)
overlaps with SPRITE display (layer 3), OUT2 is output.
Block in Layer 2
OSD, CDOSD mode
Same as layer 1
Pre-divide ratio = ✕ 1
1TC ✕ 1/2H
1TC ✕ 1H
• Same saize as layer 1
• 1.5TC can be selected only when: layer 1’s pre-divide ratio = ✕ 2
AND layer 1’s horizontal dot size = 1TC.
As this time, vertical dot size is the same as layer 1.
Same position as layer 1
Arbitrary
Pre-divide ratio = ✕ 2
1TC ✕ 1/2H, 1.5TC ✕ 1/2H
1TC ✕ 1H, 1.5TC ✕ 1H
Rev. 1.0
71
PRELIMINARY
A
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Note : When layer 1 and SPRITE display overlay
each other, only OUT2 in layer 1 is output.
Sprite
Layer 3
Fig. 12.11.5 Triple Layer OSD
Display example of layer 1 = “HELLO,” layer 2 = “CH5”
HELLO
Block 9
Block 10
...
Block 15
Block 16
Layer 2
CH5
Block 1
Block 2
...
Block 7
Block 8
Layer 1
R, G, B of layer 1
HELLO
Layer 1
SPRITE
OUT2 of layer 1
CH5
CH5
HELLO
SPRITE
(except transparent)
A'
Logical sum (OR) of
layer 1’s color and
layer 2’s color (See note)
Bit 7 = “0,” bit 6 = “0”
Note: Layer mixing is not logical sum (OR) of colors, but that of each bit of
color pallet register.
Example) When logical sum (OR) is performed on color pallet 1 (0001
pallet 2 (0010
color pallets 1 and 2 contents.
Fig. 12.11.6 Display Example of Triple Layer OSD
Layer 1’s color has priority
Bit 7 = “0”, bit 6 = “1”
2
), the color set to color pallet 3 (00112) is output, regardless of
Layer 2’s color has priority
Bit 7 = “1,” bit 6 = “0”
2
) and color
Rev. 1.0
72
PRELIMINARY
(
)
(
)
(
)
(
)
(
)
Notice: This is not a final specification.
Some paramentic limits are subject to change.
OSD Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD control register 2 (OC2) [Address 0215
16]
B Name Functions
0, 1 0 R W
Display layer
selection bits
(OC20, OC21)
2 R, G, B signal output
selection bit(OC22)
3
Solid space output bit
OC23
Horizotal
4
window/blank coutrol
bit (OC24)
5 Window/blank
selection bit 1
horizontal) (OC25
6 Window/blank
selection bit 2
vertical) (OC26
7 OSD interrupt
request selection bit
OC27
Note: When setting bit 1 of the OSD port control register to “1,” the value which is
converted from the 4-adjustment-level analog to the 2-bit digital is output
regardless of this bit value as follows : the high-order bit (R1, G1 and B1) is
output from pins P5
output from pins P1
function, the low-power dissipation can realize by setting this bit to “0.”
b1 b0 Layer 1 Layer 2
0 0 CC, OSD, CDOSD
0 1 CC, OSD CDOSD
1 0 CC, CDOSD OSD
1 1 CC CDOSD
0: Digital output
1: Analog output (4 gradations)
0: OUT1 output
1: OUT2 output
0: OFF
1: ON
0: Horizontal blank function
1: Horizontal window function
0: Vertical blank function
1: Vertical window function
0: At completion of layer 1 block display
1: At completion of layer 2 block display
2, P53 and P54, and the low-order bit is (R0, G0 and B0)
7, P15 and P16. And besides, when not using OSD
OSD
See note
At reset
R
0RW
0RW
0RW
0R
0R
0R
W
W
W
W
Fig. 12.11.7 OSD Control Register 2
Rev. 1.0
73
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.2 Display Position
The display positions of characters are specified by a block. There
are 16 blocks, blocks 1 to 16. Up to 32 characters can be displayed
in each block (refer to “12.11.6 Memory for OSD”).
The display position of each block can be set in both horizontal and
vertical directions by software.
The display position in the horizontal direction can be selected for all
blocks in common from 256-step display positions in units of 4 TOSC
(TOSC = OSD oscillation cycle).
The display position in the vertical direction for each block can be
selected from 1024-step display positions in units of 1 TH ( TH = HSYNC
cycle).
Blocks are displayed in conformance with the following rules:
• When the display position is overlapped with another block
(Figure 12.11.8 (b)), a lower block number (1 to 16) is displayed on
the front.
• When another block display position appears while one block is .
displayed (Figure 12.11.8 (c)), the block with a larger set value as
the vertical display start position is displayed. However, do not display block with the dot size of 2TC ✕ 2H or 3TC ✕ 3H during display
period (✽) of another block.
✽ In the case of OSD mode block: 20 dots in vertical from the vertical
display start position.
✽ In the case of CC or CDOSD mode block: 26 dots in vertical from
the vertical display start position.
HP
VP11, VP21
VP12, VP22
VP13, VP23
(a) Example when each block is separated
HP
VP11, VP21 = VP12, VP22
(b) Example when block 2 overlaps with block 1
HP
VP11, VP21
VP12, VP22
(c) Example when block 2 overlaps in process of block 1
Block 1
Block 2
Block 3
Block 1
(Block 2 is not displayed)
Block 1
Block 2
Note: VP1i or VP2i (i : 1 to 16) indicates the vertical display start position of display block i.
Fig. 12.11.8 Display Position
74
Rev. 1.0
M37280MF–XXXSP, M37280MK–XXXSP
(
)
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and
HSYNC are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
VSYNC signal input
V
SYNC control
signal in
microcomputer
Period of counting
SYNC signal
H
HSYNC
signal input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
8 machine cycles or more
(Note 2)
8 machine cycles
or more
0.25 to 0.50 [µs]
at f(XIN) = 8MHz
12345
Not count
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
When bits 0 and 1 of the I/O polarity control register
(address 021716) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
Fig. 12.11.9 Supplement Explanation for Display Position
H
SYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2:Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3:The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
Rev. 1.0
75
M37280MF–XXXSP, M37280MK–XXXSP
After reset
Control bits of vertical
Vertical display start positions
Indeterminate
After reset
0, 1
Control bits of vertical
Vertical display start positions
Indeterminate
Indeterminate
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
The vertical position for each block can be set in 1024 steps (where
each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in
vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16)
and values “0016” to “0316” in vertical position register 2i (i = 1 to 16)
(addresses 023016 to 023F16). The vertical position registers are
shown in Figures 12.11.10 and 12.11.11.
Vertical Position Register 1i
b7b6b5b4 b3 b2b1b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 0220
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
16 to 022F16]
B Name Functions
0
display start positions
to
(VP1i0 to VP1i7)
7
(See note 1)
Notes 1: Do not “00
2: T
H is cycle of HSYNC.
3: VP2i is vertical position register 2i.
Fig. 12.11.10 Vertical Position Register 1i (i = 1 to 16)
Vertical Position Register 2i
b7b6b5b4 b3 b2b1b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 0230
B Name Functions
display start positions
(VP2i0, VP2i1)
(See note 1)
(low-order 8 bits)
T
H ✕
(setting value of low-order 2 bits of VP2i ✕16
+ setting value of low-order 4 bits of VP1i ✕16
+ setting value of low-order 4 bits of VP1i ✕160)
16” and “0116” to VP1i at VP2i = “0016.”
(high-order 2 bits)
T
H ✕
(setting value of low-order 2 bits of VP2i ✕16
+ setting value of low-order 4 bits of VP1i ✕16
+ setting value of low-order 4 bits of VP1i ✕160)
2
1
16 to 023F16]
2
1
RW
RW
R
W
RW
Fig. 12.11.11 Vertical Position Register 2i (i = 1 to 16)
76
2
Nothing is assigned. These bits are write disable bits.
to
When these bits are read out, the values are indeterminate.
7
Notes 1: Do not set “0016” and “0116” to VP1i at VP2i = “0016.”
2: T
H is cycle of HSYNC.
3: VP1i is vertical position register 1i.
R—
Rev. 1.0
M37280MF–XXXSP, M37280MK–XXXSP
After reset
r
Control bits of horizontal
Horizontal display start positions
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
The horizontal position is common to all blocks, and can be set in
256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle
for display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal
position register (address 00CF16). The horizontal position register
is shown in Figure 12.11.12.
Horizontal Position Registe
b7b6b5b4 b3 b2b1b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Horizontal position register (HP) [Address 00CF
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
16]
B Name Functions
0
display start positions
to
(HP0 to HP7)
7
Notes 1. The setting value synchronizes with the V
2. T
OSC = OSD oscillation period.
Fig. 12.11.12 Horizontal Position Register
Note : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs be-
tween the horizontal display start position set by the horizontal position
register and the most left dot of the 1st block. Accordingly, when 2 blocks
have different pre-divide ratios, their horizontal display start position
will not match.
Ordinaly, this gap is 1T
gap is 1.5T
C only when the character size is 1.5TC.
C regardless of character sizes, however, the
4TOSC ✕
(setting value of high-order 4 bits ✕ 16
+setting value of low-order 4 bits ✕ 160)
SYNC.
RW
0RW
1
H
SYNC
Note 1
Fig. 12.11.13 Notes on Horizontal Display Start Position
Rev. 1.0
1T
C
1T
4T
OSC
T
def
✕ N
C
1T
1.5T
C
C
Tc
Tosc
Tdef
Block 1 (Pre-divide ratio = 1)
Block 2 (Pre-divide ratio = 2)
Block 3 (Pre-divide ratio = 3)
Block 4 (Pre-divide ratio = 2, character size = 1.5Tc)
: Value of horizontal position register (decimal notation)
N
: OSD clock cycle divided in pre-divide circuit
: OSD oscillation cycle
: 50 Tosc
77
PRELIMINARY
Synchronous
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.3 Dot Size
The dot size can be selected by a block unit. The dot size in vertical
direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock
gained by dividing the OSD clock source (data slicer clock, OSC1,
main clock) in the pre-divide circuit. The clock cycle divided in the
pre-divide circuit is defined as 1TC.
The dot size is specified by bits 6 to 3 of the block control register.
OSC1
circuit
Data
slicer
clock
(See
HSYNC
note)
Note: To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Cycle ✕ 2
Cycle ✕ 3
Pre-divide circuit
Refer to Figure 12.11.4 (the block control register i), refer to Figure
12.11.6 (the clock control register).
The block diagram of dot size control circuit is shown in Figure 12.11.4.
Notes 1: The pre-divide ratio = 3 cannot be used in the CC mode.
2:The pre-divide ratio of the layer 2 must be same as that of the layer 1
by the block control register i.
3:In the bi-scan mode, the dot size in the vertical direction is 2 times as
ompared with the normal mode. Refer to “12.11.13 Scan Mode” about
the scan mode.
Clock cycle
= 1T
C
Horizontal dot size
control circuit
Vertical dot size
control circuit
OSD control circuit
Fig. 12.11.14 Block Diagram of Dot Size Control Circuit
1 dot
1/2H
Fig. 12.11.15 Definition of Dot Sizes
1T
3H
3T
C
Scanning line of F1 (F2)
Scanning line of F2 (F1)
2T
1T
C
C
1H
C
2H
In normal scan mode
Rev. 1.0
78
PRELIMINARY
B
After reset
R
3
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.4 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one
of the following 3 types.
• Data slicer clock output from the data slicer (approximately 26 MHz)
• Clock from the LC oscillator supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator or the quartz-crystal oscillator
from the pins OSC1 and OSC2
The clock for display to be used for OSD can be selected by bit 7 of
port P3 direction register, bit 2 and bit 1 of clock source control register (address 021616). If the pins OSC1 and OSC2 are not used as
OSD clock input/output, these pins can be used as the sub-clock
input/output, or port P6.
Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00 0
0
Clock control register (CS) [Address 0216
Name Functions
0 Clock selection bit
(CS0)
1, 2
OSC1 oscillating mode
selection bits (CS1, CS2)
Table 12.11.2 Setting of P63/OSC1/XCIN, P64/OSC2/XCOUT
Function
Registers
Bit 7 of Port P3
Clock input/
output pins
for OSD
0
Sub-clock
input/
output pins
0
Input port
Direction Register
Clock Control
Register
0: Data slicer clock
1: OSC1 clock
b2 b1
0 0: 32kHz oscillating mode.
0 1: Used as input port of P6
1 0: LC oscillating mode
1 1: Ceramic • quartz-crystal
Bit 2
Bit 1
16]
and P64 (See note 1).
oscillating mode
1
1
0
1
0
0
W
RW
0
RW
0
1
0
1
Fig. 12.11.16 Clock Control Register
3 to 6
Fix these bits to “0.”
70RW
Test bit
(See note 2)
Note 1: Set bit 7 of address 00C716 to “1”, when OSC1 and OSC2 are used as P63
and P64.
2: Be sure to set bit 7 to “0” for program of the mask and the EPROM versions.
For the emulator MCU version (M37280ERSS), be sure to set bit 7 to “1”
when using the data slicer clock for software debugging.
R
0
W
Rev. 1.0
79
PRELIMINARY
“0”“
“
C
O
“
“
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Data slicer
circuit
32kHz
LC
eramic •
quartz-crystal
scillating mode for OSD
Note : To use data slicer clock, set bit 0 of data slicer control register 1 to “1.”
Fig. 12.11.17 Block Diagram of OSD Selection Circuit
00”
10”
CS2, CS1
11”
Data slicer clock
OSC1 clock
(See note)
OSD control circuit
CS0
1”
Rev. 1.0
80
PRELIMINARY
After reset
R
r
RWRWRWR
RWRWRWR
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to Figure 12.11.19) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
I/O Polarity Control Registe
b7 b6 b5 b4 b3 b2 b1 b0
I/O polarity control register (PC) [Address 0217
B Name Functions
0HSYNC input polarity
switch bit (PC0)
1
VSYNC input polarity
switch bit (PC1)
2 R, G, B output polarity
switch bit (PC2)
3
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0”.
4 OUT1 output polarity
switch bit (PC4)
5 OUT2 output polarity
switch bit (PC5)
6 Display dot line selection
bit (PC6) (See note)
12.11.19) in the microcomputer and then comparing this time with
the time of the previous field. When the time is longer than the comparing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field.
The field determination flag changes at a rising edge of VSYNC control signal in the microcomputer.
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 12.11.19).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
16]
W
0 : Positive polarity input
1 : Negative polarity input
0 : Positive polarity input
1 : Negative polarity input
0 : Positive polarity output
1 : Negative polarity output
0 : Positive polarity output
1 : Negative polarity output
0 : Positive polarity output
1 : Negative polarity output
0 : “ ” at even field
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
0
0
0
0
0
0
0
—
Fig. 12.11.18 I/O Polarity Control Register
Rev. 1.0
7 Field determination
flag(PC7)
Note: Refer to Fig. 12.11.19.
0 : Even field
1 : Odd field
1
—
81
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Both H
SYNC
signal and V
SYNC
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
signal are negative-polarity input
SYNC
H
V
SYNC
and
V
SYNC
control
signal
in microcomputer
Upper :
V
SYNC
Lower :
V
SYNC
signal in
microcomputer
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A
1 35 79111315
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
(n–1) field
(Odd-numbered)
T1
(n) field
(Even-numbered)
signal
control
(n+1) field
(Odd-numbered)
24 6810121416
CC mode · CDOSD mode
T2
T3
0.25 to 0.50[µs] at
f(X
IN
) =8 MHz
135791113152 4 6 8 10 12 14 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Field
determination
Field
flag(Note)
Odd
Even
Odd
When the display dot line selection bit is “0,”
the “ ” font is displayed at even field, the
“ ” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
0 (T2 > T1)
1 (T3 < T2)
Display dot line
selection bit
OSDS mode
0
1
0
1
16
) to “0.”
Display dot line
Dot line 1
Dot line 0
Dot line 0
Dot line 1
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V
the microcomputer.
Fig. 12.11.19 Relation Between Field Determination Flag and Display Font
82
SYNC
control signal (negative-polarity input) in
Rev. 1.0
PRELIMINARY
0
0
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.6 Memory for OSD
There are 2 types of memory for OSD : OSD ROM (addresses
1080016 to 157FF16 and 1800016 to 1ACFF16) used to specify character dot data and OSD RAM (addresses 070016 to 07A716 and
080016 to 0FDF16) used to specify the kinds of display characters,
display colors, and SPRITE display. The following describes each
type of memory.
(1) OSD ROM (addresses 1080016 to 157FF16, 1800016 to
1ACFF16)
The dot pattern data for OSD characters is stored in the character font area in the OSD ROM and the CD font data for OSD
characters is stored in the color dot font area in the OSD ROM.
To specify the kinds of the character font and the CD font, it is
necessary to write the character code into the OSD RAM.
The modes are selected by bit 3 of the OSD control register 3 for
each screen.
The character font data storing address is shown in Figure
12.11.20. The CD font data storing address is shown in Figure
2.11.21. The 510 kinds of character font and 62 kinds of CD font
can be stored.
OSD ROM address of character font data
OSD ROM
address bit
Line number /
Character code /
Area bit
Line number = “0216” to “1516”
Character code = “00
Area bit = 0: Left area
1: Right area
For example : The font data of the hatching area of the character code AA16 is 1 0010 1001 0101 0100 2 =1295416
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
1 Line number
16” to “1FF16” (“0FF16” and “10016” can not be used. Write “FF16” to corresponding addresses.)
Character code0
Area
bit
Line
number
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
Fig. 12.11.20 Character Font Data Storing Address
Left area Right area
b7 b
b
b7
Character code AA16
Rev. 1.0
83
PRELIMINARY
0
0
Notice: This is not a final specification.
Some paramentic limits are subject to change.
OSD ROM address of CD font data
OSD ROM
address bit
Line number/CD code/
Area bit
Line number
CD code
Area bit
Example)
Plain 2
(Color pallet selection bit 2)
11111111111111
1
1
11111111111111
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
00000000000011
1
1
100000000000011
1
11111111111111
1
1
1 1111111111111
1
1
AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
11
= “00
16
” to “1916”
16
” to “3F16” (“1F16” and “2016” cannot be used. Write “FF16” to the corresponding address.)
= “00
= 0 : Left area 1 : Right area
“03
16
” is stored to address 1A77516(Plain 2), “C016” is stored to address 1977516(Plain 1), and “F816” is stored to
address 18775
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Plain
0
selection bit
16
(Plain 0) as the font data of the hatching area of the CD code 3A16.
Line number
Plain 1
(Color pallet selection bit 1)
0000000000000000
0000000000000000
0000000000000000
0000000000000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
1000000111000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
“C016”“0316” “F816”
CD code
Plain 0
(Color pallet selection bit 0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
Area
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Line
number
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
Left area Right area
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
CD code 3A
b0b7
b7
4444444444444444
4444444444444444
0000044000440000
0000044000440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
3222044333440222
3222044333440222
3222044333440222
3222044333440222
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
1000044111440000
0000044000440000
0000044000440000
4444444444444444
4444444444444444
b0
16
Fig. 12.11.21 Color Dot Font Data Storing Address
When bit 3 of OSD control
register 3 is “0 (1)”
Color pallet set by RC13 to
0
RC16 of OSD RAM is selected
Color pallet 1 (9) is selected
1
Color pallet 2 (10) is selected
2
3
Color pallet 3 (11) is selected
Color pallet 4 (12) is selected
4
Line
number
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
Left area Right area
b7
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Display example
b
b7
b
Rev. 1.0
84
M37280MF–XXXSP, M37280MK–XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(2) OSD RAM (addresses 070016 to 07A716, 080016 to 0FFF16)
The OSD RAM for SPRITE consisting of 3 planes, is assigned to
addresses 070016 to 07A716. Each plane corresponds to each color
pallet selection bit and the color pallet of each dot is determined from
among 8 kinds.
The OSD RAM for character is allocated at addresses 080016 to
0FFF16, and is divided into a display character code specification
part, color code 1 specification part, and color code 2 specification
part for each block. Tables 2.11.4 and 2.11.5 show the contents of
the OSD RAM.
For example, to display 1 character position (the left edge) in block 1,
write the character code in address 080016, write color code 1 at
082016, and write color code 2 at 084016. The structure of the OSD
RAM is shown in Figure 12.11.23.
Note : For the layer 2 ’s OSD mode block with dot size of 1.5TC ✕ 1/2H and
1.5T
C ✕ 1H, the 3nth (n = 1 to 10) character is skipped as compared
with ordinary block (blocks with dot size of 1T
layer 1). Accordingly, maximum 22 characters are only displayed in 1
block. Blocks with dot size of 1T
the layer 1
However, note the following:
• In OSD mode
The character is not displayed, and only the left 1/3 part of the 22nd
character back ground is displayed in the 22nd’s character area.
When not displaying this background, set transparent for background.
• In CDOSD mode
The character is not displayed, and color pallet color specified by bit
3 to 6 of color code 1 can be output in the 22nd’s character area (left
1/3 part).
The RAM data for the 3nth character does not effect the display.
Any character data can be stored here (refer to Figure 12.11.22).
C ✕ 1/2H and 1TC ✕ 1H, or blocks on
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
C ✕ 1/2H, or blocks on the
MITSUBISHI MICROCOMPUTERS
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Rev. 1.0
85
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Table 12.11.3 Contents of OSD RAM (SPRITE)
Line (from top)
Line 1
Dot (from left)
Dots 1 to 8
Dots 9 to 16
Line 2
Dots 1 to 8
Dots 9 to 16
:
Line 19
:
Dots 1 to 8
Dots 9 to 16
Line 20
Dots 1 to 8
Dots 9 to 16
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
(Color pallet selection bit 0)
Plain 0
070016
070116
070216
070316
:
072416
072516
072616
072716
(Color pallet selection bit 1)
Plain 1
074016
074116
074216
074316
:
076416
076516
076616
076716
(Color pallet selection bit 2)
Plain 2
078016
078116
078216
078316
:
07A416
07A516
07A616
07A716
Plain 2
b7 b0 b7
780
782
7A4
7A6
b0 b7 b0 b7
781 Line 1
783 Line 2
7A5 Line 19
7A7 Line 20
Line
number
Plain 1
740
742
764
766
741 Line 1
743 Line 2
765 Line 19
767 Line 20
Dot number
2345678910111213141516
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Plain 0
b0 b7 b0 b7
700
702
724
726
b0
701 Line 1
703 Line 2
725 Line 19
727 Line 20
Display
sequence
RAM
address
order
Display
sequence
RAM
address
order
11223445576871081191310141116121713191420152216231725182619282029213122
1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132
1 2 3 4 5 6 7 8 9 1011121314151617181920212223 242526272829303132
Fig. 12.11.22 RAM Data for 3nth Character
86
• 1.5Tc size block
32
• 1Tc size block
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Table 12.11.14 Contents of OSD RAM (Character)
Block
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 8
Block 9
Block 10
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Character Code Specification
080016
080116
:
081E16
081F16
088016
088116
:
089E16
089F16
090016
090116
:
091E16
091F16
098016
098116
:
099E16
099F16
0A0016
0A0116
:
0A1E16
0A1F16
0A8016
0A8116
:
0A9E16
0A9F16
0B0016
0B0116
:
0B1E16
0B1F16
0B8016
0B8116
:
0B9E16
0B9F16
0C0016
0C0116
:
0C1E16
0C1F16
0C8016
0C8116
:
0C9E16
0C9F16
Color Code 1 Specification
082016
082116
:
083E16
083F16
08A016
08A116
:
08BE16
08BF16
092016
092116
:
093E16
093F16
09A016
09A116
:
09BE16
09BF16
0A2016
0A2116
:
0A3E16
0A3F16
0AA016
0AA116
:
0ABE16
0ABF16
0B2016
0B2116
:
0B3E16
0B3F16
0BA016
0BA116
:
0BBE16
0BBF16
0C2016
0C2116
:
0C3E16
0C3F16
0CA016
0CA116
:
0CBE16
0CBF16
Color Code 2 Specification
084016
084116
:
085E16
085F16
08C016
08C116
:
08DE16
08DF16
094016
094116
:
095E16
095F16
09C016
09C116
:
09DE16
09DF16
0A4016
0A4116
:
0A5E16
0A5F16
0AC016
0AC116
:
0ADE16
0ADF16
0B4016
0B4116
:
0B5E16
0B5F16
0BC016
0BC116
:
0BDE16
0BDF16
0C4016
0C4116
:
0C5E16
0C5F16
0CC016
0CC116
:
0CDE16
0CDF16
Rev. 1.0
87
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Table 12.11.15 Contents of OSD RAM (continued)
Block
Block 11
Block 12
Block 13
Block 14
Block 15
Block 16
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
Character Code Specification
0D0016
0D0116
:
0D1E16
0D1F16
0D8016
0D8116
:
0D9E16
0D9F16
0E0016
0E0116
:
0E1E16
0E1F16
0E8016
0E8116
:
0E9E16
0E9F16
0F0016
0F0116
:
0F1E16
0F1F16
0F8016
0F8116
:
0F9E16
0F9F16
Color Code 1 Specification
0D2016
0D2116
:
0D3E16
0D3F16
0DA016
0DA116
:
0DBE16
0DBF16
0E2016
0E2116
:
0E3E16
0E3F16
0EA016
0EA116
:
0EBE16
0EBF16
0F2016
0F2116
:
0F3E16
0F3F16
0FA016
0FA116
:
0FBE16
0FBF16
Color Code 2Specification
0D4016
0D4116
:
0D5E16
0D5F16
0DC016
0DC116
:
0DDE16
0DDF16
0E4016
0E4116
:
0E5E16
0E5F16
0EC016
0EC116
:
0EDE16
0EDF16
0F4016
0F4116
:
0F5E16
0F5F16
0FC016
0FC116
:
0FDE16
0FDF16
88
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Note: Do not read from/write to the addresses in Table 12.11.6.
Table 12.11.6 List of Access Disable Addresses
086016to 087F
08E010to 08FF
096016to 097F
09E016to 09FF
0A6016to 0A7F
0AE016to 0AFF
0B6016to 0B7F
0BE016to 0BFF
16
16
16
16
16
16
16
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
0C60
0CE0
0D60
0DE0
0E60
0EE0
0F60
0FE0
16
to 0C7F
16
to 0CFF
16
to 0D7F
16
to 0DFF
16
to 0E7F
16
to 0EFF
16
to 0F7F
16
to 0FFF
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
and ON-SCREEN DISPLAY CONTROLLER
16
16
16
16
16
16
16
16
Rev. 1.0
89
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Blocks 1 to 16
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
b0
b1
b0b7b0b7
Bit
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RF6 RF5 RF4 RF3 RF2 RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10RF7
CC mode
Bit name Function
Character code
(Low-order 8 bits)
Character code
(High-order 1 bits)
Color pallet
selection bit 0
Character
Color pallet
selection bit 1
Color pallet
selection bit 2
Italic control
Flash control
Underline control
pallet for character
0: Italic OFF
1: Italic ON
0: Flash OFF
1: Flash ON
0: Underline OFF
1: Underline ON
Specify
character code
in OSD ROM
(See note 3)
Specify color
(See note 5)
OSD mode CDOSD mode
Bit name Function
Character
code (Low-
order 8 bits)
Character code
(High-order 1 bits)
Color pallet
selection bit
Character
Color pallet
selection bit
Color pallet
selection bit
Color pallet
selection bit 3
Character background
Color pallet
selection bit 0
Color pallet
selection bit 1
character code in
pallet for character
Specify color pallet
Color code 1Character code
Specify
OSD ROM
(See note 3)
Specify color
(See note 5)
for background
(See note 5)
RC21 RC20
Color code 2
Bit name Function
CD code
(6 bits)
Not used
Color pallet
selection bit 0
Color pallet
Dot color
selection bit 1
Color pallet
selection bit 2
Color pallet
selection bit 3
character code
in OSD ROM
Specify a dot
which selects
color pallet 0 or 8
by OSD ROM
Specify
(color dot)
(See note 4)
(See note 6)
RC17
OUT2 output
control
Character background
RC20
RC21
Notes 1: Read value of bits 2 to 7 of the color code 2 is undefined.
2: For “not used” bits, the write value is read.
3: Do not use character code “0FF16,” “10016.”
4: Do not use character code “1F16,” “2016.”
5: Refer to Figure 12.11.24.
6: Only CDOSD mode, a dot which selects color pallet 0 or 8 is colored to the color pallet set by RC13 to RC16 of OSD RAM
Fig. 12.11.23 Structure of OSD RAM
90
Color pallet
selection bit 0
Color pallet
selection bit 1
in character units.
0: OUT2 output OFF
1: OUT2 output ON
Specify color pallet
for background
(See note 5)
OUT2 output
control
Character background
selection bit 2
selection bit 3
Color pallet
Color pallet
0: OUT2 output OFF
1: OUT2 output ON
Specify color pallet
for background
(See note 5)
OUT2 output
control
Not used
0: OUT2 output OFF
1: OUT2 output ON
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.7 Character Color
As shown in Figure 2.11.24, there are 16 built-in color pallets. Color
pallet 0 is fixed at transparent, and color pallet 8 is fixed at black.
The remaining 14 colors can be set to any of the 64 colors available.
The setting procedure for character colors is as follows:
• CC mode................................. 8 kinds
Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be
selected by bit 0 of the OSD control register 3 (address 021916).
Color pallets are set by bits RC11 to RC13 of the OSD RAM from
among the selection range.
• OSD mode .............................. 15 kinds
Color pallets are set by bits RC11 to RC14 of the OSD RAM.
• CDOSD mode ......................... 8 kinds
Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be
selected by bit 3 of the OSD control register 3 (address 021916).
Color pallets are set in dot units according to the CD font data (the
OSD RAM<color dot font> contents)from among the selection
range.
Only in CDOSD mode, a dot which selects color pallet 0 or 8 is
colored to the color pallet set by RC13 to RC16 of OSD RAM in
character units.
• SPRITE display....................... 8 kinds
Color pallet selection range (color pallets 0 to 7 or 8 to 15) can be
selected by bit 4 of the OSD control register 3 (address 021916).
Color pallets are set in dot units according to the CD font data (the
OSD RAM<color dot font> contents) from among the selection
range.
12.11.8 Character Background Color
The display area around the characters can be colored in with a character background color. Character background colors are set in
character units.
• CC mode................................. 4 kinds
Color pallet selection range (color pallets 0 to 3, 4 to 7, 8 to 11, or
12 to 15) can be selected by bits 1 and 2 of the OSD control
register 3 (address 021916). Color pallets are set by bits RC20
and RC21 of the OSD RAM from among the selection range.
• OSD mode .............................. 15 kinds
Color pallets are set by bits RC15, RC16, RC20, and RC21 of the
OSD RAM.
Note : The character background is displayed in the following part:
(character display area) – (character font) – (border).
Accordingly, the character background color and the color signal for
these two sections cannot be mixed.
Notes 1: Color pallet 8 is always selected for bordering and solid space output
(OUT 1 output) regardless of the set value in the register.
2:Color pallet 0 (transparent) and the transparent setting of other color
pallets will differ. When there are multiple layers overlapping (on top
of each other, piled up), and the priority layer is color pallet 0 (transparent), the bottom layer is displayed, but if the priority layer is the
transparent setting of any other color pallet, the background is displayed without displaying the bottom layer (refer to Figure 12.11.26).
Rev. 1.0
91
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Color pallet 0 (Transparent)
Color pallet 1
Color pallet 2
Color pallet 3
Color pallet 4
Color pallet 5
Color pallet 6
Color pallet 7
Color pallet 8 (Black)
Color pallet 9
Color pallet 10
Color pallet 11
Color pallet 12
Color pallet 13
Color pallet 14
Color pallet 15
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(See note 1) (See note 1)
CC mode
(background)
Select one
color pallet in
screen units.
CC mode (character)
SPRITE display
CDOSD mode (character)
(See note 2)
Select either
color pallet in
screen units.
OSD mode
(character,
background)
Any color pallet
can be
selected.
Notes 1: Color pallets are selected by OSD control register 3 (address 0219
Fig. 12.11.24 Color Code Selection
16
).
2: Only in CDOSD mode, a dot which selects color pallet 0 or 8 is colored to
of OSD RAM in character units.
92
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Dot area specified to color pallet 1
Dot area specified to color pallet 0 When setting black and blue to color pallets 1 and 2, respectively
Fig. 12.11.25 Set of Color Pallet 0 or 8 in CDROM Mode
Color pallet 1 (Transparent)
Layer 1
(CC mode)
26 dots
Set values of OSD RAM (RC16 to RC13)
0000
0001 0010
(only in CDOSD mode).
Color pallet 0 (Transparent)
Transparent
Black
Blue
Black
Blue
Color pallet 2 (Blue)
Layer 2
(OSD mode)
Fig. 12.11.26 Difference Between Color Code 0 (Transparent) and Transparent Setting of Other Color Codes
Rev. 1.0
20 dots
Color pallet 8 (Black)
20 dots
26 dots
When layer 1 has priority.
Transparent
(video signal)
93
PRELIMINARY
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
After reset
After reset
Notice: This is not a final specification.
Some paramentic limits are subject to change.
OSD Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD control register 3 (OC3) [Address 0219
16]
Fig. 12.11.27 OSD Control Register 3
Color Pallet Register i
b7 b6 b5 b4 b3 b2 b1 b0
B Name Functions
0 CC mode character color
selection bit (OC30)
CC mode character
1, 2
background color
selection bits
(OC31, OC32)
(See note)
30RW
CDOSD mode character
color selection bit (OC33)
4
SPRITE color selection
bit (OC34)
5
control bit (OC35)
CC mode window
control bit (OC36)
CDOSD mode window
control bit (OC37)
Note: Color pallet 8 is always selected for solid space (when OUT1 output is selected),
regardress of value of this register.
Color pallet register i (CRi) (i 1 to 7, 9 to15) [Addresses 024116 to 024716, 024916 to 024F16]
0: Color code 0 to 7
1: Color code 8 to 15
b1 b1
0 0: Color code 0 to 3
0 1: Color code 4 to 7
1 0: Color code 8 to 11
1 1: Color code 12 to 15
0: Color code 0 to 7
1: Color code 8 to 15
0: Color code 0 to 7
1: Color code 8 to 15
0: Window OFF
1: Window ON
0: Window OFF
1: Window ON
0: Window OFF
1: Window ON
R
W
0RW
0RW
R
W
0
0W
ROSD mode window
W6R
0
W7R
0
B Name Functions
0, 1 R signal output control
bits (CRi0, CRi1)
G signal output control
2, 3
bits (CRi2, CRi3)
4, 5
B signal output control
bits (CRi4, CRi5)
OUT1 signal output
6
control bit (CRi6)
7
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is indeterminate.
Note: When selecting digital output, the output is VCC at all values other than “00.”
Fig. 12.11.28 Color Pallet Register i (i = 1 to 7, 9 to 15)
b0 b1
0 0: No output (See note)
0 1: 1/3 V
1 0: 2/3 VCC
1 1: VCC
b3 b2
0 0: No output (See note)
0 1: 1/3 V
1 0: 2/3 VCC
1 1: VCC
b5 b4
0 0: No output (See note)
0 1: 1/3 V
1 0: 2/3 VCC
1 1: VCC
0: No output
1: Output
CC
CC
CC
R
W
RW
RW
RW
W
R
—
R
Rev. 1.0
94
PRELIMINARY
(See note)
signa
signa
Border output control
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.11.9 OUT1, OUT2 Signals
The OUT1, OUT2 signals are used to control the luminance of the
video signal. The output waveform of the OUT1, OUT2 signals is
controlled by bit 6 of the color code register i (refer to Figure 86), bits
Conditions
OUT1
l
OUT2 output
control
(RC 17 of
OSD RAM)
~
bit (See note)
(Bit 2 of block control
register i)
0
1
OUT1 control bit
(b6 of color pallet register i)
Background
0
1
0
1
2 and 7 of the block control register i (refer to Figure 63) and RC17 of
OSD RAM. The setting values for controlling OUT1, OUT2 and the
corresponding output waveform is shown in Figure 12.11.29
Output
Character
waveform
0
1
0
1
0
1
0
1
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
0
OUT2
l
1
Notes 1: This control is only valid in the OSD mode. It is invalid in CC/CDOSD mode .
2: In the CDOSD mode, coloring is performed for each dot. Accordingly, OUT1 outputs to dots
which bit 6 of the color pallet register i is set to “0.”
3: OUT2 cannot be output in sprite OSD.
4: ✕ is an arbitrary value.
✕
✕
✕
✕
✕
✕
H
L
H
L
Fig. 12.11.29 Setting Value for Controlling OUT1, OUT2 and Corresponding Output Waveform
Rev. 1.0
95
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.1 1.10 Attribute
The attributes (flash, underline, italic) are controlled to the character
font. The attributes to be controlled are different depending on each
mode.
CC mode .................... Flash, underline, italic for each character
OSD mode ................. Border (all bordered, shadow bordered can
be selected) for each block
(1) Under line
The underline is output at the 23rd and 24th lines in vertical direction only in the CC mode. The underline is controlled by RC16
of OSD RAM. The color of underline is the same color as that of
the character font.
(2) Flash
The parts of the character font, the underline, and the character
background are flashed only in the CC mode. The flash for each
character is controlled by RC15 of OSD RAM. The ON/OFF for
flash is controlled by bit 3 of the OSD control register 1 (refer to
Figure 12.11.3). When this bit is “0”, only character font and underline flash. When “1”, for a character without solid space output, R, G, B and OUT1 (all display area) flash, for a character
with solid space output, only R, G and B (all display area) flash.
The flash cycle bases on the VSYNC count.
<NTSC method>
· VSYNC cycle ✕ 48 ≈ 800 ms (at flash ON)
· VSYNC cycle ✕ 16 ≈ 267 ms (at flash OFF)
Notes 1: When setting both the italic and the flash, the italic character flashes.
2:When a flash character (with flash character background) ajoin on
the right side of a non-flash italic character, parts out of the non-flash
italic character is also flashed.
3:OUT2 is not flashed.
4:When the pre-divide ratio = 1, the italic character with slant of 1 dot ✕
5 steps is displayed (refer to Figure 12.11.30 (c)). When the predivide ratio = 2, the italic character with slant of 1/2 dot ✕ 10 steps is
displayed (refer to Figure 12.11.30 (d)).
5:The boundary of character color is displayed in italic. However, the
boundary of character background color is not affected by the italic
(refer to Figure 12.11.31).
6:The adjacent character (one side or both side) to an italic character is
displayed in italic even when the character is not specified to display
in italic (refer to Figure 12.11.31).
7:When displaying the 32nd character in the italic and when solid space
is off (OC14 = “0”), parts out of character area is not displayed.
8:When displaying the italic character in the block with the pre-divide
ratio = 1, set the OSD clock frequency to 11 MHz to 14 MHz.
(3) Italic
The italic is made by slanting the font stored in OSD ROM to the
right only in the CC mode. The italic is controlled by RC14 of OSD
RAM.
The display example of attribute is shown in Figure 12.11.31. In this
case, “R” is displayed.
96
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
( a ) O r d i n a r y
C o l o r c o d e 1
B i t 6B i t 4
0
0
C o l o r c o d e 1
B i t 6
0
B i t 4
1
( b ) U n d e r l i n e
C o l o r c o d e 1
B i t 6B i t 4
10
C o l o r c o d e 1
B i t 6
1
B i t 4
1
( c ) I t a l i c
f l a s h f l a s h
O N
O F F
( e ) U n d e r l i n e a n d I t a l i c a n d f l a s h
Fig. 12.11.30 Example of Attribute Display (in CC Mode)
Rev. 1.0
O F F
( d ) U n d e r l i n e a n d I t a l i c
f l a s h
O N
B i t 4
( R C 1 6 )
1
C o l o r c o d e
B i t 5
( R C 1 5 )
1
B i t 6
( R C 1 6 )
1
97
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(Refer to “12.11.10 Note 6”) (Refer to “12.11.10 Note 6”)
Bit 4 of color
code 1
Fig. 12.11.31 Example of Italic Display
10 0 1 1 0 1
Notes 1 : The dotted line is the boundary of character color.
2:When bit 4 of OSD control register 1 is “0.”
32nd chracter26th chracter
98
Rev. 1.0
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(4) Border
The border is output only in the OSD mode. The all bordered
(bordering around of character font) and the shadow bordered
(bordering right and bottom sides of character font) are selected
(refer to Figure 12.11.31) by bit 2 of the OSD control register 1
(refer to Figure 12.11.3). The ON/OFF switch for borders can be
controlled in block units by bit 2 of the block control register i
(refer to Figure 12.11.4).
The OUT1 signal is used for border output. The border color is
fixed at color code 8 (block). The border color for each screen is
specified by the border color register i.
The horizontal size (x) of border is 1TC (OSD clock cycle divided
in the pre-divide circuit) regardless of the character font dot size.
However , only when the pre-divide ratio = 2 and character size =
1.5TC, the horizontal size is 1.5TC. The vertical size (y) different
depending on the screen scan mode and the vertical dot size of
character font.
Notes 1: The border dot area is the shaded area as shown in
Figure 12.11.34.
2:When the border dot overlaps on the next character font, the charac-
ter font has priority (refer to Figure 12.11.35 A). When the border dot
overlaps on the next character back ground, the border has priority
(refer to Figure 12.11.35 B).
3:The border in vertical out of character area is not displayed (refer to
Figure 12.11.35).
All bordered Shadow bordered
Fig. 12.11.32 Example of Border Display
y
x
Scan mode
Border
dot size
Horizontal size (x)
Vertical size (y)
Fig. 12.11.33 Horizontal and Vertical Size of Border
Vertical dot size of
character font
Normal scan mode Bi-scan mode
1/2H 1H, 2H, 3H 1/2H, 1H, 2H, 3H
1T
C (OSD clock cycle divided in pre-divide circuit)
1.5TC when selecting 1.5TC for character size.
1/2H 1H 1H
Rev. 1.0
99
PRELIMINARY
s
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Character
font area
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD mode
16 dot
20 dots
Fig. 12.11.34 Border Area
1 dot width of border
Character boundaryBCharacter boundaryACharacter boundary
1 dot width of border
B
Fig. 12.11.35 Border Priority
100
Rev. 1.0
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