Mitsubishi M2V56S40AKT-7, M2V56S40AKT-6, M2V56S40AKT-5, M2V56S20AKT-7, M2V56S20AKT-6 Datasheet

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Single Data Rate

MITSUBISHI LSIs

July '01

256M Synchronous DRAM

Some of contents are subject to change without notice.

DESCRIPTION

M2V56S20AKT is a 4-bank x 16777216-word x 4-bit,
M2V56S30AKT is a 4-bank x 8388608-word x 8-bit,
M2V56S40AKT is a 4-bank x 4194304-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of
CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6),
166MHz(-5) and are suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3v±0.3V power supply

- Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2>

- Fully Synchronous operation referenced to clock rising edge

- Single Data Rate

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/full page (programmable)

- Burst type- sequential / interleave (programmable)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- LVTTL Interface

- 10.65mm width x 13.1mm length, 64-pin STSOP(II) with 0.4mm lead pitch

Max. Frequency

@CL2

M2V56S20/30/40AKT-5

Max. Frequency

@CL3

Standard

PC133 (CL2)166 MHz133 MHz

M2V56S20/30/40AKT-6

M2V56S20/30/40AKT-7

100MHz

100 MHz

133 MHz

100MHz

MITSUBISHI ELECTRIC

PC133 (CL3)

PC100 (CL2)

1

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Single Data Rate

MITSUBISHI LSIs

July '01

VDD VDD VDD

NC DQ0 DQ0

VDDQ VDDQ VDDQ

NC NC DQ1

DQ0 DQ1 DQ2

VSSQ VSSQ VSSQ

NC NC DQ3
NC DQ2 DQ4

VDDQ VDDQ VDDQ

NC NC DQ5

DQ1 DQ3 DQ6

VSSQ VSSQ VSSQ

NC NC DQ7
NC NC NC
NC NC NC
NC NC NC

VDD VDD VDD

NC NC NC
NC NC LDQM

/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS

/CS /CS /CS

NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1

A10/AP A10/AP A10/AP

A0 A0 A0

A1 A1 A1

A2 A2 A2
A3 A3 A3

VDD VDD VDD

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

TOP VIEW

x4
x8

x16

256M Synchronous DRAM

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
DQ14 NC NC
DQ13 DQ6 DQ3

VDDQ VDDQ VDDQ

DQ12 NC NC
DQ11 DQ5 NC

VSSQ VSSQ VSSQ

DQ10 NC NC

DQ9 DQ4 DQ2

VDDQ VDDQ VDDQ

DQ8 NC NC

NC NC NC
NC NC NC
NC NC NC
NC NC NC

VSS VSS VSS

UDQM DQM DQM

NC NC NC
CLK CLK CLK
CKE CKE CKE

NC NC NC

A12 A12 A12
A11 A11 A11

A9 A9 A9
A8 A8 A8
A7 A7 A7
A6 A6 A6
A5 A5 A5
A4 A4 A4

VSS VSS VSS

CLK : Master Clock
CKE : Clock Enable
/CS : Chip Select
/RAS : Row Address Strobe

/CAS : Column Address Strobe
/WE : Write Enable
DQ0-15 : Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12 : Address Input
BA0,1 : Bank Address Input

Vdd : Power Supply
VddQ : Power Supply for Output
Vss : Ground
VssQ : Ground for Output

MITSUBISHI ELECTRIC

2

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

BLOCK DIAGRAM

/CS

/RAS

/CAS

/WE

DQMU/L

Control Circuitry

Address Buffer

A0-12

BA0,1

CLK

CKE

Control Signal Buffer

Single Data Rate

MITSUBISHI LSIs

July '01

Memory

Array

Bank #0

Mode Register

I/O Buffer

Memory

Array

Bank #1

256M Synchronous DRAM

DQ0-3 (x4), 0-7 (x8), 0 - 15 (x16)

Memory

Array

Bank #2

Memory

Array

Bank #3

Type Designation Code

M 2 V 56 S 4 0 A KT - 5

Clock Buffer

This rule is applied to only Synchronous DRAM family.

Speed Grade 5: 166MHz@CL3, 133MHz@CL2

6: 133MHz@CL3, 100MHz@CL2
7: 100MHz@CL2

Package Type KT: STSOP(II)

Process Generation A:2nd. gen.
Function Reserved for Future Use

Organization 2n 2: x4, 3: x8, 4: x16

SDRAM Data Rate Type S:Single Data Rate

Density 56: 256M bits
Interface V:LVTTL
Memory Style (DRAM)
Mitsubishi Main Designation

MITSUBISHI ELECTRIC

3

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Din Mask / Output Disable: When DQMU/L is high in burst write, Din for

PIN FUNCTION

Single Data Rate

MITSUBISHI LSIs

July '01

CLK

CKE

/RAS, /CAS, /WE

A0-12

Input

Input

Input

256M Synchronous DRAM

Master Clock: All other inputs are referenced to the rising edge of CLK.Input

Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto
/ self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.

Chip Select: When /CS is high, any command means No OperationInput/CS

Combination of /RAS, /CAS, /WE defines basic commands.

A0-12 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-12. The Column Address is
specified by A0-9,11. A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is
performed. When A10 is high at a precharge command, all banks are
precharged.

BA0,1

DQ0-15

DQM

DQMU/L

Vdd, Vss

VddQ, VssQ

Input

Input / Output

Input

Power Supply

Power Supply

Bank Address: BA0,1 specifies one of four banks to which a command
is applied. BA0,1 must be set with ACT, PRE, READ, WRITE
commands.

Data In and Data out are referenced to the rising edge of CLK.

the current cycle is masked. When DQMU/L is high in burst read, Dout
is disabled at the next but one cycle.

Power Supply for the memory array and peripheral circuitry.

VddQ and VssQ are supplied to the Output Buffers only.

MITSUBISHI ELECTRIC

4

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Single Data Rate

MITSUBISHI LSIs

July '01

256M Synchronous DRAM

BASIC FUNCTIONS

The M2V56S20/30/40AKT provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at
CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and
precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.

CLK
/CS
/RAS
/CAS
/WE
CKE
A10

Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command

define basic commands

Activate (ACT) [/RAS =L, /CAS =/WE =H]

ACT command activates a row in an idle bank indicated by BA.

Read (READ) [/RAS =H, /CAS =L, /WE =H]

READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto­precharge,READA)

Write (WRITE) [/RAS =H, /CAS =/WE =L]

WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge, WRITEA).

Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]

PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA ).

Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]

REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.

MITSUBISHI ELECTRIC

5

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

COMMAND TRUTH TABLE

CKE

Single Data Rate

MITSUBISHI LSIs

July '01

COMMAND MNEMONIC

Deselect DESEL H X H X X X X X X

No Operation NOP H X L H H H X X X

Row Address Entry &

Bank Activate

Single Bank Precharge PRE H X L L H L V L X

Precharge All Banks PREA H X L L H L H X

Column Address Entry

& Write

Column Address Entry

& Write with

Auto-Precharge

Column Address Entry

& Read

ACT H X L L H H V V V

WRITE H X L H L L V L V

WRITEA H X L H L L V H V

READ H X L H L H V L V

n-1

CKE

n

/CS /RAS /CAS /WE BA0,1

256M Synchronous DRAM

A10

A0-9,

/AP

11-12

X

note

Column Address Entry

& Read with

Auto-Precharge

Auto-Refresh REFA H H L L L H X X X

Self-Refresh Entry REFS H L L L L H X X X

Self-Refresh Exit REFSX

Burst Terminate TBST H X L H H L X X X

Mode Register Set MRS H X L L L L L L V

H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number

NOTE:

1. A7-9,11-12=L, A0-A6 =Mode
Address

READA H X L H L H V H V

L H H X X X X X X
L H L H H H X X X

1

MITSUBISHI ELECTRIC

6

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Single Data Rate

MITSUBISHI LSIs

July '01

FUNCTION TRUTH TABLE

Current State

IDLE

ROW ACTIVE

/CS /RAS /CAS /WE Address Command Action

H X X X X DESEL NOP

L H H H X NOP NOP
L H H L X TBST ILLEGAL*2

L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10 PRE / PREA NOP*4
L L L H X REFA Auto-Refresh*5

L L L L

H X X X X DESEL NOP

L H H H X NOP NOP
L H H L X TBST NOP

L H L H BA, CA, A10 READ / READA

Op-Code,
Mode-Add

256M Synchronous DRAM

MRS Mode Register Set*5

Begin Read, Latch CA,
Determine Auto-Precharge

READ

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10 PRE / PREA Precharge / Precharge All
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST Terminate Burst

L H L H BA, CA, A10 READ / READA

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge

Op-Code,
Mode-Add

WRITE /

WRITEA

MRS ILLEGAL

WRITE /

WRITEA

Begin Write, Latch CA,
Determine Auto-Precharge

Terminate Burst, Latch CA,
Begin New Read, Determine
Auto-Precharge*3

Terminate Burst, Latch CA,
Begin Write, Determine Auto­Precharge*3

L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

MITSUBISHI ELECTRIC

MRS ILLEGAL

7

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

FUNCTION TRUTH TABLE (continued)

Single Data Rate

MITSUBISHI LSIs

July '01

Current State /CS /RAS /CAS /WE Address Command Action

WRITE H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST Terminate Burst

L H L H BA, CA, A10 READ / READA

WRITE /

WRITEA

MRS ILLEGAL

READ with

AUTO

PRECHARGE

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10 PRE / PREA Terminate Burst, Precharge

L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

Op-Code,
Mode-Add

256M Synchronous DRAM

Terminate Burst, Latch CA,
Begin Read, Determine Auto-

Precharge*3
Terminate Burst, Latch CA,

Begin Write, Determine Auto­Precharge*3

WRITE with

AUTO

PRECHARGE

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2

L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Continue Burst to END)

L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL

L H L L BA, CA, A10

L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

Op-Code,
Mode-Add

WRITE /

WRITEA

MRS ILLEGAL

WRITE /

WRITEA

MRS ILLEGAL

ILLEGAL

ILLEGAL

MITSUBISHI ELECTRIC

8

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

FUNCTION TRUTH TABLE (continued)

Single Data Rate

MITSUBISHI LSIs

July '01

Current State /CS /RAS /CAS /WE Address Command Action

PRE -

CHARGING

ROW

ACTIVATING

H X X X X DESEL NOP (Idle after tRP)

L H H H X NOP NOP (Idle after tRP)
L H H L X TBST ILLEGAL*2

L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP)
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Row Active after tRCD)

L H H H X NOP NOP (Row Active after tRCD)
L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2

Op-Code,
Mode-Add

MRS ILLEGAL

256M Synchronous DRAM

WRITE RE­COVERING

L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP

L H H H X NOP NOP
L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10 READ / WRITE ILLEGAL*2
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10 PRE / PREA ILLEGAL*2
L L L H X REFA ILLEGAL

L L L L

Op-Code,
Mode-Add

Op-Code,
Mode-Add

MRS ILLEGAL

MRS ILLEGAL

MITSUBISHI ELECTRIC

9

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

FUNCTION TRUTH TABLE (continued)

Single Data Rate

MITSUBISHI LSIs

July '01

Current State /CS /RAS /CAS /WE Address Command Action

RE-

FRESHING

MODE

REGISTER

SETTING

H X X X X DESEL NOP (Idle after tRC)

L H H H X NOP NOP (Idle after tRC)
L H H L X TBST ILLEGAL

L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

H X X X X DESEL NOP (Idle after tRSC)

L H H H X NOP NOP (Idle after tRSC)
L H H L X TBST ILLEGAL
L H L X BA, CA, A10 READ / WRITE ILLEGAL
L L H H BA, RA ACT ILLEGAL

Op-Code,
Mode-Add

MRS ILLEGAL

256M Synchronous DRAM

L L H L BA, A10 PRE / PREA ILLEGAL
L L L H X REFA ILLEGAL

L L L L

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration

NOTES:

1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.

2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending
on the state of that bank.

3. Must satisfy bus contention, bus turn around, write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.

5. ILLEGAL if any bank is not idle.

ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Op-Code,
Mode-Add

MRS ILLEGAL

MITSUBISHI ELECTRIC

10

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

FUNCTION TRUTH TABLE for CKE

Single Data Rate

MITSUBISHI LSIs

July '01

Current State

SELF-

REFRESH*1

POWER

DOWN

ALL BANKS

IDLE*2

256M Synchronous DRAM

CKE

CKE

n-1

H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
L H L H H H X Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
H X X X X X X INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh

/CS /RAS /CAS /WE Add Action

n

H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State =Power Down

ANY STATE

other than

listed above

ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care

NOTES:

1. CKE Low to High transition will re-enable CLK and other inputs asynchronously .
A minimum setup time must be satisfied before any command other than EXIT.

2. Self-Refresh can be entered only from the All Banks Idle State.

3. Must be legal command.

H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Suspend at Next Cycle*3
L H X X X X X Exit CLK Suspend at Next Cycle*3
L L X X X X X Maintain CLK Suspend

MITSUBISHI ELECTRIC

11

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

SIMPLIFIED STATE DIAGRAM

REGISTER

ACTIVE

Single Data Rate

MITSUBISHI LSIs

July '01

MODE

SET

CLK

SUSPEND

MRS

CKEL

IDLE

ACT

REFS

CKEH

REFSX

REFA

CKEL

256M Synchronous DRAM

SELF

REFRESH

AUTO

REFRESH

POWER

DOWN

WRITE

SUSPEND

WRITEA

SUSPEND

POWER
APPLIED

CKEH

ROW

TBST TBST

WRITE

PRE

WRITEA

READ

WRITE

WRITEA

PRE

PRE PRE

PRE

CHARGE

CKEL

WRITE

CKEH

WRITEA READA

CKEL

WRITEA

CKEH

POWER

ON

READ

READA

READ

READA

READA

CKEL

CKEH

CKEL

CKEH

READ

SUSPEND

READA

SUSPEND

MITSUBISHI ELECTRIC

Automatic Sequence
Command Sequence

12

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

POWER ON SEQUENCE

Single Data Rate

MITSUBISHI LSIs

July '01

256M Synchronous DRAM

Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.

1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the
inputs.

2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs.

3. Issue precharge commands for all banks. (PRE or PREA)

4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.

MODE REGISTER

Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data
until the next MRS command, which may be issued when all banks are in
idle state. After tRSC from a MRS command, the SDRAM is ready for

CLK
/CS
/RAS
/CAS

new command.

BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 0 0 0 SW 0 0 LTMODE BT BL

LATENCY

MODE

SW

CL /CAS LATENCY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Single Write

1

R
R
2
3
R
R
R
R

Burst Write

0

BURST

LENGTH

BURST

TYPE

/WE

BA0,1 A12-A0

BL BT=0 BT=1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

0
1

1
2
4
8
R
R
R

Full Page

SEQUENTIAL
INTERLEAVED

V

1
2
4
8
R
R
R
R

R: Reserved for Future Use

MITSUBISHI ELECTRIC

13

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

Single Data Rate

MITSUBISHI LSIs

July '01

CLK

Command

Address

DQ

CL= 3
BL= 4

Initial Address BL

A2 A1 A0

0 0 0

256M Synchronous DRAM

Read

Y

Q0 Q1 Q2 Q3 D0 D1 D2 D3

/CAS Latency

Burst Length Burst Length

Burst Type

Column Addressing

Sequential Interleaved

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Write

Y

0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

- 0 0

- 0 1

- 1 0

- 1 1

- - 0

- - 1

1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4

8

4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0

4

2 3 0 1
3 0

0 1

2

1 0

3 4 5 6 3 2 1 0

1 2

7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1

3 2

0 1
1 0

1 0

MITSUBISHI ELECTRIC

14

SDRAM (Rev.1.01)

M2V56S20/ 30/ 40

AKT

-5, -6, -7

OPERATIONAL DESCRIPTION

data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst

Single Data Rate

MITSUBISHI LSIs

July '01

256M Synchronous DRAM

BANK ACTIVATE

One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-12.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.

PRECHARGE

An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of
open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.

Bank Activation and Precharge All (BL=4, CL=3)

CLK

Command

A0-9,11-12

A10

BA0-1

DQ

ACT READACT PRE ACT

tRRD tRCD tRP

Xa Xb Yb Xa

1Xa Xb 0

00 01 01 00

Qb0 Qb1 Qb2 Qb3

Precharge All

Xa

READ

A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0­9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive

Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ,
WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The
internal precharge starts at the BL after READA. The next ACT command can be issued after (BL +
tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met.

MITSUBISHI ELECTRIC

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