Mitsubishi DS907x SIP, DS5000TK User Manual

TABLE OF CONTENTS

SECURE MICROCONTROLLER USER’S GUIDE 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 1 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2 Selection Guide 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3 Secure Microcontroller Architecture 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 4 Programmer’s Guide 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 5 Memory Interconnect 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 6 Lithium/Battery Backup 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 7 Power Management 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 8 Software Control 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 9 Firmware Security 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 10 Reset Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 11 Interrupts 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 12 Parallel I/O 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 13 Programmable Timers 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 14 Serial I/O 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 15 CPU Timing 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 16 Program Loading 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 17 Real–Time Clock 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 18 Troubleshooting 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 19 Instruction Set Details 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECURE MICROCONTROLLER DEVELOPMENT TOOLS

Development Support Third Party Development Tools DS907x SIP Stik Connectors DS5000TK User’s Guide

USER’S GUIDE

SECTION 1: INTRODUCTION

The Secure Microcontroller family is a line of 8051–compatible devices that utilize nonvolatile RAM (NV RAM) rather than ROM for program storage. The use of NV RAM allows the design of a “soft” microcontroller which provides a number of unique features to embedded system designers. Foremost among these is the enhanced security features that are employed by the Secure Microcontroller Family to protect the user application software against piracy and tampering. These devices offer varying degrees of security , ranging from simple access prevention to a full encryption of program and data memory of the device. Attempts to gain access to protected information will result in the self–destruction of all data. The Secure Microcontroller family is the heart of a wide range of security–critical applications such as electronic banking, commercial transactions, and pay TV access control, or any situation which requires the protection of proprietary software and algorithms.

The Secure Microcontroller family is divided between chips and modules. The chips are monolithic microprocessors that connect to a standard SRAM and lithium battery. The modules combine the microprocessor with the SRAM and lithium battery in a preassembled, pretested module. Depending on the specific configuration, modules are available in either 40–pin encapsulated DIP or SIMM module format.

In addition to NV RAM, Dallas Semiconductor microcontrollers offer a number of peripherals that simplify and reduce the cost of embedded systems. Although the specific features of each chip or module vary, all devices offer the following basic feature set:

• 100% code–compatible with 8051

• Directly addresses 64KB program/64KB data

memory

• Nonvolatile memory control circuitry

• 10–year data retention in the absence of power

• In–system reprogramming via serial port

• 128 bytes fast access scratchpad RAM

• Two 16–bit general purpose timer/counters

• One UART

• Five interrupts with two external

• Dedicated memory bus, preserving four 8–bit ports

for general purpose I/O

• Power–Fail Reset

• Early Warning Power Fail Interrupt

• Watchdog Timer

SOFTWARE SECURITY

One of the most important features of the Secure Microcontroller family is firmware/memory security. The devices were specifically designed to offer an unprecedented level of protection to the user application software, preventing unauthorized copying of firmware and denying access to critical data values. The use of RAM rather than the traditional ROM or EPROM for program storage increases the security, since tampering with the system will result in the loss of the RAM contents. Additional features such as real–time high–speed memory encryption, generation of dummy addresses on the bus, and internal storage of vector RAM increases the security of a Secure Microcontroller/Microprocessor–based system.

The DS5002FP Secure Microprocessor Chip and DS2252T Secure Microcontroller Module offer the highest level of security, with permanently enabled memory encryption, a 64–bit random encryption key, and a self– destruct input for tamper protection. The DS5000FP Soft Microprocessor Chip and DS5000(T) and DS2250(T) Soft Microcontroller Modules offer lesser, but still substantial, protection with optional data encryption and a 48–bit encryption key.

SEPARATE ADDRESS/DATA BUS

Soft Microprocessor chips provide a non–multiplexed address/data bus that interfaces to memory without interfering with I/O ports. This Byte–wide bus connects directly to standard CMOS SRAM in 8K x 8, 32K x 8, or 128K x 8 densities with no glue logic. Note that this is in addition to the standard 8051 port 0 and 2 multiplexed bus. In module form, the Byte–wide bus is already connected directly to on–board SRAM, so the memory access becomes transparent and the I/O ports free for application use. The extra memory bus also allows for a time–of–day function to be included, and all Soft Microcontroller modules are available with built in real–time clocks. The same clock devices are individually available when building a system from chips. Battery backup and decoding are automatically handled by the microprocessor.

050396 1/173

USER’S GUIDE

LARGE NONVOLATILE MEMORY

Soft Microprocessor chips provide nonvolatile memory control for standard CMOS SRAM. Modules combine the microprocessor chip with memory and lithium backup. This includes conditionally write protected chip enables and a power supply output that switches between +5V and battery backup. The chip enables are decoded automatically based on user selectable memory sizes and partitioning. Partitioning defines the portion of memory used for program and data segments. Areas that are designated program are always write protected and are treated as ROM. Data areas are write protected only when power is out of tolerance. A large nonvolatile memory is useful for data logging and as flexible program storage. Memory will be retained for over 10 years at room temperature in the absence of power by ultra low–leakage lithium backed circuits.

IN–SYSTEM LOADING

The in–system programming capability lets the user update program code at any time. This program loading is supervised by a built–in ROM–based bootstrap loader. The ROM loader becomes transparent once program loading is complete. All devices allow program loading via the serial port. Data memory can also be retrieved using this loader function. Selected versions provide

other parallel loading protocols as well. In–system loading allows a system to be configured during final system test. A user can load custom software, diagnostic routines, or calibration constants. If something changes or new features arise, the system can then be reprogrammed while in the field.

HIGH RELIABILITY OPERATION

Secure Microcontroller devices are designed for unsupervised operation in remote locations. Special features prevent a system from running out of control during transient events. These include a reset when power is out of tolerance; an early warning power–fail interrupt that allows software to save critical data; and a watchdog to reset the micro if it gets lost. Also, nonvolatile memory allows software to save the operating state so a task can be resumed when power returns to normal.

The Secure Microcontroller family consists of three chips and their associated modules. Differences stem from I/O, memory access, and security features. The DS5000FP is used in DS2250T and DS5000(T) modules. The DS5001FP is used in the DS2251T, and the DS5002FP is used in the DS2252T . A full selector guide with all memory and speed permutations is provided in the next section.

CHIP

DS5000FP Soft Microprocessor Chip 8, 32, 64*K bytes Optional 80–pin QFP DS5001FP 128K Microprocessor Chip 32, 64, 128K bytes None 80–pin QFP DS5002FP Secure Microprocessor Chip 32, 64, 128K bytes Maximum 80–pin QFP

MODULE DESCRIPTION ON–BOARD MEMOR Y PACKAGE

DS2250(T) DS5000FP on SIMM 8, 32, 64*K bytes 40–pin SIMM DS5000(T) DS5000FP in DIP Module 8, 32K bytes 40–pin DIP

DS2251T DS5001FP on SIMM 32, 64, 128K bytes 72–pin SIMM DS2252T DS5002FP on SIMM 32, 64, 128K bytes 40–pin SIMM

*32K partitionable, 32K restricted to data memory only.

DESCRIPTION

BYTE–WIDE BUS

MEMORY ACCESS

SECURITY PACKAGE

NOTES:

“T” specifies optional on–board real–time clock. 128K byte versions provide fixed 64K program, 64K data segments. Other versions are partitionable.

050396 2/173

USER’S GUIDE

PRODUCT DESCRIPTION

All devices listed below have the standard 8051 family feature set listed once here for convenience, but not repeated for each device.

• 8051–compatible instruction set

• Addresses 64K program and 64K data memory

• Four 8–bit pseudo–bidirectional I/O ports

• 128 bytes scratchpad RAM

• Two 16–bit timer/counters

• One UART

• Five Interrupts with two external

DS5000FP Soft Microprocessor Chip

The DS5000FP is the original Soft Microprocessor chip. It adds the following features to the 8051 set :

• Non–multiplexed Byte–wide address/data bus for

memory access.

• Nonvolatile Control for 8K x 8 or 32K x 8 SRAMs

• Partitions one SRAM into program and data areas,

and write protects the program segment

• Decodes memory for up to two 32K x 8 SRAMs (#2

is data memory only)

• Power–fail Reset, and Interrupt

• Precision Watchdog Timer

• ROM based Serial Bootstrap Loader

• Optional security features

– Memory encryption in real–time – 48–bit user selected encryption key – Security lock destroys memory if unlocked – Vector RAM hides 48 bytes on–chip – Dummy operations on the memory bus

DS5000(T) Soft Microcontroller Module

The DS5000 incorporates the DS5000FP chip in a 40–pin module with an 8051 footprint and pinout.

• Familiar 40–pin DIP package

• Built–in NV RAM of 8K x 8 or 32K x 8

• I/O ports not disturbed by on–board memory access

• 10–year data retention and clock operation in the

absence of power

• Partitions memory into program and data areas,

write protects the program segment

• Power–fail Reset and Interrupt

• Precision Watchdog Timer

• ROM based Serial Bootstrap Loader

• Optional memory security

• Optional built–in real time clock (battery backed)

DS2250(T) Soft Microcontroller Module

The DS2250(T) incorporates the DS5000FP chip on a 40–pin SIMM module. It has the identical feature set as the DS5000(T), but is in a different form–factor. This package change allows up to 64K bytes NV RAM instead of 32K bytes. Note that as mentioned above, the second 32K is restricted to data memory. Like the DS5000(T), this module guarantees better than 10–year data retention at room temperature.

DS5001FP 128K Soft Microprocessor Chip

The DS5001FP provides the base feature set of the DS5000FP with the following extras:

• Accesses up to 128K bytes on the Byte–wide bus.

• Decodes memory for 32K x 8 or 128K x 8 SRAMs.

• Four additional decoded peripheral chip enables

• CRC hardware for checking memory validity

• Optionally emulates an 8042 style slave interface

• Bandgap reference for more accurate power moni-

tor

Note: The DS5001FP has no memory encryption feature.

050396 3/173

USER’S GUIDE

DS2251T 128K Soft Microcontroller Module

The DS2251T is a SIMM based on the DS5001. It provides up to 128K bytes of on–board NV RAM and has the Byte–wide bus available at the connector. This is used with the decoded peripheral enables for memory mapped peripherals such as a UART or A/D converter . The real–time clock is a parallel access type with interrupt capability. Like the older versions, the DS2251T provides 10–year data retention, even in the largest memory configuration.

DS5002FP Secure Microprocessor Chip

The DS5002FP is a highly secure version of the DS5001FP. It provides the operating features of the DS5001FP, with the following enhancements to the DS5000 security features.

• Security is active at all times

• Improved memory encryption using a 64–bit en-

cryption key

• Automatic random generation of encryption keys

• Self–destruct input for tamper protection

• Optional top–coating prevents microprobe

(DS5002FPM)

DS2252T Secure Microcontroller Module

The DS2252T incorporates the DS5002FP on a 40–pin SIMM. This includes from 32K bytes to 128K bytes of secure memory with a real time clock. The memory is highly secure from tampering and from competitors. Like other products in the family, the D2252T has a data retention period of over 10 years at room temperature.

050396 4/173

USER’S GUIDE

SECTION 2: SELECTION GUIDE

The following configurations are available. Speeds are

controller family are fully static and can be run as slow as desired.

rated maximums, but all members of the Secure Micro-

CHIP

DESCRIPTION MAXIMUM SPEED PART NUMBER

DS5000FP–16 Soft Microprocessor Chip 16 MHz DS5000FP–16 DS5001FP–16 128K Microprocessor Chip 16 MHz DS5001FP–16 DS5002FP–16 Secure Microprocessor Chip 16 MHz DS5002FP–16

MODULE DESCRIPTION MEMORY SPEED CLOCK PART NUMBER

DS5000 Soft Microcontroller

8K bytes 16 MHz no DS5000–08–16

Module

DS5000 Soft Microcontroller

32K bytes 16 MHz no DS5000–32–16

Module

DS5000T Soft Microcontroller

8K bytes 16 MHz yes DS5000T–08–16

Module

DS5000T Soft Microcontroller

32K bytes 16 MHz yes DS5000T–32–16

Module

DS2250 Soft Microcontroller

8K bytes 16 MHz no DS2250–08–16

Module

DS2250 Soft Microcontroller

32K bytes 16 MHz no DS2250–32–16

Module

DS2250 Soft Microcontroller

64K bytes 16 MHz no DS2250–64–16

Module

DS2250T Soft Microcontroller

8K bytes 16 MHz yes DS2250T–08–16

Module

DS2250T Soft Microcontroller

32K bytes 16 MHz yes DS2250T–32–16

Module

DS2250T Soft Microcontroller

64K bytes 16 MHz yes DS2250T–64–16

Module

DS2251T 128K Microcontroller

32K bytes 16 MHz yes DS2251T–32–16

Module

DS2251T 128K Microcontroller

64K bytes 16 MHz yes DS2251T–64–16

Module

DS2251T 128K Microcontroller

128K bytes 16 MHz yes DS2251T–128–16

Module

DS2252T Secure Microcontrol-

32K bytes 16 MHz yes DS2252T–32–16

ler Module

DS2252T Secure Microcontrol-

64K bytes 16 MHz yes DS2252T–64–16

ler Module

DS2252T Secure Microcontrol-

128K bytes 16 MHz yes DS2252T–128–16

ler Module

050396 5/173

USER’S GUIDE

SECTION 3: SECURE MICROCONTROLLER ARCHITECTURE

Introduction

The Secure Microcontroller family is based on an 8051 compatible core with a memory interface and I/O logic build around it. Many functions are identical to standard 8051s and are documented here for completeness. In general, most architecture features apply to all members of the Secure Microcontroller family. When there is a difference between versions, this will be mentioned. A block diagram of the microcontroller core is shown in Figure 3–1 below.

Bus Organization

There are four major busses in the Secure Microprocessor: the Internal Data Bus, the Internal Address Bus, the Byte–wide Memory Bus, and the Expanded Bus. All addresses and data which are transferred during program execution are passed on the Internal Address and Data Busses. User Program and Data Memory is always accessed from either the byte–wide Program/Data RAM or from external memory located on the Expanded Bus.

The Byte–wide Memory Bus is used for access to Program/Data RAM in the same fashion as an 8051 Family device would access internal ROM or EPROM memory. This bus can be used in place of the Expanded Bus, freeing Port 2 and Port 0 pins for general I/O use.

CPU Registers

All of the CPU registers are mapped as Special Function Registers (SFR’s) and are identical in number and function to those present within the 8051. These registers are described briefly below:

Accumulator The Accumulator (A) is used as either a source or destination register in all arithmetic instructions. It may also be used in most other types of instructions.

Stack Pointer The Stack Pointer (SP) is an 8–bit register which is used to mark the location of the last byte of data stored in the stack. The stack itself may be located anywhere in the on–chip 128–byte Scratchpad register area. The Stack Pointer pre-increments during a stack push and postdecrements during a stack pop.

B Register The major function of the B register is as a source and destination register during multiply and divide instructions. It may also be used as a scratchpad register.

Program Status Word The Program Status Word (PSW) contains status flags that are set according to the results of a previously executed instruction. In addition, the PSW contains register bank select bits.

Data Pointer The Data Pointer (DPTR) is used to access Data Memory that may be mapped into Byte–wide Data RAM or onto external memory devices on the Expanded Bus. It is accessed by the user’s program as either two 8–bit Special Function registers or as a 16–bit register with certain instructions.

Scratchpad Registers

Scratchpad registers are 128 registers where data may be stored directly. They are addressed from 00H to 7FH and may be accessed by a MOV instruction. Included in the scratchpad area are four 8–byte banks of working registers. These registers are not part of the data memory map.

Serial I/O

The on–chip serial I/O port is comprised of a receive data buffer , a transmit data buffer, and a control register . Both the receive data buffer and the transmit data buffer are accessed in a single location (SBUF) in the Special Function Register map. The control register (SCON) is accessed in an separate location. When the serial I/O function is enabled, two external I/O pins (P3.0, P3.1) are re–assigned in hardware to serve the transmit and receive data functions.

Programmable Timers

Two 16–bit programmable timers are included that can perform various timing and counting functions. A total of four registers (TH1, TL1, TH0, and TL0) access the upper and lower halves of each of the two timer/counters. A single control register (TCON) is used to select the various operating modes of the two timers. Two external I/O pins (P3.4, P3.5) may be programmed to serve as external counter inputs, one pin for each of the two timer/counters.

050396 6/173

USER’S GUIDE

SECURE MICROCONTROLLER ARCHITECTURAL BLOCK DIAGRAM Figure 3–1

DATA RAM

EXTERNAL

PROGRAM/

BUS

MEMORY

INCREMENTOR

BYTE–WIDE

STACK

POINTER

PSW

DRIVERSDRIVERS

ADDRESS

ENCRYPTOR

KEY

ENCRYPT

I/O

SBUF

SERIAL

INTERNAL ADDRESS BUS

TIMER

SCON

TL0

TH0

TCON

TLMOD

TL1

TH1

DATA

ENCRYPTOR

ACC

DPTR

CE1

TEMP 1 TEMP 2

BUFFER

CE2

AND

TIMING

CONTROL

PROGRAM

ADDR. REG.

R/W

ALU

INTERNAL DATA BUS

TAMCONSECURITY

LOCK

LOGIC

PCON

CONTROL

INTERRUPT

LOGIC

TIMED

ACCESS

MEMORY

CTL. LOGIC

ALLOCATIONS

CONTROL

NONVOLATILE

VCC VLI

050396 7/173

PORT 3

DRIVERS

PORT 1

DRIVERS

128

SCRATCH–

TIMER

WATCHDOG

TIMING

ALE

PSEN

PAD

REGISTERS

OSCILLATOR

AND

CONTROL

XTAL1 XTAL2

RST

IDR ADDR.

RAM

ROM

LOADER

INTERNAL DATA BUS

LATCH

PORT 3

8 8

LATCH

PORT 1

RESIDENT

LATCH

PORT 2

DRIVERS

PORT 2

INTERNAL ADDRESS BUS

VECTOR

LATCH

PORT 0

DRIVERS

PORT 0

INSTRUCTION

USER’S GUIDE

Parallel I/O

Four SFR’s provide access for the four parallel I/O port latches. These I/O ports are denoted as P0, P1, P2, and P3. A total of 32 bits of parallel I/O is available through these I/O ports. However, up to 16 bits are sacrificed when the Expanded Bus mode is used to interface to external memory and up to six bits may be sacrificed if any external interrupt inputs, timer counter inputs, or serial I/O functions are used. When using the Byte–wide bus, ports are not affected.

Program/Data RAM Interface

Secure Microcontrollers provide a non–multiplexed Byte–wide bus that connects to external SRAM. They also make this RAM nonvolatile, decode memory access for it, and write–protect portions designated as program memory. The Byte–wide bus consists of up to 16 address lines (depending on the version), eight data lines, read/write control, and decoded chip enables. When accessing the SRAM via its Byte–wide bus, there is no activity on the ports. Thus if memory access is restricted to this bus, all ports are free for use by the application. In module form, the microprocessor is already connected to SRAM via the Byte–wide bus making program and data memory access appear internal.

Secure Microprocessors can also access memory using the multiplexed Expanded Bus consisting of Port 0 and 2, WR (P3.6) and RD (P3.7). This is usually undesirable since it consumes port pins that can be used for other activity. If Expanded bus access is desired, up to 64K ROM and 64K RAM can be accessed in the same manner as a traditional 8051. Each version has different provisions for using the Expanded bus, depending on memory map and user’s configuration. These issues are discussed under the Programmer’s Guide.

High–Reliability Circuitry

This feature ensures proper operation of the micro and maintains the contents of the Program/Data RAM in the absence of VCC using a self–contained lithium energy source. The logic provided includes the Power Fail Warning Interrupt, Automatic Power Down and Power On Reset. As a result, the Program/Data RAM may be modified whenever necessary during execution of the user’s software but will remain unchanged when V absent. The circuitry also maintains the Internal

Scratchpad RAM and certain Special Function registers during a power down condition.

Software Encryption Logic

DS5000 and DS5002 series parts provide software security circuits that include the Address Encryptor, Data Encryptor, and the Encryption Key Word. When the device is operating in the Encryption mode and using the Program/Data RAM, the Address Encryptor is used to transform “logical” addresses on the Internal Address Bus into encrypted addresses which appear on the Byte–wide Memory Bus to the RAM. Similarly , the Data Encryptor transforms data on the Internal Data bus into encrypted data during write operations on the Byte– wide Memory bus. When data is read back, the Data Encryptor restores it to its true value. Although each encryptor uses its own algorithm for encrypting data, both depend on the Encryption Key Word stored on–chip.

Security Lock Logic

The Security Lock logic prevents a read or write to any Program/Data RAM location using the bootstrap loader. In addition, it inhibits the device from fetching code in the Expanded Bus Mode. By disabling access to key internal resources, this feature precludes unauthorized disassembly of application software contained in Program/ Data RAM. In contrast with an EPROM security bit, clearing the Security Lock wipes the entire RAM area.

Vector RAM

The Vector RAM is used to contain the reset and interrupt vector code when the Soft Microcontroller is operating in the Encryption mode. This feature is included to insure the security of the application software. The operation of the Vector RAM as well as the reason for its inclusion in the architecture are discussed in the Software Security section.

Timed Access Logic

The Timed Access logic is used to protect against inadvertent changes to configuration and to the Program RAM in the event of a loss of software control. The protected configuration parameters include the Partition Address bits in the MCON register, as well as the Enable Watchdog Timer bit, Stop Mode bit, and Power On Re-

set bit in the PCON register.

050396 8/173

USER’S GUIDE

Watchdog Timer

When the user’s software is being executed, the Watchdog Timer can be used to automatically restart the processor in the event that software control is lost. It is also used to generate an oscillator start–up delay to allow the clock frequency to stabilize. This occurs during reset cycles that follow a time in which the oscillator has been stopped (Stop Mode Reset and Power On Reset).

Resident Loader ROM

The Resident Loader ROM contains firmware that controls the initial loading of the nonvolatile Program/Data

RAM. The firmware provides Serial Bootstrap Load operation via the on–chip serial port. The internal ROM is not accessible by the user and performs the loading function only when the device is strapped for operation in the Program mode. The ROM becomes transparent to the user once loading is complete and has no effect on the memory map.

050396 9/173

USER’S GUIDE

SECTION 4: PROGRAMMER’S GUIDE

The Secure Microcontroller uses nonvolatile RAM technology for both Program and Data memory . It uses NV SRAM in place of ROM by write protecting and decoding memory segments that a user designates as

cess a second RAM, but this was restricted to data memory only. The DS5001 series can partition two 32K byte SRAMs, or even one 128K x 8 SRAM. Common elements of the programming model are given be-

low, with individual differences highlighted. Program memory . The remaining RAM area is used as nonvolatile data storage. One of the advantages of breaking a common RAM into two segments is that a smaller number of memory chips is needed. For example, if a system requires 24K bytes of program memory and 4K bytes of data memory, this all fits within one 32K x 8 SRAM. The Secure Microcontroller can break this RAM into program and data segments, unconditionally write protecting the program area. The process of dividing the common memory space into ROM and RAM is called partitioning. All Secure Microcontrollers are capable of doing this. However, there are differences between original DS5000 series [includes DS5000FP, DS5000(T), and DS2250T] and newer DS5001 series [includes DS5001FP, DS2251T, DS5002FP, DS2252T]. The original DS5000 series could partition one SRAM of up to 32K bytes. It could ac-

Secure Microcontroller Memory

Organization

All Secure Microcontrollers follow the standard 8051

convention of three memory areas. These include Inter-

nal registers, Program memory and Data memory.

These memory areas are not contiguous and are ac-

cessed in different ways. The Secure Microcontroller

duplicates all standard 8051 registers and adds several

new ones. Secure Microcontrollers have a 64K byte

program and 64K byte data space. However, the

Secure Microcontrollers provide several ways to access

these areas, and these features are what make the fam-

ily unique. Figure 4–1 shows the memory map of

Secure Microcontrollers in general terms. The specific

details and access to the memory areas are discussed

below.

SECURE MICROCONTROLLER MEMORY MAP Figure 4–1

–FFFFh–

64K

FFh

7Fh

SCRATCH PAD

REGISTERS

INTERNAL REGISTERS

SPECIAL

FUNCTION

REGISTERS

Internal Registers

The internal register space is divided into two parts. These are Scratchpad Registers and Special Function Registers (SFRs). There are a total of 128 Scratchpad registers, commonly referred to as on–chip RAM. The 128 bytes include four 8–byte banks of working registers (R0–R7). The Scratchpad Registers are located at register addresses 00–7Fh. This area is not located in the Program or Data Memory area and is accessed by

0000

PROGRAM

MEMORY

DATA

MEMORY

different instructions. The Special Function Registers

(SFR) are located in the locations between 80h and

FFh. SFRs control the on–chip peripherals and memory

configurations. Direct addressing should be used to ac-

cess the SFR locations. If Register–Indirect addressing

is used, indeterminate data will be returned. Scratchpad

Registers are discussed immediately below, with SFR

descriptions following later in this section.

050396 10/173

USER’S GUIDE

The Scratchpad Registers are general purpose data storage RAM. They are commonly used for temporary storage of a small number of variables when high– speed access is needed. Off–chip RAM (MOVX) is used when the quantity of data is larger than 128 bytes. The Scratchpad Registers are lithium backed and will be preserved in the absence of power.

The Scratchpad area has two additional functions. First, 16 bytes of the Scratchpad area are bit addressable. That is, while each byte has an address of its own, these bits also have individual bit addresses. Certain instructions operate on bits instead of bytes. Although the addresses appear the same, the microprocessor can distinguish a bit address from a byte address by the instruction used. A large number of individual software flags and conditions can be represented using 128 (16*8) individually addressable bits.

SCRATCHPAD REGISTER MAP Figure 4–2

7FH

7F 7E 7D 7C 7B 7A 79 78

2FH

77 76 75 74 73 72 71 70

2EH

6F 6E 6D 6C 6B 6A 69 68

2DH

67 66 65 64 63 62 61 60

2CH

5F 5E 5D 5C 5B 5A 59 58

2BH

57 56 55 54 53 52 51 50

2AH

4F 4E 4D 4C 4B 4A 49 48

29H

47 46 45 44 43 42 41 40

28H

3F 3E 3D 3C 3B 3A 39 38

27H

37 36 35 34 33 32 31 30

26H

2F 2E 2D 2C 2B 2A 28 28

25H

27 26 25 24 23 22 21 20

24H

1F 1E 1D 1C 1B 1A 19 18

23H

17 16 15 14 13 12 11 10

22H

0F 0E 0D 0C 0B 0A 09 08

21H

07 06 05 04 03 02 01 00

20H 1FH

18H 17H

10H 0FH

08H 07H

00H

MSB LSB

A second use of the Scratchpad area is for the programmer’s stack. Like the 8051, the Secure Microcontroller uses a Stack Pointer (SP – 81h) SFR to direct stack access into the internal registers. The SP has a default value of 07h. This means that stack storage will begin at location 08h. Each PUSH or CALL instruction will increment the SP . Note that while the SP is located in the SFR area, the stack itself is stored in the Scratchpad area. The Scratchpad Register Memory map is shown in Figure 4–2.

Programmer’s note

: with the use of ‘C’ compilers becoming more frequent, the large memory model should be examined. This compiler model places the stack in off–chip SRAM. Secure Microcontroller based systems usually have an abundance of such SRAM compared to ROM based systems. While off–chip stack results in slower execution time, the stack size becomes virtually unlimited.

BANK 3

BANK 2

BANK 1

BANK 0

050396 11/173

USER’S GUIDE

The 8051 instruction set allows efficient (single cycle) access to variables when using the Working Registers. These are a group of four 8–byte banks of Scratchpad RAM. The active Working Registers are referred to as R0–R7. They reside between location 00h and 1Fh, depending on which bank is currently selected. Two bits in

and R0 (PSW.3) are used to determine which is the active bank. Once selected, all instructions involving R0–R7 will be directed to the selected group of 8 bytes. This scheme also allows for a fast context switch by simply changing banks. The following Table shows the operation of the Register Bank selection.

the Special Function Register PSW called R1 (PSW.4)

PSW.4–3 ; R1–R0

R1 R0 BANK STARTING ADDRESS (R0)

0 0 00h 0 1 08h 1 0 10h 1 1 18h

Program and Data Memory

The Secure Microcontroller divides its main memory between Program and Data segments. Each map consists of a 64K byte area from 0000h to FFFFh. Program memory is inherently read only, since there are no 8051

must be ROM/EPROM and data memory must be volatile SRAM. If NV RAM is needed on the Expanded bus, then it must be externally backed up and write protected. The Secure Microcontroller makes no special

provisions for NV RAM on the Expanded bus. instructions that write to this segment. Data memory is read and write accessible without restrictions. The CPU automatically routes program fetches to the program area and MOVX instructions to the data memory area. All of these elements are in common with the standard

8051. Secure Microcontroller differences lie in the memory interface, memory map control, and flexibility of the memory resources.

When discussing memory addressing of Secure Micro-

controllers, there are two important terms that are used

frequently: Partition and Range. The Partition is the

user–selectable address that divides the program seg-

ment from the data segment in a common RAM area on

the Byte–wide bus. The Partition is a user–adjustable

boundary that can be selected during Bootstrap Load-

ing or on the fly by the application software. The Range Secure Microcontrollers provide two separate buses for memory access. First is a Byte–wide address/data bus

is the total amount of memory connected to the Byte–

wide bus. This is set once during initial programming. which is new to the 8051 architecture. This bus also provides a switched supply output that make standard SRAM into nonvolatile memory , decoded chip enables, and a R/W strobe. Furthermore, the Byte–wide bus allows nonvolatile RAM memory to be divided between Program and Data segments. When using a segment of the RAM as Program Memory, this area can be loaded using the Bootstrap Loader function described later in this book.

The DS5000 series devices can access between 8K

and 64K bytes of NV RAM on the Byte–wide bus. Up to

the first 32K bytes are Partitionable into Program and

Data segments as described above. The DS5001 se-

ries can access between 8K and 128K bytes on its

Byte–wide bus with better Partition control. The

Memory map control resides in the MCON (address

C6h) Special Function Register on DS5000 devices. On

DS5001 devices, both the MCON (address C6h) and Second is an Expanded bus constituted by Ports 0 and

2. This is the standard 8051 compatible memory bus which is available as an option, but is not needed in most cases. Program memory on the Expanded bus

RPCTL (address D8h) registers are used. Since the

memory maps and control have significant differences

between these versions, they are described below in

separate sections.

050396 12/173

USER’S GUIDE

DS5000 Series Memory Organization

As mentioned above, the DS5000 series consists of the DS5000FP chip and the DS5000(T) and DS2250T modules. The programming model discussed in this section applies to all of these parts. The DS5000 series Byte– wide bus has 15 address lines, eight data lines, a R/W strobe, and two chip enables to access nonvolatile RAM. In the case of a module, these are already connected and may be thought of as internal or embedded memory. The DS5000 series can use either 8K x 8 or 32K x 8 SRAMs. The user must inform the microcontroller of the selected RAM size using the Range function. The Range bit resides in the MCON SFR at MCON.3 and has a value of 0 when 8K SRAM is used and 1 when a 32K byte SRAM is used. Range is selected during Bootstrap Loading and can not be varied by the application software. The DS5000 device accesses memory on its Byte–wide bus using two chip enables. The first,

, is Partitionable. That is, the RAM connected to

CE1 CE1, whether 8K or 32K, can be divided between program and data segments. The Partition is user–selected and can be set during Bootstrap Loading and by software. Partitions are generally available on 2K byte boundaries in the DS5000 except for the last which is 4K. The Partition is selected using the MCON SFR described below. CE2 The RAM on CE2 Access to CE2 switch. Bit 2 (ECE2) of the MCON SFR controls access to CE2 and is described below.

Figure 4–3 illustrates the functional memory map of a DS5000 series device. The Partition, Range, ECE2, and the logical address combine to determine whether the DS5000 uses its Byte–wide bus or the Expanded

is restricted to data memory only.

should be of the same size as CE1.

is manual, and functions like a bank

Bus. Nonvolatile RAM access will occur when the logical address lies in one of the shaded regions. These are program addresses below the Partition address, data addresses above the Partition and below the Range address, or data addresses between 0 and the Range when ECE2 is set to a logic 1. Note that when using ECE2 to force data access, the CE2

RAM will be selected instead of the CE1 RAM. This means that on a DS5000 module or a DS2250 with less than 64K RAM, no data memory exists under CE2. The ECE2 has no affect on program memory, which continues from the

RAM or the Expanded bus normally.

CE1

Note that the Partition and Range settings are not automatically linked. This means a user should take care not to select a Partition that is larger than the Range. Naturally when the Range is 32K, the Partition address can be as high as 32K. When a Range of 8K is used, Partition addresses below 8K should be used. Any address that does not map onto the Byte–wide bus will be automatically be routed to the Expanded Bus of Ports 0 and

2. For module users. this means that any address not routed to internal memory will go to the ports. The following examples will help illustrate the decoding.

When the Partition is at 3000h, and the Range at 32K, program memory below 3000h is accessed on the Byte–wide bus. Program memory at or above 3000h is directed to the Expanded bus or Ports 0 and 2. When the Partition is at 5800h and the Range at 32K, data memory at 0000h is accessed on Ports 0 and 2. Data memory at 6000h is located in NV RAM on the Byte– wide bus. When the Partition is at 1000h and the Range at 8K, all memory access above 1FFFh is on the Expanded bus. Below 8K, the Partition rules apply .

IMPORTANT APPLICATION NOTE

The MCON register is a special function register unique to Dallas Semiconductor microcontrollers which contains nonvolatile memory configuration information. This register should be set to the desired value before loading the device via the bootstrap loader. Failure to correctly configure the MCON register can cause the device to operate incorrectly, including symptoms which appear similar to a defective device. Because this register is nonvolatile, incorrect memory settings will be preserved when power is removed. The DS5001FP, DS5002FP, DS2251T, and DS2252T store additional memory configuration information in the RPCTL register, which should also be set to the desired value before loading the device via the bootstrap loader.

050396 13/173

DS5000 SERIES MEMORY MAP Figure 4–3

FFFFh

USER’S GUIDE

ECE2=1ECE2=0

64K

7FFFh

1FFFh

BYTE–WIDE

BUS ACCESS

PARTITION

ADDR.

BYTE–WIDE

BUS ACCESS

0000

LEGEND:

= NO MEMORY ACCESS

= EXPANDED BUS ACCESS ON PORTS 0 AND 2

PROGRAM DATA DATA

MEMORY MEMORY MEMORY

DEVICE #1 SELECTED

WITH CE1

BYTE–WIDE ACCESS WITH CE2 (NONVOLATILE RAM)

BYTE–WIDE ACCESS WITH CE1 (NONVOLATILE RAM)

The above memory map covers the standard operating case. There are two conditions that can modify this memory map. The first is the EA pin. The second is the Security Lock. When the EA

pin is grounded, the DS5000 will force all memory access to the Expanded bus. This causes the DS5000 to behave like an 8031 regardless of the Partition, Range, or ECE2. The EA should be pulled to +5V for normal operation. The second modifier is the Security Lock. When set, the Security Lock prevents using the Bootstrap Loader to read the contents of the NV RAM. For security purposes, it also prohibits program memory access on the Expanded Bus. Thus all program fetches must be restricted to the Byte–wide bus when locked. The Security Lock overrides the condition of the EA

pin as well.

32K

RANGE

ADDR.

BYTE–WIDE

BUS ACCESS

DEVICE #2 SELECTED

WITH CE2

The selection of memory map controls provide unprecedented flexibility to configure a system. However, it is possible to select contradictory settings. The micro will compensate for these as follows. The Partitioning function allows a user to select the quantity of program and data memory . It is possible to select all data and no program in NV RAM by choosing a Partition of 0000h. This is a valid selection. However, using this setting and the Security Lock is a conflict. This condition asks the micro to use all program memory on the Expanded bus, but also to prohibit the use of program memory on the Expanded bus. In this event, special circuits will automatically force the Partition to a location of 7FFFh. This means all 32K memory on the Byte–wide bus is designated program memory. The second contradictory

050396 14/173

USER’S GUIDE

case is to select a Range of 8K, and to choose a Partition of greater than 8K. This will result in the Range as the limiting factor. Addresses above the Range will automatically be deflected to the Expanded bus. No data memory will be allocated in NV RAM for this configura-

tion, the Partition can be selected or modified by the application software and CE2

is normally software controlled. However, in either case, the MCON SFR is used to choose these settings. The MCON is summarized in the SFR section below, but appears here also.

tion.

DS5000 Memory Map Control

The Partition and Range can be selected using the Bootstrap Loader discussed in a later section. In addi-

DS5000 SERIES MCON REGISTER Figure 4–4 Bit Description:

MCON.7–4: PA3–0

“Partition Address”: Use to select the starting address of Data Memory in Embedded RAM. Pro-

gram space lies below the Partition address.

Selection: PA3 P A2 PA1 PA0 Partition Address

0 0 0 0 0000H 0 0 0 1 0800H 0 0 1 0 1000H 0 0 1 1 1800H 0 1 0 0 2000H 0 1 0 1 2800H 0 1 1 0 3000H 0 1 1 1 3800H 1 0 0 0 4000H 1 0 0 1 4800H 1 0 1 0 5000H 1 0 1 1 5800H 1 1 0 0 6000H 1 1 0 1 6800H 1 1 1 0 7000H* 1 1 1 1 8000H*

*A 4K byte increment (not 2K bytes) in the Partition Address takes place between bit field values 1110B and 1111B.

Initialization: Set to all 1’s on a No V

Power On Reset or when the Security Lock bit is

cleared to a 0 from a previous 1 state. These bits are also set to all 1’s when any attempt is made to have them cleared to all 0’s with the SL bit set to a 1

(illegal condition). Read Access: May be read anytime. Write Access: PAA bit must = 1 in order to write PA3–0. Timed Access is not required to

write to PA3–0 once PAA = 1.

050396 15/173

USER’S GUIDE

MCON.3: RA32/8

“Range Address”: Sets the maximum usable address on the Byte–wide bus.

RA32/8 = 0 sets Range Address = 1FFFH (8K); RA32/8 = 1 sets Range Address = 7FFFH (32K)

Initialization: Set to a 1 on a No V

Power On Reset and when the Security Lock bit (SL) is

cleared to a 0 from a previous 1 state. Remains unchanged on all other types

of resets. Read Access: May be read normally anytime. Write Access: Cannot be modified by the application software; can only be written during

Program Load mode.

MCON.2: ECE2

“Enable Chip Enable 2”: Used to enable or disable the CE2

signal to additional RAM Data Memory space. This bit should always be cleared to 0 in the DS5000–8, DS5000–32, DS2250–8, and DS2250–32 versions.

Initialization: Cleared to 0 only during a No V

Power On Reset.

Read Access: Read normally anytime. Write Access: Can be written normally anytime.

MCON.1: PAA

“Partition Address Access”: Used to protect the programming of the Partition Address select bits. PA3–0

cannot be written when PAA=0. PAA can be written only via the Timed Access register.

Initialization: PAA is cleared on a reset. Read Access: PAA may be read anytime. Write Access: The Timed Access register must be used to perform any type of write opera-

tion on the PAA bit.

DS5001/DS5002 Memory Organization

As mentioned above, the DS5001/DS5002 series consists of the DS5001FP chip, the DS2251T module, the DS5002FP chip, and the DS2252T module. Note that the DS5002FP is a high security version of the DS5001FP, but has the same memory map and I/O. The programming model discussed in this section applies to all of these parts and any reference to the DS5001 applies to all of them. The DS5001 series Byte–wide bus has 16 address lines, eight data lines, a R/W of eight chip enables to access nonvolatile RAM and peripherals. Chip enables include CE1 – CE4 and PE1 – PE4. The four chip enables (CE1–4) are for nonvolatile RAM access. How they are connected depends on the memory mode and the selection of SRAMs. The PE signals are generally for memory mapped peripherals, but can be used for more RAM if desired. PE1 and PE2 are

strobe, and a total

lithium–backed, PE3

and PE4 are not. In the case of a module, PE1 may be connected to a real–time clock. Memory map control resides in the MCON (C6h) and RPCTL (D8h) registers. The MCON register has selected differences from its DS5000 counterpart. These are documented below . The RPCTL is not present in the DS5000. Also, not all of the bits in this register pertain to memory map control. This section describes the relevant bits and the SFR section below documents the entire register.

The DS5001 series can use multiple 8K x 8 or 32K x 8 SRAMs or a single 128K x 8 SRAM. These parts can operate in either a Partitionable (like DS5000) or non– partitionable mode. The mode is selected via the PM (MCON.1) bit of the MCON register. Note, the DS5001 MCON provides different functions than the DS5000. In

050396 16/173

USER’S GUIDE

a Partitionable mode (PM=0), the DS5001 can use up to 64K x 8 SRAM for program and data on its Byte–wide bus. It can partition this area into program and data segments on 4K boundaries. The 64K memory space would consist of two 32K x 8 SRAMs. Each is accessed by a separate chip enable (CE1

and CE2), but the microcontroller automatically decodes which is needed. While the DS5001 can use between one 8K x 8 SRAM and 4 32K x 8 SRAMs, it does not automatically know

RG1 RG0 RANGE CE1

ACCESS CE2 ACCESS

which configuration is used. The Range function deter mines how much total memory is connected to the Byte–wide bus. The user must identify the total RAM size using the Range bits RG1 and RG0. RG1 is located at MCON.3 and RG0 is located at RPCTL.0. These Range bits are selected during the Bootstrap Loading process and can not be modified by the application software. The Table below shows the Range values that can be selected when PM=0 (Partitionable).

1 1 64K 0000–7FFFh 8000–FFFFh 1 0 32K 0000–7FFFh NA 0 1 16K 0000–1FFFh 2000h–3FFFh 0 0 8K 0000–1FFFh NA

The total RAM space is partitionable, regardless of which Range is selected. This contrasts with the DS5000 that allowed partitioning of CE1

only. The Partition table is shown below. P A3–0 are the four MSBs of the MCON register (MCON.7–4). Note that the Parti-

a Range of less than 64K is selected, then the partition settings above the Range should not be unused. The microcontroller automatically decodes which RAM to enable, and uses the Partition to decide if this is program memory or data memory.

tion values do not scale depending on Range. That is, if

PA3 PA2 PA1 PA0 P ARTITION BYTE–WIDE BUS MEMORY MAP

0 0 0 0 0000h 0K PROGRAM, DATA = RANGE 0 0 0 1 1000h 4K PROGRAM, DATA = RANGE – 4K 0 0 1 0 2000h 8K PROGRAM, DATA = RANGE – 8K 0 0 1 1 3000h 12K PROGRAM, DATA = RANGE – 12K 0 1 0 0 4000h 16K PROGRAM, DATA = RANGE – 16K 0 1 0 1 5000h 20K PROGRAM, DATA = RANGE – 20K 0 1 1 0 6000h 24K PROGRAM, DATA = RANGE – 24K 0 1 1 1 7000h 28K PROGRAM, DATA = RANGE – 28K 1 0 0 0 8000h 32K PROGRAM, DATA = RANGE – 32K 1 0 0 1 9000h 36K PROGRAM, 28K DATA 1 0 1 0 A000h 40K PROGRAM, 24K DATA 1 0 1 1 B000h 44K PROGRAM, 20K DATA 1 1 0 0 C000h 48K PROGRAM, 16K DATA 1 1 0 1 D000h 52K PROGRAM, 12K DATA 1 1 1 0 E000h 56K PROGRAM, 8K DATA 1 1 1 1 FFFFh 64K PROGRAM, 0K DATA

Figure 4–5 illustrates the functional memory map of a DS5001 series device in Partitionable mode. Note that like the DS5000, any access that does not correspond

050396 17/173

to a Byte–wide bus location is routed to the Expanded bus Ports 0 and 2.

PARTITIONABLE MEMORY MAP FOR DS5001/DS5002 SERIES Figure 4–5

FFFFh

PARTITION

ADDR.

0000

LEGEND:

BYTE–WIDE

BUS ACCESS

PROGRAM DATA

MEMORY MEMORY

BYTE–WIDE ACCESS

(NONVOLATILE RAM)

PES=0

BYTE–WIDE

BUS ACCESS

64K

RANGE

ADDRESS

USER’S GUIDE

= EXPANDED BUS ACCESS ON PORTS 0 AND 2

The non–partitionable mode allows the maximum amount of memory to be used on the Byte–wide bus. A non–partitionable mode would be used because the 8051 architecture is restricted to a total of 64K program and 64K data (without bank switching). This means that if the maximum amount of either program or data (or both) is needed, partitioning can not be done. The DS5001/DS5002 series accommodates these situations with four selections of non–partitionable (PM=1)

the Range bits when PM=1. Also note the MSEL signal. This is a pin on DS5001/DS5002 series devices that tells the processor whether multiple 32K RAMs or a 128K RAM is being used. When MSEL=0, a single 128K device is used. It is not possible to partition the device when MSEL=0, and the state of the partition bits will be ignored. The four selections are as follows. The non– partitionable memory map is shown in Figure 4–6. Byte–wide bus segments begin at 0000h.

memory control shown below. These are selected using

MSEL RG1 RG0 PROGRAM DATA PROGRAM ACCESS DATA ACCESS

1 0 0 32K 64K 1 @ 32K, CE1 2 @ 32K, CE3 and CE4 1 0 1 64K 32K 2 @ 32K, CE1 and CE2 1 @ 32K, CE3 1 1 0 64K 64K 2 @ 32K, CE1 and CE2 2 @ 32K, CE3 and CE4 0 1 1 64K 64K 1 @ 128K X 8, for both program and data

050396 18/173

USER’S GUIDE

Any address that does not fall into the Byte–wide bus area is routed to the Expanded bus of Ports 0 and 2. This could only occur for the first two settings. Note that a single 128K device is the least expensive in terms of component cost and size. In this case, all memory addressable by the DS5001 is stored in a nonvolatile

128K x 8 SRAM. When the MSEL pin is grounded, the device automatically converts CE1 CE2 to A16, CE3 to A15, and CE4 is unused. The MSL bit, accessible only via the bootstrap loader, is used to select whether the the 64KB data or 64KB program segment is addressed by the loader.

NON–PARTITIONABLE MEMORY MAP FOR DS5001, DS5002 SERIES Figure 4–6

PES=0

BYTE–WIDE

BUS ACCESS

64K

RANGE

32K7FFFh

PROGRAM

RANGE

FFFFh

0000

BYTE–WIDE

BUS ACCESS

PROGRAM DATA

MEMORY MEMORY

to a chip enable,

DATA

LEGEND:

BYTE–WIDE ACCESS

(NONVOLATILE RAM)

= EXPANDED BUS ACCESS ON PORTS 0 AND 2

DS5001/DS5002 Memory Mapped Peripherals

The DS5001 series provides four decoded chip enables that can be used for peripheral access or extra RAM on the Byte–wide bus. Application software enables the four PE signals, which are decoded on 16K byte boundaries. While they are enabled, they completely use the data memory map and normal data memory is not available on either the Byte–wide or Expanded bus. The PES bit (MCON.2) is set to a logic 1 to access the peripheral space. When PES=1, the appropriate PE activated based on the logical address. Figure 4–7

050396 19/173

signal will be

shows the data memory map while PES=1. PES has an identical effect for either Partitionable or Non–partitionable modes. It has no effect on the program area. Note that the first two Peripheral Enables, PE1

and PE2 are

lithium backed by the DS5001. This means that when

is removed, the device will maintain these chip en-

ables in a logic high, inactive state. PE3 and PE4 are not lithium backed making them suitable for UARTs, A/Ds, etc. Lithium backed chip enables are used to access lithium backed memory or peripherals, including the DS1283 real–time clock used in the DS2251T and DS2252T.

USER’S GUIDE

On occasion, a memory mapped peripheral is needed that interfaces directly to an 8051 multiplexed bus. When this occurs, MOVX instructions can be forced to use the Expanded bus in any mode with the EXBS bit (RPCTL.5). Setting this bit to a logic one forces all

MOVX instructions to the Expanded bus. While EXBS=1, the entire 64K data memory map is accessed in this way. Clearing EXBS will cause the microcontroller to revert to its selected configuration. In most systems, the EXBS bit will not be used.

PERIPHERAL ENABLES IN THE DATA MEMORY MAP Figure 4–7

64K

PES=1

PE4

PE3

PE2

PE1

DATA

MEMORY

FFFFh

BFFFh

7FFFh

3FFFh

DS5001/DS5002 Memory Map Control

Like the DS5000, the DS5001/DS5002 uses Special Function Registers to control the memory map. The memory control functions include the Partition, Range, Partition Mode (PM), Expanded Bus Select (EXBS), Peripheral Enable Select (PES) and Access Enable (AE – discussed below). The Partition and Range can be selected using the Bootstrap Loader discussed in a later section. In addition, the Partition can be selected or modified by the application software by writing to the

MCON register. PES is normally used by software and is also controlled by the MCON register. The MCON is documented in the SFR summary, but also appears here for convenience. The Range is controlled by a combination of MCON and RPCTL bits. In addition, the EXBS and AE are controlled using the RTPCL register . As not all of the RPCTL bits pertain to memory control, the relevant bits are described below. RPCTL is fully documented in the SFR summary.

050396 20/173

USER’S GUIDE

DS5001/DS5002 SERIES MCON REGISTER Figure 4–8

PA3 PA2 PA1 PA0 RG1 PES PM –––

Bit Description:

MCON.7–4: PA3–0

Initialization: Unaffected by watchdog, external, or power–up resets. Set to 1111B on a

Read Access: Can be read normally at any time. Write Access: Timed Access Protected. Also, cannot be written by the application soft-

Partition Address. When PM=0, this address specifies the boundary between program and data memory in a continuous space.

reset.

No V

ware if set to 0000B by the serial loader. If a 0000B is written via the serial loader and the security lock is set, the Partition will become 1111B. The same will occur if write access is available and application software writes a 0000B. In addition, these bits will be set to 1 1 1 1B if security lock is cleared.

MCON.3: RG1

One of two bits that determine the range of program space. RG0 is located in the RPCTL register.

Initialization: Unaffected by watchdog, external, or power–up resets. Set to 1 on a No V

reset or a clearing of the security lock. Read Access: Can be read at any time. Write Access: Cannot be modified by the application software. Can only be written during

program load.

MCON.2: PES

Peripheral Enable Select. When this bit is set, the data space is controlled

by PE1 – PE4. Peripherals are memory–mapped in 16K blocks, and are

accessed by MOVX instructions. Initialization: Cleared by all resets.

Read Access: Can be read at any time. Write Access: Can be written at any time.

MCON.1: PM

Partition Mode. When PM=0, a partitionable, continuous memory map is

invoked. When PM=1, one of four fixed allocations is used. Initialization: Unaffected by watchdog, external, or power–up reset. Cleared on a No V

reset. Read Access: Can be read at any time. Write Access: Cannot be written by the application software. Can only be modified during

program load.

050396 21/173

DS5001/DS5002 SERIES RPCTL REGISTER BITS AFFECTING MEMORY Figure 4–9

RNR ––– EXBS AE IBI DMA RPCON RG0

Bit Description:

RPCTL.5: EXBS

The Expanded Bus Select routes data memory access (MOVX) to the Expanded bus formed by ports 0 and 2 when set.

Initialization: Cleared after all resets. Read Access: Can be read at any time. Write Access: Can be written at any time.

USER’S GUIDE

RPCTL.4: AE

Access Enable is used when a software reload is desired without using Program Load mode. When set, the DS5001 will be temporarily configured in a Partitionable configuration with the partition at 4K. This will occur even if the PM=1. When cleared, the prior memory configuration is resumed.

Initialization: Cleared after all resets. Read Access: Can be read at any time. Write Access: Can be written at any time, timed access protected.

RPCTL.0: RG0

This is a Range bit which is used to determine the size of the program memory space. Its usage is shown above.

Initialization: Unaffected by watchdog, external, or power–up resets. Cleared on a No V

reset or clearing of the security lock. Read Access: Can be read at any time. Write Access: Cannot be modified by the application software. Can only be written during

Program Load.

Loading and Reloading Program Memory

Soft Microcontrollers are programmed through a built– in Bootstrap Loader function. This loader is also used to configure the desired options for memory map control.

device, the Bootstrap Loader must be invoked. However, the Secure Microcontroller is designed to allow a partial reload of memory without invoking the Bootstrap

Loader. The Secure Microcontroller uses its low power lithium backed circuits to maintain critical settings in the absence of power. For this reason, it is not necessary to set the Partition, Range, etc. after every power–up or reset. Once set, they will remain unless deliberately modified. Bootstrap Loading is discussed in a later section. One of the major advantages of a Secure Microcontroller is the ability to change these settings, and even reload the entire program memory while the device is installed in system. To completely re–program and re–configure a

The major advantage of this technique is that it requires

no hardware or external switches. Most of the memory

can be reprogrammed under application software con-

trol. It would commonly be used when the target system

connects to a PC through a serial port as part of an ap-

plication. For example, a data logger that must dump

memory periodically. While connected to the PC, it is

extremely easy to reload portions of memory using the

“Soft Reload”.

050396 22/173

USER’S GUIDE

Application software always has unrestricted read/write access to the nonvolatile RAM designated as data memory. This is the memory that lies above the Partition address and below the Range address (the non–partitionable configuration of the DS5001 will be addressed separately). Data memory is read or written using the MOVX instruction. Only the area designated as program memory can not be altered. The key to doing a “Soft Reload” is to temporarily change the program memory RAM into data memory. Using an SFR, the application software can authorize the Secure Microcontroller to temporarily redefine a portion of the program memory area as data memory. Once this is done, the new code can be received through a serial port (or other means) and written into data memory. When the process is complete and the new memory is verified as correct, software converts the RAM back into write–protected program memory for the duration. As with the memory map control, there are minor differences between the DS5000 series and DS5001/DS5002 series devices in how this is accomplished. Each is described below.

SOFT RELOAD OF A DS5000 SERIES DEVICE When application software decides that it should repro-

gram a portion of memory, the software must convert the target area into data memory. The DS5000 will do this when software sets the PAA bit (MCON.1) to a logic

1. PAA is the Partition Access Enable. Setting PAA has two effects. The microcontroller will automatically move the Partition to 0800h and allow write access to the Partition control bits PA3–0 (MCON.7–4). At this time, the software can adjust the Partition, but the new value will not be used until after PAA is cleared. The Partition remains at 0800h as long as P AA=1, regardless of the Partition control bits. This leaves a 2K block of NV RAM (from 0000–0800h) assigned as program memory. Apart from this, no other changes take place and software continues to operate normally. Caution, make certain that the code that controls the PAA resides in this first 2K. When PAA=1, all addresses on the Byte–wide bus greater than 0800h will be viewed as data memory and can not be executed even if they were program memory originally. This gives the software read/write access to the remaining 6K bytes (Range=8K) or 30K bytes (Range=32K) of NV RAM on the Byte–wide bus.

At this time, software can begin reloading the target area of memory. There are two minor variations of this procedure. First, a user’s loader routine that resides below 0800h (2K) can reprogram the remainder of memory as needed. This is done be receiving the new

code through a serial port or other mechanism and writing it to the RAM at the addresses where it will be executed. Since the RAM is data memory , the write operation is done using MOVX instructions.

The second option is that the user’s code below 2K can simply move the Partition to a new value. This is done by writing a new value for PA3–0 in MCON (MCON.7–4) while PAA is still set to a 1, then clearing PAA. The purpose of this would be that the loader routine mentioned in option 1 resides in memory above 2K, but below the target memory area. T o gain access, the Partition must be moved to a location that includes this loader routine. Once the Partition is moved to this temporary location, the software loader can reprogram new code as before.

When loading is complete, the Partition must be either restored or set to a new value that is appropriate for the new software. If the PA3–0 bits were not modified, then the PAA bit can simply be cleared. This will cause the old Partition to be restored. If the PAA3–0 were modified during loading or software has grown significantly , then a new Partition is needed. The PA3–0 bits must be written while PAA is set to a 1.

The DS5000FP protects the PAA bit from accidental modification by requiring a Timed Access procedure. Timed Access is designed to prevent an out–of–control program from modifying the PAA bit and crashing the application. Timed Access is discussed in a later section. To summarize the “Soft Reload”, the procedure goes as follows:

1. Ensure that current program execution is in the range of 0000h to 0800h.

2. Set the Partition Address Access (PAA) bit using a Timed Access Procedure.

3. Load new contents into program memory at addresses above 0800h using MOVX instructions.

4. Define a new Partition address if necessary and write the appropriate bits into PA3–0 in the MCON SFR.

5. Restore the current Partition by clearing the PAA bit with a Timed Access procedure.

6. Resume operation.

The following illustrates the Soft Reload procedure. The original program requires a partition of 4000h (16K bytes). The new program is larger, requiring a Partition of 6000h (24K bytes). The code that performs these steps is shown below. This routine must be located below 0800h in program memory .

050396 23/173

MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #10001010b ; SET PAA BIT . ; USER’S CODE TO LOAD . ; RAM USING MOVX . . MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #11001000b ; LOAD NEW PARTITION AND CLEAR PAA BIT

RELOADING PORTIONS OF A DS5000 SERIES DEVICE Figure 4–10

7FFFh

DATA

MEMORY

SPACE

PROGRAM

MEMORY

SPACE

6000h

4000h

DATA

MEMORY

SPACE

DATA

MEMORY

SPACE

USER’S GUIDE

RANGE (32K)

NEW PARTITION (24K)

OLD PARTITION (16K)

0800h

0000h

LEGEND:

PROGRAM

MEMORY

SPACE

BEFORE LOADING PAA=0 PA3–0=1000b

NONVOLATILE RAM PROGRAM MEMORY

NONVOLATILE RAM DATA MEMORY

PROGRAM

MEMORY

SPACE

DURING LOADING PAA=1 PA3–0=XXXXb

AFTER LOADING PAA=0 PA3–0=1100b

TEMP PARTITION (2K)

050396 24/173

USER’S GUIDE

SOFT RELOAD OF A DS5001/DS5002 When application software decides that it should repro-

gram a portion of memory, the software must convert the target area into data memory. However, a Soft Reload of a DS5001 series device has minor variations from the DS5000 version. First, there is no PAA bit in the DS5001. If the DS5001 is in a Partitionable mode then the user’s program must manipulate the Partition control bits PA3–0, placing the Partition to a value that permits the target area to be loaded. Moving the Partition to a new value should convert the target area to data memory allowing read/write access. The user’s loader routine then uses MOVX instructions to load the new program contents into memory . This program can be received from a serial port or other mechanism. When the loading procedure is complete, a new Partition (or the old one) must be loaded. Note that the loader routine must reside below the Partition at all times.

In the DS5000 series, the PAA bit was protected by a Timed Access procedure. In the DS5001, the PA3–0 bits are protected directly. The user’s program must use a Timed Access procedure to alter these bits. The microcontroller further protects the application by not permitting software to write a 0000b into P A3–0. This would cause a program memory area of 0K. Timed Access is discussed in a later section.

If the device is in a non–partitionable configuration, then an extra step is required. T o perform a Soft Reload of the program contents in a non–partitionable mode, the software must convert the micro to a Partitionable mode temporarily . The Access Enable bit (RPCTL.4) will accomplish this. Setting the AE bit to a logic 1 converts the DS5001 into a Partitionable mode for as long as it is set. This means that regardless of the original setting, once AE=1, the memory map is a 64K partitionable mode. The Partition is set to 1000h (4K) when AE=1, so the loader routine must reside in this area. The user can then perform the Soft Reload as discussed above. When loading is complete, the software should clear the

AE bit. Note that AE requires software to use a Timed Access procedure to alter it. This method allows a user to alter program memory in a non–partitionable mode. Data memory can be initialized by application software at any time. Since full read/write access is available, no special provisions are needed.

T o summarize the “Soft Reload” for a DS5001/DS5002, the procedure goes as follows:

Partitionable mode

1. Write a value to PA3–0 using a Timed Access that gives access to the target area of memory.

2. Load new contents into program memory at addresses above the Partition using MOVX instructions.

3. Define a new Partition address if necessary and write the appropriate bits into PA3–0 in the MCON SFR using a Timed Access.

4. Resume operation.

Non–Partitionable mode

1. Set the AE bit to a 1 using a Timed Access procedure.

2. Load new contents into program memory at addresses above the Partition (4K) using MOVX instructions.

3. Clear the AE bit using a Timed Access procedure.

4. Resume operation.

The following illustrates an example where a Soft Reload is performed for a Partitionable mode. The original program requires a partition of 4000h (16K bytes). The new program is larger, requiring a Partition of A000h (40K bytes). A loader routine resides below address 1000h. The code that performs these steps is shown below. Note that the Timed Access procedure is performed, but is described in a later section.

050396 25/173

MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #00011000b ; SET PARTITION TO 1000h | ; USER’S CODE TO LOAD | ; RAM USING MOVX | | MOV TA, #0AAh ; TIMED ACCESS MOV TA, #55h ; TIMED ACCESS 2 MOV MCON, #10101000b ; LOAD NEW PARTITION OF A000h

RELOADING A DS5001/DS5002 SERIES DEVICE Figure 4–11

FFFFh

DATA

MEMORY

SPACE

A000h

DATA

MEMORY

SPACE

DATA

MEMORY

SPACE

USER’S GUIDE

RANGE (64K)

NEW PARTITION (40K)

4000h

1000h

0000h

LEGEND:

PROGRAM

MEMORY

SPACE

BEFORE LOADING PA3–0=0100b

NONVOLATILE RAM PROGRAM MEMORY

NONVOLATILE RAM DATA MEMORY

PROGRAM

MEMORY

SPACE

DURING LOADING PA3–0=0001b

PROGRAM

MEMORY

SPACE

AFTER LOADING PA3–0=1010b

OLD PARTITION (16K)

TEMP PARTITION (4K)

050396 26/173

USER’S GUIDE

Special Function Registers

The Secure Microcontroller uses Special Function Registers (SFRs) to control most functions. In many cases, an SFR will contain 8 bits, each of which control a function or report status on a function. The SFRs reside in register locations 80–FFh. They can be accessed using MOV instructions with direct addressing. In addition, some of the SFRs are bit addressable. This can be particularly useful when enabling a function without modifying others in the register since an SFR can contain 8 unrelated control and status functions.

With a few minor exceptions documented below, the Secure Microcontroller provides identical SFRs to a standard 8051, plus extra locations to control unique functions. Modifications to the standard 8051 SFR map are as follows. The PCON register GF1 (PCON.3) and GF0 (PCON.2) have been replaced by the Enable Power Fail Interrupt and the Enable Watchdog Timer bits re-

spectively. In addition, the Secure Microcontroller requires a Timed Access procedure before allowing software to modify the STOP mode bit (PCON.1). This is to prevent errant software from creating a situation that the Watchdog T imer can not recover from. The remaining SFRs are either identical to the 8051 or new to the architecture.

As with the memory map, there are some differences between the DS5000 series and the DS5001 series SFRs. Figures 4–12 and 4–13 show an overview of their respective SFR maps. Following these figures are detailed descriptions. In the case where a particular SFR has differences between the DS5000 and DS5001/DS5002, those differences will be pointed out under the particular register. In some cases, the DS5001 and DS5002 have registers that do not appear in the DS5000. This is also highlighted under the particular register.

050396 27/173

DS5000 SERIES SPECIAL FUNCTION REGISTER MAP Figure 4–12

DIRECT BYTE

ADDRESS

0F0H

(MSB)

F7 F6 F5 F4 F3 F2 F1 F0

BIT ADDRESS

USER’S GUIDE

SPECIAL FUNCTION REGISTER SYMBOL

(LSB)

0E0H

0D0H

0C7H

0C6H

0B8H

0B0H

0A8H

0A0H

99H

98H

90H

8DH 8CH

8BH 8AH

E7 E6 E5 E4 E3 E2 E1 E0

C AC F0 RS1 RS0 OV P

D7 D6 D5 D4 D3 D2 D1 D0

NOT BIT ADDRESSABLE

PA3 PA2 PA1 PA0 RA32/8 ECE2

NOT BIT ADDRESSABLE

RWT PS PT1 PX1 PT0 PX0

BF – – BC BB BA B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

EA ES ET1 EX1 ET0 EX0 AF – – AC AB AA A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

NOT BIT ADDRESSABLE

SM0 SM1 SM2 REN TB8 RB8 TI RI

9F 9E 9D 9C 9B 9A 99 98

97 96 95 94 93 92 91 90

NOT BIT ADDRESSABLE NOT BIT ADDRESSABLE NOT BIT ADDRESSABLE NOT BIT ADDRESSABLE

PAA

ACC

PSW

MCON

SBUF

SCON

TH1 TH0

TL1 TL0

GATE C/T M1 M0 GATE C/T M1 M0

89H

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

88H

87H

83H 82H

81H 80H

* BITS IN ITALICS ARE NONVOLATILE

8F 8E 8D 8C 8B 8A 89 88

SMOD POR

87 86 85 84 83 82 81 80

NOT BIT ADDRESSABLE

PFW

WTR

NOT BIT ADDRESSABLE

NOT BIT ADDRESSABLE NOT BIT ADDRESSABLE NOT BIT ADDRESSABLE

EPFW

EWT

TMOD

TCON

STOP IDL

PCON

DPH DPL SP

050396 28/173

USER’S GUIDE

DS5001/DS5002 SERIES SPECIAL FUNCTION REGISTER MAP Figure 4–13

DIRECT BYTE

ADDRESS

(MSB) (LSB)BIT ADDRESS

0F0H

F7 F6 F5 F4 F3 F2 F1 F0

SPECIAL FUNCTION REGISTER SYMBOL

0E0H

0DAH

0D8H RPCTL

0D0H PSW

0B8H IP

0B0H P3

0A8H IE

0A0H P2

98H SCON

E7 E6 E5 E4 E3 E2 E1 E0

ST7 ST6 ST5 ST4 IA0 F0 IBF 0BF

RNR ––– EXBS AE IBI DMA RPC

DF DE DD DC DB DA D9 D8

C AC F0 RS1 RS0 OV P

D7 D6 D5 D4 D3 D2 D1 D0

PA3 PA2 PA1 PA0 RG1

RNGE3 RNGE2 RNGE1 RNGE0 ––– –––

RWT PS PT1 PX1 PT0 PX0

BF ––– ––– BC BB BA B9 B8

B7 B6 B5 B4 B3 B2 B1 B0 EA ES ET1 EX1 ET0 EX0 AF ––– ––– AC AB AA A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

SM0 SM1 SM2 REN TB8 RB8 TI RI

9F 9E 9D 9C 9B 9A 99 98

NOT BIT ADDRESSABLE

NOT BIT ADDRESSABLE0CFH RNR NOT BIT ADDRESSABLE0C7H TA

NOT BIT ADDRESSABLE0C6H MCON

PES

NOT BIT ADDRESSABLE0C3H CRC HIGH NOT BIT ADDRESSABLE0C2H CRC LOW

PM SL

MDM CRC

NOT BIT ADDRESSABLE0C1H CRC

NOT BIT ADDRESSABLE99H SBUF

RG0

ACC

RPS

90H P1

89H TMOD

88H TCON

81H SP

80H P0/DBB

* BITS IN ITALICS ARE NONVOLATILE

050396 29/173

97 96 95 94 93 92 91 90

GATE M1 M0 GATE M1 M0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

8F 8E 8D 8C 8B 8A 89 88

SMOD PFW EPFW

D7 D6 D5 D4 D3 D2 D1 D0 87 86 85 84 83 82 81 80

POR

NOT BIT ADDRESSABLE8DH TH1 NOT BIT ADDRESSABLE8CH TH0 NOT BIT ADDRESSABLE8BH TL1 NOT BIT ADDRESSABLE8AH TL0

C/TC/TC/T

NOT BIT ADDRESSABLE

WTR

NOT BIT ADDRESSABLE87H PCON

NOT BIT ADDRESSABLE83H DPH NOT BIT ADDRESSABLE82H DPL NOT BIT ADDRESSABLE

EWT

STOP IDL

+ 144 hidden pages

Mitsubishi DS907x SIP, DS5000TK User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual