MITSUBISHI 38B4 Technical data

查询M38B40E1H-XXXXFP供应商查询M38B40E1H-XXXXFP供应商

DESCRIPTION

The 38B4 group is the 8-bit microcomputer based on the 740 family core technology. The 38B4 group has six 8-bit timers, a 16-bit timer, a fluorescent display automatic display circuit, 12-channel 10-bit A-D converter, a serial I/O with automatic transfer function, which are available for controlling musical instruments and household appliances.

FEATURES

Basic machine-language instructions....................................... 71

•

Minimum instruction execution time ................................. 0.48 µs

•

(at 4.2 MHz oscillation frequency) Memory size

•

ROM .............................................48K to 60K bytes

RAM ..........................................1024 to 2048 bytes

Programmable input/output ports ............................................. 51

•

High-breakdown-voltage output ports ...................................... 36

•

Software pull-up resistors

•

P9)

Interrupts .................................................. 21 sources, 16 vectors

•

Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1

•

Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1

•

......................(max. 256-byte automatic transfer function)

Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1

•

PWM ............................................................................ 14-bit ✕ 1

•

A-D converter .............................................. 10-bit ✕ 12 channels

•

Fluorescent display function......................... Total 40 control pins

•

Interrupt interval determination function ..................................... 1

•

Watchdog timer ............................................................ 20-bit ✕ 1

•

(Ports P5, P61 to P65, P7, P84 to P87,

8-bit ✕ 1 (also functions as timer 6)

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Buzzer output ............................................................................. 1

•

Clock generating circuit ...................................... Built-in 2 circuits

•

(connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage

•

In high-speed mode ...................................................4.0 to 5.5 V

(at 4.2 MHz oscillation frequency)

2.7 to 5.5 V

(at 2.0 MHz oscillation frequency)

In middle-speed mode................................................ 2.7 to 5.5 V

(at 4.2 MHz oscillation frequency)

In low-speed mode .....................................................2.7 to 5.5 V

(at 32 kHz oscillation frequency)

Power dissipation

•

In high-speed mode ..........................................................35 mW

(at 4.2 MHz oscillation frequency)

In low-speed mode .............................................................60 µW

(at 32 kHz oscillation frequency, at 3 V power source voltage)

In stop mode .........................................................................1 µA

(at clock stop)

Operating temperature range ................................... –20 to 85 °C

•

APPLICATION

Musical instruments, VCR, household appliances, etc.

PIN CONFIGURATION (TOP VIEW)

O U T 1

R E F

/ A N

6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2

I N 1

7 3

S S

7 4 7 5

1 1

7 6

1 0

7 7

9

7 8

8

7 9

7

8 0

6

N o t e : I n t h e m a s k o p t i o n t y p e P , I N T3 a n d C N T R1 c a n n o t b e u s e d .

P 57/ S

R D Y 2 /SC L K 2 2

6

/ S

C L K 2 1

P 5

5

/ T x D

P 5 P 54/ R x D

P 53/ S

C L K 1 2

P 52/ S

C L K 1 1

P 51/ S

P 50/ S

A V V

P 65/ S

S T B 1

P 62/ S

B U S Y 1

R D Y 1

/ A N / A N

P 63/ A N P 77/ A N

P 76/ A N

P 64/ I N T4/ S

Fig. 1 Pin configuration of M38B4xMxH-XXXXFP

0

D /

2

1

2

3

4

5

6

7

8

D

U

B

/

0

1

2

3

4

2

Z 0

F L

2

F L

P

F L

P

4

96

06

16

26

36

9

D

/

5

6

7

0

1

2

0

F L

P

45

55

65

75

85

M 3 8 B 4 x M x H - X X X X F P

123456789

1

5

4

3

2

N

/

1

5

4

3

2

7

P

A

1

01

11

2

0

1

2

T

N

R

/

0

7

4

R

E S E

/

P

0

P

I N

6

R

O U

P

C N T

)

/

1

6

(

N o t e

C N T

P

C N T

Package type : 80P6N-A

80-pin plastic-molded QFP

0 1

D /

2

0

F L

P

35

21

T C

X

/

1

I

9 P

1 1

D /

3

0

F L

P

25

31

N C

X

/

0

9 P

2 1

D /

4

0

F L

P

15

41

S S

V

3 1

D /

5

0 P

N

I

X

U

4 1

D /

6

0

F L

P

05

51

T O

X

F L

95

61

C C

V

O U

5 1

D /

7

0

F L

P

84

71

6 1

D /

0

1

F L

P

74

81

T 3

T

/

6

4 P

U

T

7 1

D /

1

F L

P

64

92

T O

1 /

5

4 P

P W

8 1

D /

2

1

F L

P

54

02

1

M /

4

Z 0

P

9 1

D /

3

1

F L

P

44

12

1 U

B

/

3

4

I N

P

N o t e

0 2

D /

4

1 P

3

T /

2

4 P

)

(

F L

34

22

I N

1 2

D /

5

1

F L

P

24

32

1

T /

1

4 P

I N

2

3

2

D

/

6

7

1

F L

P

4

14

4 0

P 30/ F L D

3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5

4

0

9 3

T

D

/

0

/

4

0

P

M /

7

8 P

F L

P W

2 4

P 31/ F L D

2 5

P 32/ F L D

2 6

P 33/ F L D

2 7

P 34/ F L D

2 8

P 35/ F L D

2 9

P 36/ F L D

3 0

P 37/ F L D

3 1

P 80/ F L D

3 2

P 81/ F L D

3 3

P 82/ F L D

3 4

P 83/ F L D

3 5

V

E E

P 84/ F L D

3 6

P 85/ R T P0/ F L D P 86/ R T P1/ F L D

3 7 3 8

FUNCTIONAL BLOCK

P

o r t P 0 ( 8 )8P o r t P 1 ( 8 )8P o r t P 2 ( 8 )8P o r t P 3 ( 8 )8P o r t P 4 ( 8 )7P o r t P 5 ( 8 )8P o r t P 6 ( 6 )6P o r t P 7 ( 8 )8P o r t P 8 ( 8 )8P o r t P 9 ( 2 )2S y s t e m c l o c k g e n e r a t i o

n

XI

N-

XO

U

T

(

m a i n - c l o c k

)

X

C

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XC

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(

s u b - c l o c k

)

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i m e r

s T

i m e r X ( 1 6 - b i t

)

T

i m e r 1 ( 8 - b i t

)

T

i m e r 2 ( 8 - b i t

)

T

i m e r 3 ( 8 - b i t

)

T

i m e r 4 ( 8 - b i t

)

T

i m e r 5 ( 8 - b i t

)

T

i m e r 6 ( 8 - b i t

)

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a t c h d o g t i m e rR

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u i l d - i n p e r i p h e r a l f u n c t i o n sM

e m o r yI

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s

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8

-

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)

S

e r i a l I /

O

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e r i a l I / O 1 ( C l o c k - s y n c h r o n i z e d

)

(

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t

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)

Fig. 2 Functional block diagram

2

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PIN DESCRIPTION

Table 1 Pin description (1)

Pin Name Function

VCC, VSS Power source • Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS. VEE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.

power source

VREF Reference • Reference voltage input pin for A-D converter.

voltage

AVSS Analog power • Analog power source input pin for A-D converter.

source • Connect to VSS. RESET Reset input • Reset input pin for active “L”. XIN Clock input • Input and output pins for the main clock generating circuit.

• Feedback resistor is built in between XIN pin and XOUT pin.

XOUT Clock output

P00/FLD8– I/O port P0 • 8-bit I/O port. • FLD automatic display P07/FLD15 • I/O direction register allows each pin to be individually programmed as either pins

P10/FLD16– Output port P1 • 8-bit output port. • FLD automatic display P17/FLD23 • A pull-down resistor is built in between port P1 and the VEE pin. pins

P20/BUZ02/ I/O port P2 • 8-bit I/O port with the same function as port P0. • FLD automatic display FLD0– • Low-voltage input level. pins P27/FLD7 • High-breakdown-voltage P-channel open-drain output structure. • Buzzer output pin (P20) P30/FLD24– Output port P3 • 8-bit output port. • FLD automatic display P37/FLD31 • A pull-down resistor is built in between port P3 and the VEE pin. pins

P40/INT0, I/O port P4 • 7-bit I/O port with the same function as port P0. • Interrupt input pins P41/INT1, • CMOS compatible input level In the mask option type P, P42/INT3 • N-channel open-drain output structure. INT3 cannot be used. P43/BUZ01 • Buzzer output pin P44/PWM1 • PWM output pin

P45/T1OUT, • Timer output pin P46/T3OUT P47/INT2 Input port P4 • 1-bit input port. • Interrupt input pin

• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.

• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

• The clock is used as the oscillating source of system clock.

input or output.

• At reset, this port is set to input mode.

• A pull-down resistor is built in between port P0 and the VEE pin.

• CMOS compatible input level.

• High-breakdown-voltage P-channel open-drain output structure.

• At reset, this port is set to VEE level.

• High-breakdown-voltage P-channel open-drain output structure.

• At reset, this port is set to VEE level.

• High-breakdown-voltage P-channel open-drain output structure.

• At reset, this port is set to VEE level.

• CMOS compatible input level.

Function except a port function

(Timer output pin)

3

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 2 Pin description (2)

Pin Name Function P50/SIN1, I/O port P5 • 8-bit CMOS I/O port with the same function as port P0. • Serial I/O1 function pins P51/SOUT1, • CMOS compatible input level.

P52/SCLK11, • CMOS 3-state output structure. P53/SCLK12

P54/RXD, • Serial I/O2 function pins

P55/TXD, P56/SCLK21, P57/SRDY2/ SCLK22 P60/CNTR1 I/O port P6 • 1-bit I/O port with the same function as port P0. • Timer input pin

• CMOS compatible input level. In the mask option type P,

• N-channel open-drain output structure. CNTR1 cannot be used. P61/CNTR0/ • 5-bit CMOS I/O port with the same function as port P0. • Timer I/O pin CNTR2 • CMOS compatible input level. P62/SRDY1/ • CMOS 3-state output structure. • Serial I/O1 function pin

AN8 • A-D conversion input pin P63/AN9 • A-D conversion input pin

P64/INT4/ • Serial I/O1 function pin SBUSY1/AN10, P65/SSTB1/ • Interrupt input pin (P64) AN11

P70/AN0– I/O port P7 • 8-bit CMOS I/O port with the same function as port P0. • P77/AN7 • CMOS compatible input level.

• CMOS 3-state output structure.

P80/FLD32– I/O port P8 • 4-bit I/O port with the same function as port P0. P83/FLD35

P84/FLD36 • 4-bit CMOS I/O port with the same function as port P0.

P85/RTP0/ • Low-voltage input level. FLD37, • CMOS 3-state output structure • Real time port output P86/RTP1/

FLD38 P87/PWM0/

FLD39 • 14-bit PWM output

P90/XCIN, I/O port P9 • 2-bit CMOS I/O port with the same function as port P0. • P91/XCOUT • CMOS compatible input level.

• Low-voltage input level.

• High-breakdown-voltage P-channel open-drain output structure.

• CMOS 3-state output structure.

Function except a port function

•

Dimmer signal output pin

• A-D conversion input pin

A-D conversion input pin

•

FLD automatic display pins

•

FLD automatic display pins

•

FLD automatic display pins

I/O pins for sub-clock generating

circuit (connect a ceramic resona-

tor or a quarts-crystal oscillator)

4

PART NUMBERING

g

y

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P r o d u c t

M 3 8 B 4 9 M F H - X X X X F P

P a c k a g e t y p e

F P : 8 0 P 6 N - A p a c k a

R O M n u m b e r

H i g h - b r e a k d o w n v o l t a g e p u l l - d o w n o p t i o n

R e g a r d i n g o p t i o n c o n t e n t s , r e f e r t o s e c t i o n “ M A S K O P T I O N O F P U L L - D O W N R E S I S T O R ” .

R O M s i z e

t e : 4 0 9 6 b y t e s

1

: 8 1 9 2 b y t e s

2

: 1 2 2 8 8 b y t e s

3

: 1 6 3 8 4 b y t e s

4

: 2 0 4 8 0 b y t e s

5

: 2 4 5 7 6 b y t e s

6

: 2 8 6 7 2 b y t e s

7

: 3 2 7 6 8 b y t e s

8

: 3 6 8 6 4 b y t e s

9

: 4 0 9 6 0 b y t e s

A

: 4 5 0 5 6 b y t e s

B

: 4 9 1 5 2 b y t e s

C

: 5 3 2 4 8 b y t e s

D

: 5 7 3 4 4 b y t e s

E

: 6 1 4 4 0 b

F

s

e

Fig. 3 Part numbering

T h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f R O M a r e r e s e r v e d a r e a s ; t h e y c a n n o t b e u s e d f o r u s e r s .

M e m o r y t y p e

: M a s k R O M v e r s i o n

M

: E P R O M o r O n e T i m e P R O M v e r s i o n

E

R A M s i z e

0

: 1 9 2 b y t e s : 2 5 6 b y t e s

1

: 3 8 4 b y t e s

2

: 5 1 2 b y t e s

3

: 6 4 0 b y t e s

4

: 7 6 8 b y t e s

5

: 8 9 6 b y t e s

6

: 1 0 2 4 b y t e s

7

: 1 5 3 6 b y t e s

8

: 2 0 4 8 b y t e s

9

5

GROUP EXPANSION

Mitsubishi plans to expand the 38B4 group as follows:

Memory Type

Support for Mask ROM version.

Memory Size

Mask ROM size..................................................... 48K to 60K bytes

RAM size............................................................1024 to 2048 bytes

Package

80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

R O M s i z e ( b y t e s )

6 0 K 5 6 K 5 2 K 4 8 K 4 4 K 4 0 K 3 6 K 3 2 K 2 8 K 2 4 K 2 0 K 1 6 K 1 2 K

8 K 4 K

2 5 65

Note : Products under development or planning : the development schedule and specifications may be revised without notice.

1

27

U n d e r d e v e l o p m e n t

M 3 8 B 4 7 MC

6

81

, 0 2

R A M s i z e ( b y t e s )

41

, 5 3

62

U n d e r d e v e l o p m e n t

M 3 8 B 4 9 M F H

, 0 4

8

Fig. 4 Memory expansion plan

Currently supported products are listed below.

Table 3 List of supported products

Product

M38B49MFH-XXXXFP

M38B47MCH-XXXXFP

6

ROM size (bytes)

ROM size for User ( )

61440

(61310)

49152

(49022)

RAM size (bytes)

2048

1024

Package

80P6N-A

As of Mar. 2000

Remarks

Mask ROM version

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)

The 38B4 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows:

The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instr uctions can be used.

[Accumulator (A)]

The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accum ulator.

[Index Register X (X)]

The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address.

[Index Register Y (Y)]

The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address.

[Stack Pointer (S)]

The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls (see Table 4).

[Program Counter (PC)]

The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.

b7

b0

A Accumulator

b7

b0

X Index register X

b7

b0

Y Index register Y

b7 b0

S Stack pointer

b7b15 b0

PC

H

L

Program counterPC

b7 b0

N V T B D I Z C Processor status register (PS)

Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

Fig. 5 740 Family CPU register structure

7

e

O n - g o i n g R o u t i n

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P u s h r e t u r n a d d r e s s o n s t a c k

P O P re t u r n a d d r e s s f r o m s t a c k

I n t e r r u p t r e q u e s t

M ( S )( P CH)

( S )

M ( S )( P CL)

( S )

S u b r o u t i n e

E x e c u t e R T S

( S )

( P CL)M ( S )

( S )

( P CH)M ( S )

( N o t e )

( S ) – 1

( S ) + 1

E x e c u t e J S R

M ( S )( P CH)

( S )

( S ) – 1

M ( S )( P CL)

( S )

( S ) – 1

M ( S )( P S )

( S )

( S ) – 1

I n t e r r u p t

S e r v i c e R o u t i n e

E x e c u t e R T I

( S )

( S ) + 1

( P S )M ( S )

( S )

( S ) + 1

( P CL)M ( S )

( S )

( S ) + 1

P u s h r e t u r n a d d r e s s o n s t a c k

P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k

I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r

P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k

P O P r e t u r n a d d r e s s f r o m s t a c k

( P CH)M ( S )

N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ”

Fig. 6 Register push and pop at interrupt generation and subroutine call

Table 4 Push and pop instructions of accumulator or processor status register

Push instruction to stack

Accumulator Processor status register

PHA PHP

I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

Pop instruction from stack

PLA PLP

8

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Processor Status Register (PS)]

The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

•Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.

•Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.

•Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.

•Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.

•Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.

•Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations.

•Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.

•Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.

Table 5 Set and clear instructions of each bit of processor status register

C flag Z flag I flag D flag B flag T flag V flag N flag

Set instruction Clear instruction

SEC CLC

_ _

SEI CLI

SED

CLD

_ _

SET CLT CLV

_

_ _

9

[CPU Mode Register (CPUM)] 003B16

The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B16.

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b 7

b 0

C P U m o d e r e g i s t e r

(

C P U M : a d d r e s s

P r o c e s s o r m o d e b i t s b 1 b 0 0 0 : S i n g l e - c h i p m o d e 0 1 : 1 0 : N o t a v a i l a b l e 1 1 :

S t a c k p a g e s e l e c t i o n b i t 0 : P a g e 0 1 : P a g e 1

N o t a v a i l a b l e

P o r t X

C

0 : I / O p o r t f u n c t i o n 1 : X

C I N

M a i n c l o c k ( X

0 : O s c i l l a t i n g 1 : S t o p p e d

M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t

0 : f ( X 1 : f ( X

I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t

0 : X 1 : X

Fig. 7 Structure of CPU mode register

0 0 3 B

1 6

)

s w i t c h b i t

– X

C O U T

o s c i l l a t i n g f u n c t i o n

I N

– X

O U T

) s t o p b i t

I N

) ( h i g h - s p e e d m o d e )

I N

) / 4 ( m i d d l e - s p e e d m o d e )

I N

- X

O U T

s e l e c t i o n ( m i d d l e - / h i g h - s p e e d m o d e )

C I N

- X

C O U T

s e l e c t i o n ( l o w - s p e e d m o d e )

10

MITSUBISHI MICROCOMPUTERS

6

a

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY Special Function Register (SFR) Area

The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for stack area of subroutine calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for device testing, and the other areas are user areas for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

R A M a r e a

R A M s i z e

( b y t e )

1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8

8 9 6 1 0 2 4 1 5 3 6 2 0 4 8

R O M a r e a

R O M s i z e

( b y t e )

4 0 9 6 8 1 9 2

1 2 2 8 8 1 6 3 8 4 2 0 4 8 0 2 4 5 7 6 2 8 6 7 2 3 2 7 6 8 3 6 8 6 4 4 0 9 6 0 4 5 0 5 6 4 9 1 5 2 5 3 2 4 8 5 7 3 4 4 6 1 4 4 0

A d d r e s s X X X X

0 0 F F 0 1 3 F 0 1 B F 0 2 3 F 0 2 B F 0 3 3 F 0 3 B F 0 4 3 F 0 6 3 F 0 8 3 F

A d d r e s s

Y Y Y Y

F 0 0 0 E 0 0 0 D 0 0 0 C 0 0 0 B 0 0 0 A 0 0 0 9 0 0 0

1 6

8 0 0 0

1 6

7 0 0 0

1 6

6 0 0 0

1 6

5 0 0 0

1 6

4 0 0 0

1 6

3 0 0 0

1 6

2 0 0 0

1 6

1 0 0 0

1 6

1 6 1 6

1 6

1 6 1 6 1 6 1 6

A d d r e s s

1 6

1 6 1 6

1 6

1 6 1 6 1 6

Z Z Z Z

F 0 8 0 E 0 8 0 D 0 8 0 C 0 8 0 B 0 8 0 A 0 8 0 9 0 8 0 8 0 8 0 7 0 8 0 6 0 8 0 5 0 8 0 4 0 8 0 3 0 8 0 2 0 8 0 1 0 8 0

1 6

1 6 1 6

1 6

1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6

Zero Page

The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special Page

The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

0 0 0 0

R A M

R O M

0 0 4 0

0 1 0 0

X X X X

0 4 4 0

0 E F 0 0 E F F

0 F 0 0

0 F F F

Y Y Y Y

Z Z Z Z

F F 0 0

F F D C

F F F E

F F F F

1 6

1

1 1 1 6

1 1 6

1 6

1 6 1 6

S F R a r e a 1

R e s e r v e d a r e a

N o t u s e d ( N o t e )

S F R a r e a 2

R A M a r e a f o r S e r i a l I / O a u t o m a t i c t r a n s f e r R A M a r e a f o r F L D a u t o m a t i c d i s p l a y

R e s e r v e d R O M a r e a

( c o m m o n R O M a r e a , 1 2 8 b y t e )

I n t e r r u p t v e c t o r a r e a

R e s e r v e d R O M a r e

Z e r o p a g e

S p e c i a l p a g e

Fig. 8 Memory map diagram

N o t e: W h e n 1 0 2 4 b y t e s o r m o r e a r e u s e d a s R A M a r e a , t h i s a r e a c a n b e u s e d .

11

MITSUBISHI MICROCOMPUTERS

S

C O

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0 8 0 0 0 9 0 0 0 A 0 0 0 B 0 0 0 C 0 0 0 D 0 0 0 E 0 0 0 F 0 0 1 0 0 0 1 1 0 0 1 2 0 0 1 3 0 0 1 4 0 0 1 5 0 0 1 6 0 0 1 7 0 0 1 8 0 0 1 9 0 0 1 A 0 0 1 B 0 0 1 C 0 0 1 D 0 0 1 E 0 0 1 F

1 6

P o r t P 0 ( P 0 ) P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D )

1 6

P o r t P 1 ( P 1 )

1 6 1 6

P o r t P 2 ( P 2 )

1 6

P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D )

1 6

P o r t P 3 ( P 3 )

1 6 1 6

P o r t P 4 ( P 4 )

1 6

P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D )

1 6

P o r t P 5 ( P 5 )

1 6

P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D )

1 6

P o r t P 6 ( P 6 )

1 6

P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D )

1 6

P o r t P 7 ( P 7 )

1 6

P o r t P 7 d i r e c t i o n r e g i s t e r ( P 7 D )

1 6

P o r t P 8 ( P 8 )

1 6

P o r t P 8 d i r e c t i o n r e g i s t e r ( P 8 D )

1 6

P o r t P 9 ( P 9 )

1 6

P o r t P 9 d i r e c t i o n r e g i s t e r ( P 9 D )

1 6

P W M r e g i s t e r ( h i g h - o r d e r ) ( P W M H )

1 6

P W M r e g i s t e r ( l o w - o r d e r ) ( P W M L )

1 6

B a u d r a t e g e n e r a t o r ( B R G )

1 6

U A R T c o n t r o l r e g i s t e r ( U A R T C O N )

1 6 1 6

S e r i a l I / O 1 a u t o m a t i c t r a n s f e r d a t a p o i n t e r ( S I O 1 D P )

S e r i a l I / O 1 c o n t r o l r e g i s t e r 1 ( S I O 1 C O N 1 )

1 6

S e r i a l I / O 1 c o n t r o l r e g i s t e r 2 ( S I O 1 C O N 2 )

1 6

S e r i a l I / O 1 r e g i s t e r / T r a n s f e r c o u n t e r ( S I O 1 ) S e r i a l I / O 1 c o n t r o l r e g i s t e r 3 ( S I O 1 C O N 3 )

1 6

S e r i a l I / O 2 c o n t r o l r e g i s t e r ( S I O 2 C O N )

1 6

S e r i a l I / O 2 s t a t u s r e g i s t e r ( S I O 2 S T S )

e r i a l I / O 2 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r ( T B / R B

1 6

0 0 2 0 0 0 2 1 0 0 2 2 0 0 2 3 0 0 2 4 0 0 2 5 0 0 2 6 0 0 2 7 0 0 2 8 0 0 2 9 0 0 2 A 0 0 2 B 0 0 2 C 0 0 2 D 0 0 2 E 0 0 2 F 0 0 3 0 0 0 3 1 0 0 3 2 0 0 3 3 0 0 3 4 0 0 3 5 0 0 3 6 0 0 3 7 0 0 3 8 0 0 3 9 0 0 3 A 0 0 3 B 0 0 3 C 0 0 3 D 0 0 3 E

)

0 0 3 F

T i m e r 1 ( T 1 )

1 6

T i m e r 2 ( T 2 )

1 6

T i m e r 3 ( T 3 )

1 6

T i m e r 4 ( T 4 )

1 6

T i m e r 5 ( T 5 )

1 6

T i m e r 6 ( T 6 )

1 6

P W M c o n t r o l r e g i s t e r ( P W M C O N )

1 6

T i m e r 6 P W M r e g i s t e r ( T 6 P W M )

1 6

T i m e r 1 2 m o d e r e g i s t e r ( T 1 2 M )

1 6

T i m e r 3 4 m o d e r e g i s t e r ( T 3 4 M )

1 6

T i m e r 5 6 m o d e r e g i s t e r ( T 5 6 M )

1 6

W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D T C O N )

1 6

T i m e r X ( l o w - o r d e r ) ( T X L )

1 6

T i m e r X ( h i g h - o r d e r ) ( T X H )

1 6

T i m e r X m o d e r e g i s t e r 1 ( T X M 1 ) T i m e r X m o d e r e g i s t e r 2 ( T X M 2 )

1 6

I n t e r r u p t i n t e r v a l d e t e r m i n a t i o n r e g i s t e r ( I I D )

1 6

I n t e r r u p t i n t e r v a l d e t e r m i n a t i o n c o n t r o l r e g i s t e r ( I I D C O N )

1 6 1 6

A - D c o n t r o l r e g i s t e r ( A D C O N )

1 6

A - D c o n v e r s i o n r e g i s t e r ( l o w - o r d e r ) ( A D L )

1 6

A - D c o n v e r s i o n r e g i s t e r ( h i g h - o r d e r ) ( A D H )

1 6 1 6 1 6 1 6

I n t e r r u p t s o u r c e s w i t c h r e g i s t e r ( I F R )

1 6

I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r

1 6

C P U m o d e r e g i s t e r ( C P U M ) I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 )

1 6

I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 )

1 6

I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 )

1 6

I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 )

( I N T E D G E )

0 E F 0 0 E F 1 0 E F 2 0 E F 3 0 E F 4 0 E F 5 0 E F 6 0 E F 7

P u l l - u p c o n t r o l r e g i s t e r 1 ( P U L L 1 )

1 6

P u l l - u p c o n t r o l r e g i s t e r 2 ( P U L L 2 )

1 6 1 6 1 6

F L D C m o d e r e g i s t e r ( F L D M )

1 6

T d i s p t i m e s e t r e g i s t e r ( T D I S P )

1 6

T o f f 1 t i m e s e t r e g i s t e r ( T O F F 1 )

1 6 1 6

T o f f 2 t i m e s e t r e g i s t e r ( T O F F 2 )

0 E F 8 0 E F 9 0 E F A 0 E F B 0 E F C 0 E F D 0 E F E 0 E F F

F L D d a t a p o i n t e r ( F L D D P )

1 6

P o r t P 0 F L D / p o r t s w i t c h r e g i s t e r ( P 0 F P R )

1 6

P o r t P 2 F L D / p o r t s w i t c h r e g i s t e r ( P 2 F P R )

1 6

P o r t P 8 F L D / p o r t s w i t c h r e g i s t e r ( P 8 F P R )

N P o r t P 8 F L D o u t p u t c o n t r o l r e g i s t e r ( P 8 F L D

1 6 1 6

B u z z e r o u t p u t c o n t r o l r e g i s t e r ( B U Z C O N )

1 6 1 6

)

Fig. 9 Memory map of special function register (SFR)

12

I/O PORTS [Direction Registers] PiD

The 38B4 group has 51 programmable I/O pins arranged in eight individual I/O ports (P0, P2, P40–P46, and P5–P9). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to “0”) are floating and the value of that pin can be read. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

[High-Breakdown-Voltage Output Ports]

The 38B4 group has 5 ports with high-breakdown-voltage pins (ports P0–P3 and P80–P83). The high-breakdown-voltage ports have Pchannel open-drain output with Vcc- 45 V of breakdown voltage. Each pin in ports P0, P1, and P3 has an internal pull-down resistor connected to VEE. At reset, the P-channel output transistor of each port latch is turned off, so that it goes to VEE level (“L”) by the pull-down resistor. Writing “1” (weak drivability) to bit 7 of the FLDC mode register (address 0EF416) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode register is set to “0” (strong drivability).

[Pull-up Control Register] PULL

Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to “1” and the corresponding port direction registers are set to input mode.

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b 7

Fig. 10 Structure of pull-up control registers

PULL2)

b 0

P u l l - u p c o n t r o l r e g i s t e r 1 ( P U L L 1 : a d d r e s s 0 E F 0

P 50, P 51 p u l l - u p c o n t r o l b i t P

2,

53 p u l l - u p c o n t r o l b i t

P 5 P

P 5

4,

55 p u l l - u p c o n t r o l b i t

P

6,

57 p u l l - u p c o n t r o l b i t

P 5

p u l l - u p c o n t r o l b i

1

P 6 P P 6

2,

63 p u l l - u p c o n t r o l b i t

P

4,

65 p u l l - u p c o n t r o l b i t

P 6 N o t u s e d

( r e t u r n s “ 0 ” w h e n r e a d )

b 0

P u l l - u p c o n t r o l r e g i s t e r 2 ( P U L L 2 : a d d r e s s 0 E F 1

P 70, P 71 p u l l - u p c o n t r o l b i t P P 7

2,

73 p u l l - u p c o n t r o l b i t

P

4,

75 p u l l - u p c o n t r o l b i t

P 7 P P 7

6,

77 p u l l - u p c o n t r o l b i t

P

4,

85 p u l l - u p c o n t r o l b i t

P 8 P

6,

87 p u l l - u p c o n t r o l b i t

P 8 P

P 9

0,

91 p u l l - u p c o n t r o l b i t

N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )

1

6)

t

1

6)

0 : N o p u l l - u p 1 : P u l l - u p

(PULL1 and

13

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 6 List of I/O port functions (1)

zPin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No.

P00/FLD8– Port P0 Input/output, CMOS compatible input level FLD automatic display function FLDC mode register (1) P07/FLD15 individual bits High-breakdown voltage P-

channel open-drain output

with pull-down resistor P10/FLD16– Port P1 Output High-breakdown voltage P- FLDC mode register (2) P17/FLD23 channel open-drain output

with pull-down resistor P20/BUZ02/ Port P2 Input/output, Low-voltage input level Buzzer output (P20) FLDC mode register (3) FLD0 individual bits High-breakdown voltage P- FLD automatic display function P21/FLD1– channel open-drain output FLD automatic display function P27/FLD7 P30/FLD24– Port P3 Output High-breakdown voltage P- FLDC mode register (2) P37/FLD31 channel open-drain output

with pull-down resistor P40/INT0, Port P4 Input/output, CMOS compatible input level External interrupt input P41/INT1 individual bits N-channel open-drain output In the mask option type P, INT3 P42/INT3 cannot be used. P43/BUZ01 Buzzer output P44/PWM1 PWM output Timer 56 mode register (6) P45/T1OUT Timer output Timer 12 mode register (8-1) P46/T3OUT Timer output Timer 34 mode register (8-2) P47/INT2 Input CMOS compatible input level External interrput input I

P50/SIN1 Port P5 Input/output, CMOS compatible input level Serial I/O1 function I/O P51/SOUT1, individual bits CMOS 3-state output (11) P52/SCLK11, P53/SCLK12 P54/RXD Serial I/O2 function I/O Serial I/O2 control register (10) P55/TXD, UART control register (11) P56/SCLK21 P57/SRDY2/ (12) SCLK22 P60/CNTR1 Port P6 CMOS compatible input level External count input

N-channel open-drain output In the mask option type P, (7-2) P61/CNTR0/ CMOS compatible input level CNTR1 cannot be used. (13) CNTR2 CMOS 3-state output P62/SRDY1/ Serial I/O1 function I/O AN8 A-D conversion input A-D control register P63/AN9 A-D conversion input A-D control register (15)

Dimmer signal output P8FLD output control bit P64/INT4/ Serial I/O1 function I/O SBUSY1/

AN10

P65/SSTB1/ Serial I/O1 function I/O AN11 A-D conversion input A-D control register P70/AN0– Port P7 A-D conversion input A-D control register (15) P77/AN7

A-D conversion input A-D control register

External interrupt input

Port P0FLD/port switch register

Port P2FLD/port switch register Buzzer output control register

Interrupt edge selection register

(7-

1) (7-2)

Buzzer output control register

nterrupt edge selection register Interrupt interval determination control register Serial I/O1 control register 1, 2

Interrupt edge selection register

Serial I/O1 control register 1, 2

Interrupt edge selection register Serial I/O1 control register 1, 2

(1)

(5)

(4)

(9)

(10)

(7-1)

(14)

(16)

(17)

14

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 7 List of I/O port functions (2)

Pin Name Input/Output I/O Format Non-Port Function Related SFRs Ref.No.

P80/FLD32– Port P8 Input/output, Low-voltage input level FLD automatic display function FLDC mode register (1) P83/FLD35 individual bits High-breakdown voltage P-

channel open-drain output P84/FLD36 Low-voltage input level (18) P85/RTP0/ CMOS 3-state output FLD automatic display function FLDC mode register (19) FLD37, Real time port output P86/RTP1/ Timer X mode register 2 FLD38 P87/PWM0/ FLD automatic display function FLDC mode register (20) FLD39 PWM output

P90/XCIN Port P9 CMOS compatible input level Sub-clock generating circuit I/O CPU mode register (21) P91/XCOUT CMOS 3-state output (22)

Notes 1 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.

2 : How to use double-function ports as function I/O ports, refer to the applicable sections.

Port P8FLD/port switch register

Port P8FLD/port switch register PWM control register

15

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 ) P o r t s P 0 , P 21– P 27, P 80– P 8

F L D / P o r t s w i t c h r e g i s t e r

D i m m e r s i g n a l ( N o t e 1 )

L o c a l d a t a b u s

D a t a b u s

( 3 ) P o r t P 2

L o c a l d a t a b u s

D a t a b u s

( 5 ) P o r t s P 40, P 4

D i r e c t i o n r e g i s t e r

P o r t l a t c h

0

F L D / P o r t s w i t c h r e g i s t e r

D i m m e r s i g n a l ( N o t e 1 )

D i r e c t i o n r e g i s t e r

P o r t l a t c h

1

3

B u z z e r c o n t r o l s i g n a l

B u z z e r s i g n a l o u t p u t

r e a d

V

E E

*

( N o t e 2 )

V

E E

*

( N o t e 2 )

( 2 ) P o r t s P 1 , P 3

L o c a l d a t a b u s

D a t a b u s

( 4 ) P o r t P 4

( 6 ) P o r t P 4

3

D a t a b u s

4

T i m e r 6 o u t p u t s e l e c t i o n b i t

D i m m e r s i g n a l ( N o t e 1 )

P o r t l a t c h

D i r e c t i o n r e g i s t e r

P o r t l a t c h

B u z z e r c o n t r o l s i g n a l

B u z z e r s i g n a l o u t p u t

r e a d

*

V

E E

#

D i r e c t i o n r e g i s t e r

D a t a b u s

I N T

0

,

I N T

P o r t l a t c h

1

i n t e r r u p t i n p u t

Fig. 11 Port block diagram (1)

D i r e c t i o n r e g i s t e r

D a t a b u s

* H i g h - b r e a k d o w n - v o l t a g e P - c h a n n e l t r a n s i s t o r # M i d d l e - b r e a k d o w n - v o l t a g e N - c h a n n e l t r a n s i s t o r

N o t e s 1 : T h e d i m m e r s i g n a l s e t s t h e T o f f t i m i n g .

2 : A p u l l - d o w n r e s i s t o r i s n o t b u i l t i n t o p o r t s P 2 a n d P 8 .

P o r t l a t c h

T i m e r 6 o u t p u t

#

r e a d

16

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 7 - 1 ) P o r t s P 42, P 6

D i r e c t i o n r e g i s t e r

I N T C N T R

P o r t l a t c h

3

i n t e r r u p t i n p u t

D a t a b u s

( 8 - 1 ) P o r t s P 45, P 4

T i m e r 1 o u t p u t b i t T i m e r 3 o u t p u t b i t

D i r e c t i o n r e g i s t e r

D a t a b u s

T i m e r 1 o u t p u t T i m e r 3 o u t p u t

( 9 ) P o r t P 4

7

0

1

i n p u t

6

P o r t l a t c h

( 7 - 2 ) P o r t s P 42, P 60 ( m a s k o p t i o n t y p e P )

D i r e c t i o n r e g i s t e r

#

D a t a b u s

P o r t l a t c h

r e a d

#

( 8 - 2 ) P o r t s P 45, P 46 ( m a s k o p t i o n t y p e P )

T i m e r 1 o u t p u t b i t T i m e r 3 o u t p u t b i t

D i r e c t i o n r e g i s t e r

#

D a t a b u s

( 1 0 ) P o r t s P 50, P 5

P o r t l a t c h

T i m e r 1 o u t p u t T i m e r 3 o u t p u t

4

#

r e a d

D a t a b u s

I N T2 i n t e r r u p t i n p u t

Fig. 12 Port block diagram (2)

P u l l - u p c o n t r o l

D i r e c t i o n r e g i s t e r

D a t a b u s

# M i d d l e - b r e a k d o w n - v o l t a g e N - c h a n n e l t r a n s i s t o r

P o r t l a t c h

S e r i a l I / O i n p u t

17

MITSUBISHI MICROCOMPUTERS

K

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 1 ) P o r t s P 51– P 53, P 55, P 5

P - c h a n n e l o u t p u t d i s a b l e s i g n a l ( P 51, P 55)

S e r i a l I / O 2 m o d e s e l e c t i o n b i t

D a t a b u s

( 1 3 ) P o r t P 6

T i m e r X o p e r a t i n g m o d e b i t

O u t p u t O F F c o n t r o l s i g n a l

D i r e c t i o n r e g i s t e r

P o r t l a t c h

T

X

D , S

O U T

o r S

C L

S e r i a l c l o c k i n p u t

1

D i r e c t i o n r e g i s t e r

6

P 52, P 53, P 5

P u l l - u p c o n t r o l

6

P u l l - u p c o n t r o l

( 1 2 ) P o r t P 5

D a t a b u s

( 1 4 ) P o r t P 6

P 62/ S p i n c o n t r o l b i t

7

S

R D Y 2

o u t p u t e n a b l e b i t

D i r e c t i o n r e g i s t e r

P o r t l a t c h

S e r i a l r e a d y o u t p u t

S e r i a l c l o c k i n p u t

2

R D Y 1 •

P 64/ S

B U S Y 1

D i r e c t i o n r e g i s t e r

P u l l - u p c o n t r o l

D a t a b u s

P o r t l a t c h

T i m e r X o u t p u t

T i m e r 2 , T i m e r X e x t e r n a l c l o c k i n p u t

( 1 5 ) P o r t s P 63, P 7

D i m m e r o u t p u t c o n t r o l b i t ( P 6

D a t a b u s

D i m m e r s i g n a l o u t p u t ( P 63)

C N T R0, C N T R

D i r e c t i o n r e g i s t e r

P o r t l a t c h

A - D c o n v e r s i o n i n p u t

2

i n p u t

P u l l - u p c o n t r o l

3

)

A n a l o g i n p u t p i n s e l e c t i o n b i t

D a t a b u s

S e r i a l r e a d y o u t p u t

( 1 6 ) P o r t P 6

P 62/ S p i n c o n t r o l b i t

D a t a b u s

I N T

4

i n t e r r u p t i n p u t , S

P o r t l a t c h

4

R D Y 1 •

P 64/ S

D i r e c t i o n r e g i s t e r

P o r t l a t c h

S

B U S Y 1

o u t p u t

S e r i a l r e a d y i n p u t

A - D c o n v e r s i o n i n p u t

A n a l o g i n p u t p i n s e l e c t i o n b i t

B U S Y 1

i n p u t

A - D c o n v e r s i o n i n p u t

P u l l - u p c o n t r o l

A n a l o g i n p u t p i n s e l e c t i o n b i t

Fig. 13 Port block diagram (3)

18

MITSUBISHI MICROCOMPUTERS

r

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

( 1 7 ) P o r t P 6

D a t a b u s

( 1 9 ) P o r t s P 8

L o c a l d a t a b u s

D a t a b u s

P 65/ S

5

S T B 1

F L D / P o r t s w i t c h r e g i s t e r

p i n c o n t r o l b i t

D i r e c t i o n r e g i s t e r

P o r t l a t c h

S

S T B 1

o u t p u t

5

,

P 8

6

D i m m e r s i g n a l

D i r e c t i o n r e g i s t e r

P o r t l a t c h

P u l l - u p c o n t r o l

A - D c o n v e r s i o n i n p u t

( N o t e )

P u l l - u p c o n t r o l

R e a l t i m e p o r t c o n t r o l b i t

( 1 8 ) P o r t P 8

L o c a l d a t a b u s

D a t a b u s

( 2 0 ) P o r t P 8

L o c a l d a t a b u s

D a t a b u s

4

7

D i m m e r s i g n a l

F L D / P o r t s w i t c h r e g i s t e r

D i r e c t i o n r e g i s t e r

P o r t l a t c h

D i m m e r s i g n a l

F L D / P o r t s w i t c h r e g i s t e r

D i r e c t i o n r e g i s t e r

P o r t l a t c h

( N o t e )

P u l l - u p c o n t r o l

P 87/ P W M o u t p u t e n a b l e b i t

( 2 1 ) P o r t P 9

D a t a b u s

0

D i r e c t i o n r e g i s t e

P o r t l a t c h

Fig. 14 Port block diagram (4)

R T P o u t p u t

P u l l - u p c o n t r o l

P o r t X c s w i t c h b i t

S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u t

( 2 2 ) P o r t P 9

D a t a b u s

* H i g h - b r e a k d o w n - v o l t a g e P - c h a n n e l t r a n s i s t o r N o t e : T h e d i m m e r s i g n a l s e t s t h e T o f f t i m i n g .

1

D i r e c t i o n r e g i s t e

P o r t l a t c h

P W M

0

o u t p u t

P o r t X c s w i t c h b i t

P u l l - u p c o n t r o l

P o r t P 9

O s c i l l a t o

0

P o r t X c s w i t c h b i t

19

INTERRUPTS

Interrupts occur by twenty one sources: five external, fifteen internal, and one software.

Interrupt Control

Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first.

Interrupt Operation

Upon acceptance of an interrupt the following operations are automatically performed:

1. The contents of the program counter and processor status register are automatically pushed onto the stack.

2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.

3. The interrupt jump destination address is read from the vector table into the program counter.

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

■Notes on Use

When the active edge of an external interrupt (INT0–INT4) is set or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence:

(1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (3) Clear the set interrupt request bit to “0”. (4) Enable the external interrupt which is selected.

20

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 8 Interrupt vector addresses and priority

Interrupt Source Priority Remarks

Reset (Note 2) 1 FFFD16 FFFC16 At reset Non-maskable INT0 2 FFFB16 FFFA16 At detection of either rising or falling edge of External interrupt

INT1 3 FFF916 FFF816 At detection of either rising or falling edge of External interrupt

INT2 4 FFF716 FFF616 At detection of either rising or falling edge of External interrupt

Remote control/ At 8-bit counter overflow Valid when interrupt interval counter overflow determination is operating Serial I/O1 5 FFF516 FFF416 At completion of data transfer Valid when serial I/O ordinary

Serial I/O auto- At completion of the last data transfer Valid when serial I/O automatic matic transfer transfer mode is selected Timer X 6 FFF316 FFF216 At timer X underflow Timer 1 7 FFF116 FFF016 At timer 1 underflow Timer 2 8 FFEF16 FFEE16 At timer 2 underflow STP release timer underflow Timer 3 9 FFED16 FFEC16 At timer 3 underflow Timer 4 10 FFEB16 FFEA16 At timer 4 underflow (Note 3) Timer 5 11 FFE916 FFE816 At timer 5 underflow Timer 6 12 FFE716 FFE616 At timer 6 underflow Serial I/O2 receive INT3 14 FFE316 FFE216 At detection of either rising or falling edge of External interrupt (Note 4)

Serial I/O2 transmit INT4 15 FFE116 FFE016 At detection of either rising or falling edge of External interrupt

A-D conversion At completion of A-D conversion FLD blanking 16 FFDF16 FFDE16 At falling edge of the last timing immediately Valid when FLD blanking

FLD digit At rising edge of digit (each timing) BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt

Notes 1 : Vector addresses contain interrupt jump destination addresses.

2 : Reset function in the same way as an interrupt with the highest priority. 3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used. 4 : In the mask option type P, INT3 interrupt cannot be used.

Vector Addresses (Note 1) Interrupt Request

High Low Generating Conditions

INT0 input (active edge selectable)

INT1 input (active edge selectable)

INT2 input (active edge selectable)

mode is selected

13 FFE516 FFE416 At completion of serial I/O2 data receive

INT3 input (active edge selectable) At completion of serial I/O2 data transmit

INT4 input (active edge selectable)

Valid when INT4 interrupt is selected Valid when A-D conversion is selected

before blanking period starts interrupt is selected

Valid when FLD digit interrupt is selected

21

I n t e r r u p t r e q u e s t b i t

I n t e r r u p t e n a b l e b i t

I n t e r r u p t d i s a b l e f l a g I

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 15 Interrupt control

b 7 b 0

B R K i n s t r u c t i o n

R e s e t

I n t e r r u p t s o u r c e s w i t c h r e g i s t e r

( I F R : a d d r e s s 0 0 3 9

I N T3/ s e r i a l I / O 2 t r a n s m i t i n t e r r u p t s w i t c h b i t ( N o t e 1 ) 0 : I N T 1 : S e r i a l I / O 2 t r a n s m i t I N T

4

/ A D c o n v e r s i o n i n t e r r u p t s w i t c h b i t 0 : I N T 1 : A - D c o n v e r s i o n N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) ( D o n o t w r i t e “ 1 ” t o t h e s e b i t s . )

I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E : a d d r e s s 0 0 3 A

I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N T

1

i n t e r r u p t e d g e s e l e c t i o n b i t

2

i n t e r r u p t e d g e s e l e c t i o n b i t

I N T

3

i n t e r r u p t e d g e s e l e c t i o n b i t ( N o t e 1 )

I N T I N T

4

i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d ( r e t u r n “ 0 ” w h e n r e a d ) C N T R C N T R

I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 : a d d r e s s 0 0 3 C

I N T

0

i n t e r r u p t r e q u e s t b i t

1

i n t e r r u p t r e q u e s t b i t

I N T I N T

2

i n t e r r u p t r e q u e s t b i t R e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t r e q u e s t b i t S e r i a l I / O 1 i n t e r r u p t r e q u e s t b i t

S e r i a l I / O a u t o m a t i c t r a n s f e r i n t e r r u p t r e q u e s t b i t

T i m e r X i n t e r r u p t r e q u e s t b i t T i m e r 1 i n t e r r u p t r e q u e s t b i t T i m e r 2 i n t e r r u p t r e q u e s t b i t T i m e r 3 i n t e r r u p t r e q u e s t b i t

I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 : a d d r e s s 0 0 3 E

I N T0 i n t e r r u p t e n a b l e b i t

1

i n t e r r u p t e n a b l e b i t

I N T I N T

2

i n t e r r u p t e n a b l e b i t R e m o t e c o n t r o l l e r / c o u n t e r o v e r f l o w i n t e r r u p t e n a b l e b i t S e r i a l I / O 1 i n t e r r u p t e n a b l e b i t

S e r i a l I / O a u t o m a t i c t r a n s f e r i n t e r r u p t e n a b l e b i t

T i m e r X i n t e r r u p t e n a b l e b i t T i m e r 1 i n t e r r u p t e n a b l e b i t T i m e r 2 i n t e r r u p t e n a b l e b i t T i m e r 3 i n t e r r u p t e n a b l e b i t

1 6

)

3

i n t e r r u p t

4

i n t e r r u p t

0

p i n e d g e s w i t c h b i t

1

p i n e d g e s w i t c h b i t ( N o t e 1 )

i n t e r r u p t

1 6

)

1 6

)

0 : R i s i n g e d g e c o u n t 1 : F a l l i n g e d g e c o u n t

0 : F a l l i n g e d g e a c t i v e 1 : R i s i n g e d g e a c t i v e

b 7 b 0

0 : N o i n t e r r u p t r e q u e s t i s s u e d 1 : I n t e r r u p t r e q u e s t i s s u e d

b 7 b 0

0 : I n t e r r u p t d i s a b l e d 1 : I n t e r r u p t e n a b l e d

I n t e r r u p t r e q u e s t

I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 : a d d r e s s 0 0 3 D

T i m e r 4 i n t e r r u p t r e q u e s t b i t ( N o t e 2 ) T i m e r 5 i n t e r r u p t r e q u e s t b i t T i m e r 6 i n t e r r u p t r e q u e s t b i t S e r i a l I / O 2 r e c e i v e i n t e r r u p t r e q u e s t b i t I N T

3

/ s e r i a l I / O 2 t r a n s m i t i n t e r r u p t r e q u e s t b i t ( N o t e 2 )

4

i n t e r r u p t r e q u e s t b i t

I N T A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t F L D b l a n k i n g i n t e r r u p t r e q u e s t b i t F L D d i g i t i n t e r r u p t r e q u e s t b i t N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )

I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 : a d d r e s s 0 0 3 F

T i m e r 4 i n t e r r u p t e n a b l e b i t ( N o t e 3 ) T i m e r 5 i n t e r r u p t e n a b l e b i t T i m e r 6 i n t e r r u p t e n a b l e b i t S e r i a l I / O 2 r e c e i v e i n t e r r u p t e n a b l e b i t

I N T3/ s e r i a l I / O 2 t r a n s m i t i n t e r r u p t e n a b l e b i t ( N o t e 3 ) I N T

4

i n t e r r u p t e n a b l e b i t A D c o n v e r s i o n i n t e r r u p t e n a b l e b i t F L D b l a n k i n g i n t e r r u p t e n a b l e b i t F L D d i g i t i n t e r r u p t e n a b l e b i t N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) ( D o n o t w r i t e “ 1 ” t o t h i s b i t . )

1 6

)

1 6

)

N o t e s 1 : I n t h e m a s k o p t i o n t y p e P , t h e s e b i t s a r e n o t a v a i l a b l e b e c a u s e C N T R

2 : I n t h e m a s k o p t i o n t y p e P , i f t i m e r 4 i n t e r r u p t w h o s e c o u n t s o u r c e i s C N T R 3 : I n t h e m a s k o p t i o n t y p e P , t i m e r 4 i n t e r r u p t w h o s e c o u n t s o u r c e i s C N T R

Fig. 16 Structure of interrupt related registers

22

1

f u n c t i o n a n d I N T3 f u n c t i o n c a n n o t b e u s e d .

1

i n p u t a n d I N T3 i n t e r r u p t a r e s e l e c t e d , t h e s e b i t s d o n o t b e c o m e “ 1 ” .

1

i n p u t a n d I N T3 i n t e r r u p t a r e n o t a v a i l a b l e .

TIMERS 8-Bit Timer

The 38B4 group has six built-in timers : Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, and Timer 6. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches “0016”, an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The count can be stopped by setting the stop bit of each timer to “1”. The internal system clock can be set to either the high-speed mode or low-speed mode with the CPU mode register. At the same time, timer internal count source is switched to either f(XIN) or f(XCIN).

●Timer 1, Timer 2

The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P45/T1OUT pin. The active edge of the external clock CNTR0 can be switched with the bit 6 of the interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to “0”, timer 1 is set to “FF16”, and timer 2 is set to “0116”.

●Timer 3, Timer 4

The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P46/T3OUT pin. The active edge of the external clock CNTR1 (Note) can be switched with the bit 7 of the interrupt edge selection register. Note: In the mask option type P, CNTR1 function cannot be used.

●Timer 5, Timer 6

The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P44/PWM1 pin.

(1) Timer 6 PWM1 mode

Timer 6 can output a PWM rectangular waveform with “H” duty cycle n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register (refer to Figure 19). The n is the value set in timer 6 latch (address

002516) and m is the value in the timer 6 PWM register (address

002716). If n is “0”, the PWM output is “L”, if m is “0”, the PWM output is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur at the rising edge of the PWM output.

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b 7

N o t e : I n t h e m a s k o p t i o n t y p e P , C N T R1 f u n c t i o n c a n n o t b e u s e d .

b 0

T i m e r 1 2 m o d e r e g i s t e r ( T 1 2 M : a d d r e s s 0 0 2 8

/ 1 6 o r f (

/ 3

I

/ 6 4 o r f (

/ 1 2

/ 8 o r f (

/ 1

I

T i m e r 1 c o u n t s t o p b i t 0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 2 c o u n t s t o p b i t 0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( X

I N)

0 1 : f ( X

C I N)

1 0 : f ( X

I N)

1 1 : f ( X

I N)

T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : U n d e r f l o w o f T i m e r 1 0 1 : f ( X

C I N)

1 0 : E x t e r n a l c o u n t i n p u t C N T R 1 1 : N o t a v a i l a b l e T i m e r 1 o u t p u t s e l e c t i o n b i t ( P 4 0 : I / O p o r t 1 : T i m e r 1 o u t p u t N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) ( D o n o t w r i t e “ 1 ” t o t h i s b i t . )

b 0

T i m e r 3 4 m o d e r e g i s t e r ( T 3 4 M : a d d r e s s 0 0 2 9

/ 8 o r f (

/ 1

/ 1 6 o r f (

/ 3

I

/ 6 4 o r f (

/ 1 2

/ 8 o r f (

/ 1

I

N o t e

T i m e r 3 c o u n t s t o p b i t 0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 4 c o u n t s t o p b i t 0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( X

I N)

0 1 : U n d e r f l o w o f T i m e r 2 1 0 : f ( X

I N)

1 1 : f ( X

I N)

T i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( X

I N)

0 1 : U n d e r f l o w o f T i m e r 3 1 0 : E x t e r n a l c o u n t i n p u t C N T R 1 1 : N o t a v a i l a b l e T i m e r 3 o u t p u t s e l e c t i o n b i t ( P 4 0 : I / O p o r t 1 : T i m e r 3 o u t p u t N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) ( D o n o t w r i t e “ 1 ” t o t h i s b i t . )

b 0

T i m e r 5 6 m o d e r e g i s t e r ( T 5 6 M : a d d r e s s 0 0 2 A

/ 8 o r f (

/ 1

I

/ 8 o r f (

/ 1 T i m e r 5 c o u n t s t o p b i t

0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 6 c o u n t s t o p b i t 0 : C o u n t o p e r a t i o n 1 : C o u n t s t o p T i m e r 5 c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( X

I N)

1 : U n d e r f l o w o f T i m e r 4 T i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t 0 : T i m e r m o d e 1 : P W M m o d e T i m e r 6 c o u n t s o u r c e s e l e c t i o n b i t s 0 0 : f ( X

I N)

0 1 : U n d e r f l o w o f T i m e r 5 1 0 : U n d e r f l o w o f T i m e r 4 1 1 : N o t a v a i l a b l e T i m e r 6 ( P W M ) o u t p u t s e l e c t i o n b i t ( P 4 0 : I / O p o r t 1 : T i m e r 6 o u t p u t N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) ( D o n o t w r i t e “ 1 ” t o t h i s b i t . )

1 6)

XC

N)

6

XC

N)

XC

N)

1 6)

XC

N)

XC

N)

XC

N)

XC

N)

1 6)

XC

N)

6

XC

N)

2

8

0

5)

6

2

8

6

1 (

6)

6

)

4)

Fig. 17 Structure of timer related register

23

I

T

XC

XI

O U

P 45/ T1

P 61/ C N T R0/ C N T R2

MITSUBISHI MICROCOMPUTERS

38B4 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

D a t a b u s

N

1 / 2

I n t e r n a l s y s t e m c l o c k

“ 1 ”

s e l e c t i o n b i t

N

“ 0 ”

1 / 8 1 / 1 6 1 / 6 4

l a t c P 4

5

h

T i m e r 1 c o u n t s o u r c e

“ 0 1 ”

s e l e c t i o n b i t s

“ 0 0 ” “ 1 0 ” “ 1 1 ”

T i m e r 1 c o u n t s t o p b i t

T i m e r 1 l a t c h ( 8 )

T i m e r 1 ( 8 )

F F

1 6

1 / 2

T i m e r 1 o u t p u t s e l e c t i o n b i t

d i r e c t i o n r e g i s t e P 4

5

R i s i n g / F a l l i n g

a c t i v e e d g e s w i t c h

T i m e r 2 c o u n t s o u r c e

“ 0 0 ”

s e l e c t i o n b i t s

r

“ 0 1 ”

“ 1 0 ”

T i m e r 2 c o u n t s t o p b i t

T i m e r 2 l a t c h ( 8 )

T i m e r 2 ( 8 )

0 1

1 6

R E S E T

S T P i n s t r u c t i o n

T i m e r 1 i n t e r r u p t r e q u e s t

T i m e r 2 i n t e r r u p t r e q u e s t

U

P 46/ T 3O

P 60/ C N T R1

( N o t e )

T i m e r 3 c o u n t s t o p b i t

T i m e r 4 c o u n t s t o p b i t

T i m e r 5 c o u n t s t o p b i t

T i m e r 6 c o u n t s t o p b i t

T i m e r 3 l a t c h ( 8 )

T i m e r 3 ( 8 )

T i m e r 4 l a t c h ( 8 )

T i m e r 4 ( 8 )

T i m e r 5 l a t c h ( 8 )

T i m e r 5 ( 8 )

T i m e r 6 l a t c h ( 8 )

T i m e r 6 ( 8 )

T i m e r 3 i n t e r r u p t r e q u e s t

T i m e r 4 i n t e r r u p t r e q u e s t

T i m e r 5 i n t e r r u p t r e q u e s t

T i m e r 6 i n t e r r u p t r e q u e s t

T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t s

“ 0 1 ”

l a t c P 4

6

T

h

1 / 2

T i m e r 3 o u t p u t s e l e c t i o n b i t

d i r e c t i o n r e g i s t e P 4

6

r

“ 0 0 ” “ 1 0 ” “ 1 1 ”

“ 0 1 ”

“ 0 0 ”

T i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t s

“ 1 0 ”

R i s i n g / F a l l i n g

a c t i v e e d g e s w i t c h

T i m e r 5 c o u n t s o u r c e

“ 1 ”

s e l e c t i o n b i t

“ 0 ”

T i m e r 6 c o u n t s o u r c e

“ 0 1 ”

s e l e c t i o n b i t s

“ 0 0 ”

“ 1 0 ”

Fig. 18 Block diagram of timer

24

P 44/ P W M1

l a t c P 4

4

h

T i m e r 6 o u t p u t s e l e c t i o n b i t

d i r e c t i o n r e g i s t e P 4

4

r

“ 1 ”

“ 0 ”

T i m e r 6 o p e r a t i o n m o d e s e l e c t i o n b i t

T i m e r 6 P W M r e g i s t e r ( 8 )

P W M

1 / 2

f u n c t i o n c a n n o t b e u s e d N o t e : I n t h e m a s k o p t i o n t y p e P , C N T R

1

.