MITEL SP5669, SP5669KG, SP5669MP1S, SP5669MP1T Datasheet

Ordering Information

SP5669/KG/MP1S (Tubes) SP5669/KG/MP1T (Tape and reel)

The comparison frequency is obtained either from an on–chip crystal controlled oscillator, or from an external source. The oscillator frequency F

ref

or the comparison

frequency F

comp

may be switched to the REF/COMP output. This feature is ideally suited to providing the reference frequency for a second synthesiser such as in a double conversion tuner (see Fig. 8).

The synthesiser is controlled via an I 2 C bus, and responds to one of four programmable addresses which are selected by applying a specific voltage to the ‘address’ input. This feature enables two or more synthesisers to be used in a system.

The device contains four switching ports P0–P3 and a 5–level ADC. The output of the ADC can be read via the I 2 C bus.

The device also contains a varactor line disable and chargepump disable facility.

Features

● Complete 2.7GHz single chip system

● Compatible with UK DTT offset requirements

● Optimised for low phase noise

● Selectable divide by two prescaler

● Selectable reference division ratio

● Selectable reference/comparison frequency output

● Selectable charge pump current

● Four selectable I

C bus address

● 5–level ADC

● Pin compatible with the SP5658 3–wire bus

controlled synthesiser and SP5659 I2C bus synthesiser and SP5659 I2C bus synthesiser ESD protection; (Normal ESD handling procedures should be observed)

Applications

● Complete 2.7GHz single chip system

● Optimised for low phase noise

SP5669

2.7GHz I2C Bus Controlled Synthesiser

Preliminary Information

DS4852 - Issue 2.1 May 1999

Description

The SP5669 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz and offers step size compatible with DTT offset requirements.

The RF preamplifier drives a divide by two prescaler which can be disabled for applications up to 2GHz, allowing direct interfacing with the programmable divider so enabling a step size equal to the comparison frequency. For applications up to 2.7GHz the divide by two is enabled, giving a step size of twice the comparison frequency.

SP5669

Figure. 1 Pin connections - top view

1161

MP16

CHARGE PUMP

CRYSTAL

REF/COMP

ADDRESS

SDA

SCL PORT P3 PORT P2

DRIVE Vee

RF INPUT RF INPUT Vcc ADC PORT P0 PORT P1

2 3 4 5 6 7 89

1 BIT

17 BIT LA

TCH

4 BIT

TCH

AND

PORT

INTERFACE

TRANSCEIVER

CRYSTAL

PUMP

DRIVE

ADDRESS

ADC

SDA SCL

PORT P3 PORT P2

INPUTS

4 5 6

PROGRAMMABLE

DIVIDER

PUMP

REFERENCE

DIVIDER

PHASE

COMP

2 BIT

OSC 2

987

2/1

13 BIT

COUNT

4 BIT

COUNT

4 BIT

PORT P1 PORT P0

16/17

C1, C0

REF/COMP

3 BIT

ADC

5 BIT LA

TCH and

MODE CONTROL

LOGIC

(see Fig. 5)

CHARGE

LATCHLATCH

LOCK

DETECT

LATCH

DIVIDE RA

TIO

PRE AMP

FPD/2

P0 TEST

CONTROL

POWER ON

DETECT

POR

DISABLE

MODE

CONTROL

CHARGE

(see Fig. 3)

comp

ref

Figure. 2 Block diagram

SP5669

ELECTRICAL CHARACTERISTICS

T amb = –20°C to +80°C, V

= +4.5V to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristics Pin Value Units Conditions

Min Typ Max

Supply current, I

12 68 85 mA V CC = 5V prescaler enabled, PE = 1 58 73 mAV

= 5V prescaler disabled, PE = 0

RF input voltage 13, 14 40 300 mV rms 300MHz to 2.7GHz Prescaled

enabled, PE = 1, See Fig. 7b.

13, 14100 300 mV rms 80MHz Prescaler enabled,

PE=1, See Fig. 7b.

13,14 50 300 mV rms 80MHz to 2.0GHz Prescaler

disabled, PE = 0, See Fig. 7a. RF input impedance 13, 14 50 Ω Refer to Fig. 13 RF input capacitance 13, 14 2 pF Refer to Fig. 13 SDA, SCL 5, 6

Input High voltage 3 5.5 V Input Low voltage 0 1.5 V Input High current 10 µA Input voltage = V

Input Low Current –10 µA Input voltage = V

LeakageCurrent 10 µAV

= V

Input hysteresis 0.8 V SDA Output voltage 5 0.4 V I sink = 3mA Charge pump output 1 See Fig. 6, V pin = 2V current Charge pump output 1 ± 3 ± 10 nA V pin1 = 2V leakage Charge pump drive output current 16 1 mAV pin16 = 0.7V Drive output saturation voltage when disabled 16 350 mV External reference input frequency 2 2 20 MHzAC coupled sinewave External reference input ampltude 2 200 500 mV p–pAC coupled sinewave Crystal frequency 2 4 16 MHz Crystal oscillator drive 2 35 mV p–p level Recommended crystal series resistance 10 200 Ω Applies to 4MHz crystal only.

‘Parallel resonant’ crystal. Figure quoted is under all conditions

including start up. Crystal oscillator negative resistance 2 400 Ω Includes temperature and

process tolerances. REF/COMP output 3 Voltage 350 mV p–p AC coupled output. Output

enabled,RE=1. See Note 1.

SP5669

Electrical Chacteristics (cont.)

T amb = –20°C to 80 °C, V CC =+ 4.5V to + 5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristics Pin Value Units Conditions

Min Typ Max

Comparison frequency 2 MHz Equivalent phase noise at phase detector –148 dBC/Hz 6kHz loop BW, phase comparator

freq 250kHz. Figure measured @ 1kHz offset, SSB (within loop band width).

RF division ratio 240 131071 Prescaler disabled, PE = 0

480 262142 Prescaler enabled, PE = 1 Reference division ratio See Fig. 3 Output ports P0, P1, P2, P3 7,8,9,

10 Sink current 10 mA V port = 0.7V Leakage current 10 µA V port = 13.2V

ADC input voltage 11 See Table 4, Fig 4 ADC input current 11 ±10 µAV

≥ V input ≥ V

Address input current High 4 1 mA Input voltage =V

Address input current Low 4 –0.5 mA Input voltage =V

Note 1: If the REF/COMP output is not used, the output should be left open circuit or connected to V CC , and disabled by setting RE=0.

Absolute Maximum Ratings

All voltages are referred to VEE at 0V.

Characteristics Pin Value Units Conditions

Min Max

Supply Voltage, V

12 0.3 7 V RF input voltage 13,14 2.5 V p–p AC coupled as per application RF input DC offset 13,14 –0.3 V CC +0.3 V Port voltage 7–10 –0.3 14 V Port in off state

7–10 –0.3 6 V Port in on state Total port current 7–10 50 mA ADC input DC offset 11 –0.3 V CC +0.3 V REF/COMP output DC offset 3 –0.3 V

+0.3 V

Charge pump DC offset 1 –0.3 V

+0.3 V

Drive DC offset 16 –0.3 V

+0.3 V

Crystal oscillator DC offset 2 –0.3 V

+0.3 V

Address DC offset 4 –0.3 V

+0.3 V SDA and SCL DC offset 5, 6 –0.3 6V V Storage temperature –55 +150 °C Junction temperature +150 °C MP16 thermal resistance chip to ambient 111 °C/W chip to case 41 °C/W Power consumption at V CC =5.5V 468 mW All ports off, prescaler enabled ESD protection All 4 kV Mil Std 883 TM 3015

SP5669

Functional Description

The SP5669 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The block diagram is shown in Fig. 2.

The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces with the 17–bit fully programmable divider via a divide–by–two prescaler. For applications up to 2GHz RF input, the prescaler may be disabled so eliminating the degradation in phase noise due to prescaler action. The divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4–bits, and the M counter is 13–bits.

The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on–board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 15 ratios as detailed in Fig. 3.

The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. By invoking the device test modes as described in Fig. 5, the varactor drive output can be disabled so switching the external transistor ’off’ and allowing an external voltage to be written to the varactor line for tuner alignment purposes. Similarly, the charge pump may be also disabled to a high impedance state.

The programmable divider output Fpd/2 can be switched to port P0 by programming the device into test mode. The test modes are described in Fig. 5 high

Programming

The SP5669 is controlled by an I 2 C data bus. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesiser can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 1 and 2 in Fig. 4 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 3 in Fig.4 shows how the address is selected by applying a voltage to the ’address’ input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading.

Write Mode

With reference to Table 1, bytes 2 and 3 contain frequency information bits 2 14 –2 0 inclusive. Auxillary frequency bits 2 16 –2 15 are in byte 4. For most frequencies only bytes 2 and 3 will be required. The remainder of byte 4 and byte 5 control the prescaler enable, reference divider ratio (see Fig. 3), charge pump, REF/COMP output (see Fig. 5), output ports and test modes (see Fig. 5).

After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic ’0’ indicating byte 2 and a logic ’1’ indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous data is retained.

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