MITEL SP5668, SP5668KG, SP5668MP1S, SP5668MP1T Datasheet

The SP5668 is a single chip frequency synthesiser

designed for tuning systems up to 2.7GHz.

The RF preamplifer contains a divide by two prescaler which can be disabled for applications up to 2GHz so enabling a step size equal to the comparison frequency up to 2GHz and twice the comparison frequency up to 2.7GHz.

Comparison frequencies are obtained either from a crystal controlled on–chip oscillator or from an external source.

The device contains three switching ports, P0 – P2, together with an ’in–lock’ flag output. Various test modes including varactor disable and charge pump disable are also included.

FEATURES

■ Complete 2.7GHz single chip system

■ Optimised for low phase noise

■ Selectable divide by two prescaler

■ Selectable reference division ratio

■ Charge pump disable

■ Varactor line disable

■ ‘In–lock’ flag

■ Two selectable charge pump currents

■ Three switching ports

■ Reference frequency output

■ ESD protection (Normal ESD handling procedures

should be observed)

MP16

CHARGE PUMP

CAP Q1

CRYSTAL Q2

ENABLE

DATA

CLOCK

PORT P2

PORT P1/OC

DRIVE V

RF INPUT RF INPUT

LOCK REF PORT P0/OC

Fig. 1 Pin connections - top view

APPLICATIONS

■ SAT, TV, VCR and Cable tuning systems

■ Communications systems

ORDERING INFORMATION

SP5668/KG/MP1S (Tubes,) SP5668/KG/MP1T Tape and Reel)

SP5668

2.7GHz 3-Wire Bus Controlled Synthesiser

Preliminary Information

DS4538 - 1.6 January 1997

SP5668

Fig. 2 SP5668 block diagram

ELECTRICAL CHARACTERISTICS

AMB

= 120°C to +80°C, V

= +4.5 to +5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristic Pin Value Units Conditions

Min Typ Max

Supply current, Icc 12 65 81 mA Vcc = 5V Prescaler enabled, PE = 1

58 72 mA Vcc = 5V Prescaler disabled, PE = 0

RF input voltage 13, 14 100 300 mV

rms

100MHz Prescaler enabled, PE = 1 See Fig. 5b.

13, 14 40 300 mV

rms

300MHz - 2.7GHz Prescaler enabled, PE = 1, See Fig. 5b.

13,14 40 300 mV

rms

100MHz to 2.0GHz Prescaler

disabled, PE = 0, See Fig. 5a RF input impedance 13, 14 See Fig. 4. Data, Clock, Enable 4,5,6

Input high voltage 3 V

V Input low voltage 0 0.7 V Input high current 10 µA Input voltage = V

Input low current -10 µA Input voltage = V

Hysteresis 400 mV Clock Rate 6 500 kHz

REFERENCE

DIVIDER

See Table 1

INPUTS

PROGRAMMABLE

DIVIDER

÷ 16/17

÷ 2/1

4 BIT

COUNT

13 BIT

COUNT

comp

PHASE

COMP

CHARGE

PUMP

OSC

ref

REF

CRYSTAL

CHARGE

PUMP

DRIVE

LOCK

1 BIT

LATCH

3 BIT LATCH

(R0,R1,R2)

1 BIT

LATCH

FLOCK

1 BIT

LATCH

3 BIT

LATCH AND

PORT

INTERFACE

DATA

INTERFACE

DISABLE

18 BIT LATCH

ENABLE

CLOCK

DATA

4 5

P2P1P0

SP5668

ELECTRICAL CHARACTERISTICS (continued)

AMB

= 120°C to +80°C, V

Characteristic Pin Value Units Conditions

Min Typ Max

Bus timing 4, 5, 6

Data set up , t

300 ns See Fig. 3

Data hold, t

600 ns See Fig. 3

Enable set up, t

300 ns See Fig. 3

Enable hold , t

600 ns See Fig. 3

Clock to enable, t

300 ns See Fig. 3

Charge pump output 1 See Table 3, V

pin1

=2V Current Charge pump output 1 ±10 nA V

pin1

= 2V leakage Drive output current 16 1 mA V

PIN16

= 0.7V Drive output saturation 16 350 mV OS = 1 Voltage when disabled External reference input 3 2 20 MHz AC coupled sinewave frequency External reference input 3 200 500 mVp-p AC coupled sinewave amplitude Crystal frequency 3 4 12 MHz Recommended crystal 10 200 Ω Applies to 4MHz crystal only. Series resistance "Parallel resonant" crystal. Figure

quoted is under all conditions

including start up. Reference oscillator bias 3 200 µA See Fig. 11 current REF output voltage* 10 350 mVp-p AC coupled, 4MHz reference

frequency, See Fig. Phase detector comparison 4 MHz frequency Equivalent phase noise at dBc/Hz See **Note phase detector RF division ratio 240 131071 PE = 0, Prescaler disabled

480 262142 PE = 1, Prescaler enabled Reference division ratio See Table 1 Output ports P0-P2 7-9

Sink current 10 mA V

PORT

= 0.7V

Leakage current 10 µAV

PORT

= 13.2V

Lock output

Sink current 1 mA V

PIN10

= 0.7V, 'out of lock'

Leakage current 10 µA 'in lock'

* REF output should be connected to V

if unused

** Note: 1. -148dB @ 1KHz offset with 1MHz comparison frequency measured at the phase comparator.

2. When external reference is used, a high signal level is required for low phase noise.

SP5668

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to VEE at 0V Charateristics Pin Min Max Units Conditions Supply voltage, V

12 -0.3 7 V RF input voltage 13, 14 2.5 Vp-p RF input offset 13, 14 -0.3 VCC+0.3 V Port output voltage 7-9 -0.3 14 V Port in off state

7-9 -0.3 6 V Port in on state Total port current 7-9 50 mA REFoutput DC offset 10 -0.3 VCC+0.3 V Lock output DC offset 11 -0.3 V

+0.3 V Lock output current 11 10 mA Charge pump DC offset 1 -0.3 VCC+0.3 V Drive DC offset 16 -0.3 V

+0.3 V Crystal oscillator DC offset 2, 3 -0.3 V

+0.3 V Data, Clock & inputs 4,5,6 -0.3 V

+0.3 V Storage temperature -55 +150 °C Junction temperature +150 °C MP16 Thermal resistance Chip to ambient 111 °C/W Chip to case 41 °C/W Power consumption 407 mV All ports off, prescaler enabled at V

= 5.5V

ESD protection ALL 2 kV MIL-STD 883 TM3015

FUNCTIONAL DESCRIPTION

The SP5668 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The RF preamplifier contains a selectable divide by two for operation above 2.0GHz. Up to 2GHz the RF input interfaces directly with the programmable divider, so eliminating degradation in phase noise due to the prescaler action. The block diagram is shown in Fig.2.

The SP5668 is controlled by a standard 3–wire bus comprising data, clock and enable inputs. The programming word contains 27 bits. P0 - P2 are used for port selection, 217 - 20 set

the programmable divider ratio R2 - R0 select the reference division ratio (Table1). C0 sets the charge pump current (Table 3) and the remaining two bits T0, OS access test modes and disable the varactor drive (Table 2).The programming format is shown in Fig. 3.

The clock input is disabled by an enable low signal, data is therefore only clocked into the internal shift registers during an enable high and is loaded into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning.

The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the ÷ 2/1 selectable prescaler and then to the 17 bit fully programmable divider, which is of MN+A architecture. The M counter is 13 bit and the A counter 4. If bit PE is set to a 0 the prescaler is disabled; the control function PE cannot be used dynamically. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 8 ratios as described in Table 1.

The output of the phase comparator feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current is selected by bit C0 as described in Table 3.

The phase comparator also drives the lock detect circuit which generates a lock flag. 'In-lock' is indicated by a high impedance state on the lock output.

The crystal frequency Fref is available at the REF output. This may be used as the reference for a second synthesiser as shown in Fig. 6. The REF output is disabled by connecting the output, pin 3, to VCC.

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