MITEL SP5611 Datasheet

SP5611

1·3GHz Bidirectional I2C Bus Controlled Synthesiser

Advance Information

Supersedes February 1997 version, DS3758-4.1 DS3758 - 5.0 June 1998

The SP5611 is a single chip frequency synthesiser de­signed for TV tuning systems. Control data is entered in the
standard I2C BUS format. The device contains 4 addressable
bidirectional open collector ports, one of which is a 3-bit ADC.
The information on these ports can be read via the I

2

C BUS.
the device has 4 programmable addresses, programmed by
applying a specific input voltage to the P3 address select
input. This enables two or more synthesisers to be used in a
system.

FEATURES

■ Complete 1·3GHz Single Chip System

■ High Sensitivity RF Inputs

■ Programmable via I

2

C BUS

■ Low Power Consumption (5V, 20mA)

■

Low Radiation

■ Phase Lock Detector

■ Varactor Drive Amp Disable

■ 4 Bi-directional Controllable Outputs

■ 5-Level ADC

■ Variable I

■ ESD Protection: 4kV, Mil-Std-883C, Method 3015

2

C BUS Address for Multi-tuner Applications

(1)

■ Switchable 4512/1024 Reference Divider

■ Pin and Function Compatible with SP5511S

(1) Normal ESD handling precautions should be observed.

(2) The SP5511S does not have a switchable reference

division ratio.

(2)

CHARGE PUMP

CRYSTAL Q1
CRYSTAL Q2

SDA

SCL

†

I/O PORT P7

*

I/O PORT P6

†

I/O PORT P5

† = Logic level I/O port

*

= 3-bit ADC input

Fig. 1 Pin connections – top view

APPLICATIONS

■ Satellite TV

■ Cable Tuning Systems

■ VCRs

THERMAL DATA

u

= 41°C/W

JC

u

= 111°C/W

JA

ORDERING INFORMATION

SP5611 KG/MPAS (Tubes)
SP5611S KG/MPAD (Tape and reel)

1
2
3
4

SP5611

5
6
7
8

16

DRIVE OUTPUT

15

V

EE

14

RF INPUT

13

RF INPUT

12

V

CC

11

NC

10

P3 ADD SELECT PORT

9

I/O PORT P4

†

MP16

SP5611

ELECTRICAL CHARACTERISTICS

T

= 240°C to 185°C, V

AMB

These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated.

= 14·5V to 15·5V, reference frequency = 4MHz.

CC

Characteristic Pin

Supply current
Prescaler input voltage

Prescaler input impedance
Prescaler input capacitance

SDA, SCL

Input high voltage
Input low voltage
Input high current
Input low current
Leakage current

SDA

Output voltage

Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
External reference input frequency
External reference input amplitude

Output Ports

P4-P7 sink current
P4-P7 leakage current

Input Ports

P3 input current high
P3 input current low
P4, P5, P7 input voltage low
P4, P5, P7 input voltage high
P6 input current high
P6 input current low

12

13,14

13,14

13, 14

4,5
4,5
4,5
4,5
4,5

4

1
1
1

16

2
2
2
2

9-6
9-6

10

10
9,8,6
9,8,6

7
7

Value

Min. Max.

12·5

Typ.

20

27

300

50

2

3
0

5·5
1·5

10

210

10

0·4

650

6170

65

500

6400

10

200

80

70

1000

2

8

200

750

10

10

1

20·5

0·8

2·7

110
210

Units

mA

mVrms

Ω

pF

V
V

µA
µA
µA

V

µA
µA

nA

µA

Ω

mV p-p

Ω

MHz

mVrms

mA

µA

mA
mA

V
V

µA
µA

Conditions

V

= 4·5V to 5·5V (note 1)

CC

50MHz to 1·3GHz sinewave,
see Fig. 5

Input voltage = V

CC

Input voltage = 0V
When V

CC

= 0V

Sink current = 3mA

Byte 4, bit 2 = 0, pin 1 = 2V
Byte 4, bit 2 = 1, pin 1 = 2V
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 16 = 0·7V

Parallel resonant crystal (note 2)

AC coupled sinewave
AC coupled sinewave

V

= 0·7V

OUT

V

= 13·2V

OUT

V pin 10 = V

CC

V pin 10 = 0V

See Table 3 for ADC levels

NOTES

1. Maximum power consumption is 150mW with V

2. Resistance specified is maximum under all conditions.

= 5·5V and all ports off.

CC

2

ABSOLUTE MAXIMUM RATINGS

All voltages are referred to VEE and pin 3 at 0V

Parameter

Pin

Value

SP5611

Units

Max.Min.

Conditions

Supply voltage

RF input voltage

Port voltage

Total port output current

Address select voltage

RF input DC offset

Charge pump DC offset

Drive output DC offset

Crystal oscillator DC offset

SDA, SCL input voltage

Storage temperature

Junction temperature

12

13,14

6-9

6-9

6-9

10

13-14

1

16

2

4,5

20·3

20·3

20·3

20·3

20·3

20·3

20·3

20·3

20·3

20·3

255

7

2·5

14

6

50

10·3

V

CC

10·3

V

CC

VCC10·3

10·3

V

CC

10·3

V

CC

VCC10·3

6

1150

1150

V

V p-p

V

V

mA

V

V

V

V

V

V

V

°C
°C

Port in off state

Port in on state

RF IN

SCL

SDA

13

14

5

4

P3 ADD SELECT

PREAMP

TRANSCEIVER

ADDRESS

SELECT

10

PRESCALER

POWER
ON DET

POR

I2C BUS

3-BIT

ADC

4

8

LEVEL

3 TTL

COMP

15-BIT

PROGRAMMABLE

DIVIDER

15-BIT LATCH
DIVIDE RATIO

F

4-BIT LATCH

PORT INFO

F

PD

L

4

F

PHASE

COMP

COMP

F

LOCK

DET

CONTROL DATA

LATCHES

AND

CONTROL LOGIC

4

PORT OUTPUT

DRIVERS

9876

P4 P5 P6 P7

DIVIDER

4

512/1024

DN

CHARGE

PUMP

UP

CP TO OS

OSC

2

Q1

CRYSTAL

3

Q2

1

CHARGE PUMP

16

DRIVE/
VARICAP OUT

V

CC

15

V

EE

Fig. 2 Block diagram

3

SP5611

FUNCTIONAL DESCRIPTION

The SP5611 is programmed from an I2C Bus. Data and
Clock are fed in on the SDA and SCL lines respectively, as
defined by the I2C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
LSB of the address byte (R/W) sets the device into write mode
if it is low and read mode if it is high. The Tables in Fig. 3
illustrate the format of the data. The device can be pro­grammed to respond to several addresses, which enables the
use of more than one synthesiser in an I
Table 4 shows how the address is selected by applying a
voltage to P3.

When the device receives a correct address byte, it pulls
the SDA line low during the acknowledge period, and during
following acknowledge periods after further data bytes are
programmed. When the device is programmed into the read
mode, the controller accepting the data must pull the SDA line
low during all status byte acknowledge periods to read an­other status byte. If the controller fails to pull the SDA line low
during this period, the device generates an internal STOP
condition, which inhibits further reading.

WRITE Mode (Frequency Synthesis)

When the device is in write mode bytes 2 and 3 select the
synthesised frequency, while bytes 4 and 5 control the output
port states, charge pump, reference divider ratio and various
test modes.

Once the correct address is received and acknowledged,
the first bit of the next byte determines whether that byte is
interpreted as byte 2 or 4; a logic 0 for frequency information
and a logic 1 for control and output port information. When
byte 2 is received the device always expects byte 3 next.
Similarly, when byte 4 is received the device expects byte 5
next. Additional data bytes can be entered without the need
to re-address the device until an I
recognised. This allows a smooth frequency sweep for fine
tuning or AFC purposes.

If the transmission of data is stopped mid-byte (for exam­ple, by another device on the bus) then the previously pro­grammed byte is maintained.

Frequency data from bytes 2 and 3 are stored in a 15-bit
register and used to control the division ratio of the 15-bit
programmable divider. This is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input, see Fig. 5. The input impedance is shown in
Fig. 7.

The programmed frequency can be calculated by multiply­ing the programmed division ratio by 8 times the comparison
frequency F
comparator, via a charge pump and varicap drive amplifier,
adjusts the local oscillator control voltage until the output of
the programmable divider is frequency and phased locked to
the comparison frequency.

The reference frequency may be generated by an external
source capacitively coupled into pin 2, or provided by an on­chip crystal controlled oscillator. The comparison frequency
F

is derived from the reference frequency via the refer-

COMP

. When frequency data is entered, the phase

COMP

2

C Bus system.

2

C stop condition is

ence divider. The reference divider division ratio is switchable
from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a
logic 1 to 512, a logic 0 for 1024. The SP5611 differs from the
SP5511 in this respect, only 512 being available on the
SP5511. Note that the comparison frequency is 7·8125kHz
when a 4MHz reference is used, and divide by 512 is selected.

Bit 2 of byte 4 of the programming data (CP) controls the

current in the charge pump circuit, a logic 1 for ±170µA and a
logic 0 for ±50µA, allowing compensation for the variable

tuning slope of the tuner and also to enable fast channel
changes over the full band. When the device is frequency

locked, the charge pump current is internally set to ±50µA

regardless of CP.

Bit 4 of byte 4 (T0) disables the charge pump when it is set

to a logic 1.

Bit 8 of byte 4 (OS) switches the charge pump drive

amplifier’s output off when it is set to a logic 1.

Bit 3 of byte 4 (T1) enables various test modes when set
high. These modes are selected by bits 5, 6 and 7 of byte 4
(TS2, and TS1, TS0) as detailed in Table 5. When T1 is set
low, TS2 and TS1 are assigned a ‘don’t care’ condition, and
TS0 selects the reference divider ratio as previously de­scribed.

Byte 5 programs the output ports P4 to P7; a logic 0 for a
high impedance output and a logic 1 for low impedance (on).

READ Mode

When the device is in read mode the status byte read from
the device on the SDA line takes the form shown in Table 2.

Bit 1 (POR) is the power-on reset indicator and is set to a
logic 1 if the V

supply to the device has dropped below 3V

CC

(at 25˚C), for example, when the device is initially turned on.
The POR is reset to 0 when the read sequence is terminated
by a stop command. When POR is set high (at low V

CC

), the
programmed information is lost and the output ports are all set
to high impedance.

Bit 2 (FL) indicates whether the device is phase locked, a
logic 1 is present if the device is locked, and a logic 0 if the
device is unlocked.

Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports
P7, P5 and P4 respectively. A logic 0 indicates a low level and
a logic 1 a high level. If the ports are to be used as inputs they
should be programmed to a high impedance state (logic 1).
These inputs will then respond to data complying with TTL
type voltage levels.

Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of
the 5-level ADC. The ADC can be used to feed AFC informa­tion to the microprocessor from the IF section of the receiver,
as illustrated in the typical application circuit.

APPLICATION

A typical application is shown in Fig. 4. All input/output
interface circuits are shown in Fig. 6. The SP5611 is function and
pin equivalent to the SP5511 device apart from the switchable
reference divider, and has much lower power dissipation, im­proved RF sensitivity and better ESD performance.

4