MITEL SP5502FKGMPAS, SP5502SKGMPAS Datasheet
SP5502
1.3GHz I2C BUS 4-Address Synthesiser
Supersedes version in April 1994 Consumer IC Handbook, HB3120 - 2.0 DS3031 - 5.0 January 1997
The SP5502 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I2C BUS format. The SP5502 has four programmable I2C BUS
addresses, which allows two or more synthesisers to be used
in a system.
The device is available in two variants: the SP5502F in 14lead miniature plastic package (MP14) and the SP5502S in 16lead miniature plastic package (MP16). See Features below for
functional differences between the devices.
FEATURES
■ Complete 1·3GHz Single Chip System
■ Programmable via the I
■ Low Power Consumption (240mW Typ.)
■ Low Radiation
■ Phase Lock Detector
■ Varactor Drive Amp Disable
■ 5320mA Controllable Outputs (SP5502S)
■ 3320mA Controllable Outputs (SP5502F)
■ Variable I
2
C BUS Address for Multi-Tuner Applications
■ ESD Protection *
* Normal ESD handling precautions should be observed.
2
C BUS
Fig. 1 Pin connections – top view
APPLICATIONS
■ Cable Tuning Systems
■ VCRs
ORDERING INFORMATION
SP5502F KG MPAS (14-lead miniature plastic package)
SP5502S KG MPAS (16-lead miniature plastic package)
Fig. 2 Block diagram of SP5502S. (Ports P0 and P4 not present on SP5502F)
SP5502
ELECTRICAL CHARACTERISTICS
T
= 210°C to 180°C, VCC = 14·5V to 15·5V. All pin references are to the SP5502S (MP16 package).
AMB
These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature
and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated.
Characteristic Pin
Supply current
Prescaler input voltage
Prescaler input voltage
Prescaler input impedance
Prescaler input capacitance
12
13,14
13,14
Min. Max.
Typ.
48
12·5
30
50
2
60
300
300
Units
mA
mVrms
mVrms
Ω
pF
Conditions
VCC = 5V
80MHz to 1GHz
1·3GHz, see Fig. 5
SDA, SCL
Value
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
4,5
4,5
4,5
4,5
4,5
3
0
V
CC
1·5
10
210
10
V
V
µA
Input voltage = V
µA
Input voltage = 0V
µA
When VCC = 0V
CC
SDA
Output voltage
Charge pump current low
Charge pump current high
Charge pump output leakage current
Charge pump drive output current
Charge pump amplifier gain
Recommended crystal series resistance
Crystal oscillator drive level
Crystal oscillator negative resistance
16
4
1
1
650
6170
1
500
0·4
65
V
Sink current = 3mA
µA
Byte 4, bit 2 = 0, pin 1 = 2V
µA
Byte 4, bit 2 = 1, pin 1 = 2V
nA
Byte 4, bit 4 = 1, pin 1 = 2V
V pin 16 = 0·7V
6400
10
40
2
750
200
Ω
mV p-p
Ω
Parallel resonant crystal (note 2)
Output Ports
Sink current
Leakage current
6,7,9-11
6,7,9-11
20
10
mA
µA
V
= 0·7V (see note 1)
OUT
V
= 13·2V
OUT
Input Port
P3 input current high
P3 input current low
NOTES
1. Source impedance between all output ports and ground is approximately 5Ω . This should be taken into account when calculating output port
saturation voltages.
2. The maximum resistance quoted refers to all conditions, including start-up.
8
8
1
20·5
mA
mA
V pin 8 = V
V pin 8 = 0V
CC
FUNCTIONAL DESCRIPTION (Except where
otherwise indicated, ‘SP5502’ refers to both
variants)
The SP5502 is programmed from an I2C BUS. Data and
Clock are fed in on the SDA and SCL lines respectively as
defined by the I2C Bus format. The synthesiser can either
accept new data (write mode) or send data (read mode). The
Tables in Fig. 3 illustrate the format of the data. The device
can be programmed to respond to several addresses, which
enables the use of more than one synthesiser in an I2C Bus
system. Table 3 shows how the address is selected by
applying a voltage to P3. The address input is shown in Fig.
6. The LSB of the address Byte (R/W) sets the device into read
mode if it is high and write mode if it is low. When the SP5502
receives a correct address Byte it pulls the SDA line low
during the acknowledge period and during following acknowledge periods after further data Bytes are programmed. When
the SP5502 is programmed into the read mode the controlling
device accepting the data must pull down the SDA line during
the following acknowledge period to read another status Byte.
2
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 213 select the
synthesised frequency while Bytes 415 select the output port
states and charge pump information.
Once the correct address is received and acknowledged,
the first Bit of the next Byte determines whether that Byte is
interpreted as Byte 2 or 4, a logic 0 for frequency information
and a logic 1 for charge pump and output port information.
Additional data Bytes can be entered without the need to readdress the device until an I2C stop condition is recognised.
This allows a smooth frequency sweep for fine tuning or AFC
purposes.
If the transmission of data is stopped mid-byte (i.e., by
another device on the bus) then the previously programmed
byte is maintained.
Frequency data from Bytes 2 and 3 is stored in a 15-bit shift
register and is used to control the division ratio of the 15-bit
programmable divider which is preceded by a divide-by-8
prescaler and amplifier to give excellent sensitivity at the local
oscillator input; see Fig 5. The input impedance is shown in Fig
7.
The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison
frequency F
COMP
.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an onchip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 6170µA and
a logic 0 for 650µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
SP5502
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P2 and P7, a logic
1 connects F
Byte 5 programs the output ports P0-P2, P4 and P7 on the
SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2. Bit
1 (POR) is the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when the
device is initially turned on). The POR is set to 0 when the read
sequence is terminated by a stop command. The outputs are all
set to high impedance when the device is initially powered up. Bit
2 (FL) indicates whether the device is phase locked, a logic 1 is
present if the device is locked and a logic 0 if the device is
unlocked.
to P2 and F
COMP
DIV
to P7.
Address
Programmable divider
Programmable divider
Charge pump and test bits
I/O port control bits
Table 1 Write data format (MSB transmitted first)
Address
Status byte
A : Acknowledge bit
MA1, MA0 : Variable address bits (see Table 3)
CP : Charge Pump current select
T1 : Test mode selection
T0 : Charge pump disable
OS : Varactor drive Output disable Switch
P7, P4*, P2, P1, P0* : Control output port states
POR : Power On Reset indicator
FL : Phase lock detect flag
X : Don’t care
N : Not valid
MSB
1
0
2
T1
0
13
12
2
5
4
2
2
T0
X
P4*
1
14
2
0
6
7
2
2
CP
1
X
P7
1FL0N0N0
1
POR
Table 2 Read data format
MA0
MA1
0
0
1
1
Voltage input to P3
0
1
0
1
0V to 0·1V
Open circuit
0·4VCC to 0·6VCC†
0·9VCC to V
Table 3 Address selection
LSB
0
11
2
3
2
1
X
N
CC
CC
MA1
10
2
2
2
1
P2
MA1
N
MA0
9
2
1
2
1
P1
MA0
N
0
2
2
OS
P0*
1
N
8
0
Byte 1
A
Byte 2
A
Byte 3
A
Byte 4
A
Byte 5
A
Byte 1
A
Byte 2
A
NOTES
† Programmed by connecting a 15kΩ resistor between Address Select Port P3 and VCC.
Don’t care condition on SP5502F.
*
Fig. 3 Data formats
3
Loading...