MITEL SP5054KGDPAS, SP5054SKGMPAS Datasheet

2.6GHz 3-Wire BUS Controlled Synthesiser
The SP5054 is a single-chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5055, allowing the design of one tuner with either I2C bus or 3-wire bus format, depending on which device is inserted. The SP5054, when used with a satellite varactor tuner, forms a complete phase locked loop tuning system.
The comparison frequencies are obtained by the division of the output of a 4MHz crystal controlled on-chip oscillator. The phase comparator has a charge pump output with an output amplifier stage around which feedback may be applied. Only one external transistor is required for varactor line driving.
SP5054
DS3048 - 3.4 May 1996
FEATURES
Complete 2·6GHz Single Chip System
62·5kHz, 100kHz and 125kHz Step Size
Low Power Consumption (325mW Typ.)
Programming Compatible with Toshiba TD6380,
TD6381 and TD6382 *
Pin Compatible with SP5055 *
Low Radiation
Varactor Drive Amplifier Disable
Charge Pump Disable
Single Port 18/19 Bit Serial Data Entry
Four Controllable Outputs
ESD Protection †
* See notes on pin compatibility
† Normal ESD handling precautions should be observed
APPLICATIONS
Satellite TV
High IF Cable Tuning Systems
Fig. 1 Pin connections – top view
ORDERING INFORMATION
SP5054 KG DPAS (18-lead plastic package) SP5054S KG MPAS (16-lead miniature plastic package)
SP5054
ELECTRICAL CHARACTERISTICS
T
AMB
= 220°C to 180°C, VCC = 14·5V to 15·5V. Frequency standard = 4MHz. All pin connections refer to DP package. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.
Supply current Prescaler input voltage Prescaler input voltage
Prescaler input impedance Input capacitance
High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current
Clock inout hysteresis Clock rate Data set up time, t
2
Data hold time, t
3
Enable set up time, t
1
Enable hold time, t
5
Clock-to-enable time, t
4
Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain
Oscillator temperature stability Oscillator stability with supply voltage
Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance
Ports and Lock Output
Sink current Port leakage current
Varactor drive amplifier disable Charge pump disable
Typ.
Value
Conditions
Characteristic Pin
14
15,16
15,16
4,5,10 4,5,10 4,5,10
5
4,10
3 3
5 5 4
4 10 10 10
1
1
18
2
2
6-9,11
6-9
10
4
50
100
3 0
300 600 300 600 300
1
10
10
2350 2350
65
50
2
0·4
6150
6400
40
2400
80 400 400
V
CC
0·7
1 5
2250
700
2700
0·5
65
5
2 2
200
10
Units
Min. Max.
mA mVrms mVrms
pF
V
V µA µA µA µA µA
V
MHz
ns ns ns ns ns
µA nA
mV/s
mA
ppm/°C
ppm/V
mV p-p
mA
µA
µA µA
VCC = 5V 500MHz to 2·6GHz sinewave 120MHz and 500MHz, see Fig. 6
VIN = 5·5V, VCC = 5·5V VIN = 0V, VCC = 5·5V VIN = 0V, VCC = 5·5V VIN = 5·5V, VCC = 5·5V VIN = 0V, VCC = 5·5V
See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4
V pin 1 = 2·0V V pin 1 = 2·0V At collector of external transistor V pin 18 = 0·7V I pin 18 = 100µA
Parallel resonant crystal (note 1)
Nominal spread = 615%
V
OUT
= 0·7V
V
OUT
= 13·2V
VIN < 0V VIN < 0V
NOTE 1. The maximum resistance quoted refers to all conditions, including start-up.
2
SP5054
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V
Supply voltage RF input voltage Port voltage
Prescaler DC offset Loop amplifier DC offset Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature DP18 thermal resistance, chip-to-ambient
DP18 thermal resistance, chip-to-case MP16 thermal resistance, chip-to-ambient
MP16 thermal resistance, chip-to-case Power consumption at 5·5V
Parameter
Conditions
12
13,14
6-9 6-9
13-14
1,16
2
4,5,10
Max.Min.
Units
7
2·5
14
6
VCC10·3 VCC10·3 VCC10·3 VCC10·3
1150 1150
78 24
111
41
484
Value
20·3
20·3 20·3
20·3 20·3 20·3 20·3
255
V
V p-p
V V
V V V
V °C °C
°C/W °C/W
°C/W °C/W
mW
Port in off state Port in on state
With VCC applied
Pin
SP5054 SP5054S
14
15,16
6-9 6-9
15,16
1,18
2
4,5,10
Fig. 2 Typical input impedance
3
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