DS5117 Issue 2.1 October 1999
SL2035
High Performance Broadband Downconverter
Preliminary Information
Ordering Information
SL2035/IG/MP1S (Tubes)
SL2035/IG/MP1T (Tape and Reel)
Features
● Single Chip Broadband Solution
● Wide Dynamic Range RF Input
● Low Phase Noise Balanced Internal Local Oscillator
● High Frequency Range: 1 to 1·3 GHz
● ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
● Double Conversion Tuners
● Digital Terrestrial Tuners
● Data Transmit Systems
● Data Communications Systems
The SL2035 is a bipolar, broadband wide dynamic range
mixer oscillator, optimised for applications as the
downconverter in double conversion tuner systems. It also
has application in any system where a wide dynamic range
broadband frequency converter is required.
The SL2035 is a single chip containing all necessary active
circuitry and simply requires an external tuneable resonant
network for the local oscillator. The block diagram is shown
in Figure 1 and pin connections are shown in Figure 2.
In normal application the signal from the high IF output is
connected to the RFIN and RFIN inputs. The RF input
preamplifier of the device is designed for low noise figure
within the operating region and for high intermodulation
distortion intercept so offering good signal to noise plus
composite distortion spurious performance.
The preamplifier also provides gain to the mixer section
and back isolation from the local oscillator section. The
approximate model of the RF input is shown in Figure 3.
Absolute Maximum Ratings
Supply voltage, V
CC
RF differential input voltage
All I/O port DC offset
Storage temperature
Junction temperature
Package thermal resistance
Chip to ambient, θ
JA
Chip to case, θ
JC
20·3V to 17V
2·5V
20·3 to VCC 10·3V
255°C to 1150°C
1150°C
20°C/W
80°C/W
The output of the preamplifier is fed to the mixer section
which is optimised for low radiation application. In this stage
the RF signal is mixed with the local oscillator frequency,
which is generated by an on-chip oscillator. The oscillator
block uses an external tuneable network and is optimised
for low phase noise. A typical application is shown in
Figure 5. This block also contains a buffer-amplifier to
interface with an external PLL to allow for frequency
synthesis of the local oscillator.
The IF output can be loaded either differentially or singleended. It is recommended that the differential load as in
Figure 5 is applied as this gives best noise performance. If
the output is loaded single-ended the noise figure will be
degraded. The approximate model of the IF output is shown
in Figure 4.
In application care should be taken to achieve symmetric
balance to the IF outputs to maximise intermodulation
performance.
Figure 1 SL2035 block diagram
RFIN
RFIN
LO2
LO1
IF1
IF2
PRSC1