SL2030
High Performance Broadband Mixer Oscillator
Preliminary Information
DS5116 Issue 2.1 October 1999
Ordering Information
SL2030/IG/MP1S (Tubes)
SL2030/IG/MP1T (Tape and Reel)
Features
● Single Chip Broadband Solution
● Wide Dynamic Range RF Input
● Low Phase Noise Balanced Internal Local Oscillator
● Wide Frequency Range: 50 to 860 MHz
● ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
● Double Conversion Tuners
● Digital Terrestrial Tuners
● Data Transmit Systems
● Data Communications Systems
The SL2030 is a bipolar, broadband wide dynamic range
mixer oscillator, optimised for applications as an
upconverter in double conversion tuner systems. It also
has application in any system where a wide dynamic range
broadband frequency converter is required.
The SL2030 is a single chip solution containing all
necessary active circuitry and simply requires an external
tuneable resonant network for the local oscillator. The block
diagram is shown in Figure 1 and pin connections are
shown in Figure 2.
In normal application the high IF output is interfaced through
appropriate impedance matching to the high IF filter. The
RF input preamplifier of the device is designed for low noise
figure within the operating region and for high
intermodulation distortion intercept so offering good signal
to noise plus composite distortion spurious performance.
The preamplifier also provides gain to the mixer section
and back isolation from the local oscillator section. The
approximate model of the RF input is shown in Figure 3.
Absolute Maximum Ratings
Supply voltage, V
CC
RF differential input voltage
All I/O port DC offset
Storage temperature
Junction temperature
Package thermal resistance
Chip to ambient, θ
JA
Chip to case, θ
JC
20·3V to 17V
2·5V
20·3 to VCC 10·3V
255°C to 1150°C
1150°C
20°C/W
80°C/W
The output of the preamplifier is fed to the mixer section
which is optimised for low radiation application. In this stage
the RF signal is mixed with the local oscillator frequency,
which is generated by an on-chip oscillator. The oscillator
block uses an external tuneable network and is optimised
for low phase noise. A typical application is shown in
Figure 6 and the typical phase noise performance in
Figure 5. This block also contains a buffer-amplifier to
interface with an external PLL to allow for frequency
synthesis of the local oscillator.
The IF output must be loaded differentially in order to get
best intermodulation performance. The approximate model
of the IF output is shown in Figure 4.
In application care should be taken to achieve symmetric
balance to the IF outputs to maximise intermodulation
performance.
Figure 1 SL2030 block diagram
RFIN
RFIN
LO2
LO1
IF1
IF2
PRSC1