MITEL PDSP16330, PDSP16330A, PDSP16330AAOAC, PDSP16330AC, PDSP16330ACOAC Datasheet
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PDSP16330/A/B
Pythagoras Processor
Supersedes version September 1996, DS3884 - 1.3 DS3884 - 2.1 November 1998
The PDSP16330 is a high speed digital CMOS IC that
converts Cartesian data (Real and Imaginary) into Polar form
(Magnitude and Phase), at rates up to 20MHz. Cartesian
16+16 bit 2's complement or Sign-Magnitude data is
converted into 16 bit Phase format. The Magnitude output may
be scaled in amplitude by powers of 2. The Phase output
represents a full 2 x π field to eliminate phase ambiguities.
Polyimide is used as an inter-layer dielectric and as
glassivation.
The PDSP16330 is offered in three speed grades: a
basic 10MHz part (PDSP16330), a 20MHz version
(PDSP16330A) and a 25MHz version (PDSP16330). A MILSTD-883 version is also detailed in a separate datasheet.
Fig.1 Pin connections - bottom view (PGA)
AC84
1234567891011
L
K
J
H
G
F
E
D
C
B
A
PIN 1A INDEX MARK
ON TOP SURFACE
FEATURES
25MHz Cartesian to Polar Conversion
16-Bit Cartesian Inputs
16-Bit Magnitude Output
12-Bit Phase Output
2’s Complement or Sign-Magnitude Input Formats
Three-state Outputs and Independent
Data Enables Simplify System Interfacing
Magnitude Scaling Facility with Overflow Flag
Less than 400 mW Power Dissipation at 10MHz
84-pin PGA or 100 pin QFP Package or 84 LCC
APPLICATIONS
Digital Signal Processing
Digital Radio
Radar Processing
Sonar Processing
Robotics
ORDERING INFORMATION
Commercial (0°C to +70°C)
PDSP16330A CO AC (20MHZ - PGA Package)
PDSP16330B CO AC (25MHZ - PGA Package)
Industrial (-40°C to +85°C)
PDSP16330A BO AC 20MHZ - PGA Package
PDSP16330A/IG/GC1R 20MHZ - GC Package
PDSP16330B BO AC 25MHZ - PGA Package
Military (-55°C to +125°C)
PDSP16330A AO AC 20MHZ - PGA Package
PDSP16330/MC/GC1R 10MHz - GC Package
Mil 883C Screened
Fig.2 Pin connections - QFP Package
GC100
ASSOCIATED PPODUCTS
PDSP16112 16 X 12 Complex Multiplier
PDSP16116 16 X 16 Complex Multiplier
PDSP16318 Complex Accumulator
PDSP16350 I/Q Splitter and NCO
PDSP16510A Stand Alone FFT Processor
PDSP16330/A/B
2
FUNCTIONAL DESCRIPTION
The PDSP16330 converts incoming Cartesian Data
into the equivalent Polar Values. The device accepts new 16
+ 16 bit complex data every cycle, and delivers a 16 bit + 12
bit Polar equivalent after 24 clock cycles.The input data can be
in 2s’ Complement or Sign Magnitude format selected via the
FORM input. The output is in a magnitude format for both the
Magnitude output and the Phase. Phase data is zero for data
with a zero Y input and positive X, and is 400 hex for zero X
data and positive Y, is 800 hex for zero Y data and negative X,
and is C00 hex for zero X and negative Y. The LSB weighting
(bit 0) is 2 x π/4096 radians. The 16 bit Magnitude result may
be scaled by shifting one, two, or three places in the more
significant direction, effectively multiplying the Magnitude
result by 2,4 or 8 respectively. Any of these shifts can under
certain conditions cause an invalid result to be output from the
device. Under these circumstances the OVR output will
become active. The PDSP16330 has independent clock
enables and three state output controls for all ports.
FORM
This input selects the format of the X and Y input data.
A low level on FORM indlcates that the Input data is twos’
complement format (Note: input data 8000 hex is not valid in
2s’ complement mode). This input refers to the format of the
current Input data and may be changed on a per cycle basis
if desired. The level of FORM is latched at the same time as
the data to which it refers.
S1-0
These inputs select the scaling factor to be applied to
the Magnitude output. They are latched by the rising edge of
CLK and determine the scaling of the output in the cycle after
they are loaded into the device. The scale factor applied is
determined by the table. Should the scaling factor applied
cause an invalid Magnitude result to be output on the M Port,
then the OVR Flag will become active for the period that the
M Port output is invalid.
The output number range is from 0 to 2 when the
scaling factor is set at x1.
S0
0
1
0
1
Scaling Factor
x1
x2
x4
x8
S1
0
0
1
1
Fig.2 Block diagram
+
SHIFT
16
32
30
15
16
16 16
9
9
12
2
OEM
S0
S1
FORM
CEX
SIGN
15
30
SIGN X SIGN Y
X > Y
OEP
P11:0OVRM15:0
X
2
MAGNITUDE MAGNITUDE
Y
2
X2 + Y
2
ROTATE
SIGN
Y/X
CEY
/4
ARCTAN
ROM
Y15:0X15:0
π
PDSP16330/A/B
3
PIN DESCRIPTIONS
Symbol Pin Name and Description
CLK Clock: Common Clock to device Registers. Register contents change on the rising edge of clock.
Both pins must be connected.
CEX Clock Enable: Clock Enable for X Port. The clock to the X port is enabled by a low level.
CEY Clock Enable: Clock Enable for Y Port The clock to the Y port is enabled by a low level.
X15-X0 X Data Input Data presented to this input is loaded into the device by the rising edge of CLK.
X15 is the MSB
Y15-Y0 Y Data Input Data presented to this input is loaded into the device by the rising edge of CLK.
Y15 is the MSB
M15-M0 M Data Output: Magnitude data generated by the device is output on this port. Data changes on
the rising edge of CLK, M15 is the MSB. The weighting of M15 is determined by the Scale factor
selected .
P11-P0 P Data Output: Phase data generated by the device is output on this port. Data changes on the
rising edge of CLK, P11 is the MSB. The weighting of P11 is π radians.
OEM Output Enable: Output Enable for M Port. The M Port is in a high impedance state when this input
is high.
OEP Output Enable: Output Enable for P Port. The P Port is in a high impedance state when this input
is high.
FORM Format Select This input selects the format of the Cartesian Data input on the X and Y ports.
This input is latched by the rising edge of CLK, and is applied at the same time as the data to
which it refers. A low !evel indicates that two’s complement data is applied, a high indicates
Sign-Magnitude
S1-S0 Scaling Control: Control input for scaling of Magnitude Data. This input is latched by the rising
edge of CLK, and determines the scaling to be applied to the Magnitude result. The Scaling is
applied to the output data in the cycle following the cycle in which the control was latched.
OVR Overflow: Overflow flag. This signal becomes active if the scaling currently selected causes an
invalid value to be presented to the Magnitude output.
Vcc +5V supply. All Vcc pins must be connected.
GND 0V supply. All GND pins must be connected.
2's Complement
7FFF
.
.
.
0001
0000
FFFF
.
.
.
8001
Sign Magnitude
7FFF
.
.
.
0001
.
.
.
FFF
0000
8000
INPUT DATA RANGE
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