MITEL NWK933TP1N, NWK933, NWK933CG Datasheet

3.3V 10/100 Fast Ethernet Transceiver to MII

Features

● Integrated 10/100 Mbps Ethernet in a Single Chip

Solution

● Single 3.3V Power Supply

● Half Duplex and Full Duplex in both 10BASE-T

and 100BASE-TX

● Full MII for a Glueless MAC Connection

● Extended Register Set

● Integrated 10BASE-T Transceivers and Receive /

Transmit Filters

● Integrated Adaptive Equaliser and Base Line

Wander Correction (for FDDI Killer Packet)

● Full Auto-Negotiation Support for 10BASE-T and

100BASE-TX both Half and Full Duplex

● Link Status Change Interrupt

● Parallel Detection for Supporting Non Auto

Negotiation in Legacy Link Partners

● Low Dynamic Current

● Deep Sleep Low Power Mode <1mA

● Internal Power on Reset

● 64 pin 1mm thick TQFP Package

● Single Magnetics for 10BASE-T and 100BASE-TX

Operation for a Single RJ45 Connector

● Support for Flow Control 802.3 Specification

● Integrated 6 LED Driver

NWK933

NWK933

DS5029 Issue no 2.1 May 1999

Odering Information

NWK933/CG/TP1N

● Low External Component Count

● Loop-back mode for diagnostics

● Intelligent power management

(auto shutdown, auto wake)

● Low Transmit Jitter

Description

The NWK933 is a single chip 3.3V CMOS physical
layer solution from MII to the magnetics. It is designed
for 10BASE-T and 100BASE-TX Ethernet, based
on the IEEE 802.3 specifications.

The NWK933 is compatible with the Auto Negotiation
section of IEEE 802.3u and provides all the support
needed for the 802.3 Full duplex specification.

Switch or MAC

NWK933

Figure 1 System block diagram

Isolation

Magnetics

RJ45

1

NWK933

64 TX_CLK

63 TX03

62 TXD2

61 TXD1

60 TXD0

59 RX_ER

58 RXD3

55 RXD0

57 RXD2

56 RXD1

54 DVDD2

53 RX_CLK

52 DGND2

51 RX_DV

50 CRS

49 COL

SUBGND2 1

TX_ER 2

DGND1 3

TX_EN 4
LNKST 5
ACTST 6
COLST 7
DVDD1 8

RXVDD3 9

RXGND3 10

FDST 11

SPDST 12

PA4 13

RESETN 14

RXVDD2 15

RXGND2 16

PA3 17

RXIN 20

RXIP 19

ANEN 22

RXVDD1 21

RXGND1 18

Figure 2Pin connections

Functional Description

The NWK933 has three basic modes of operation:
10BASE-T, 100BASE-TX and LOW POWER modes.
The Control block is designed to manage these modes
by starting and stopping the 10M and 100M transceivers
in a well-controlled manner such that no spurious
signals are output on either the MII or twisted-pair
interfaces. Furthermore, it continuously monitors the
behaviour of the transceivers and takes corrective
action if a fault is detected.

Other modes described herein are repeater mode and
reset mode.

25MHz Reference Clock

The NWK933 requires a 25MHz +/-100ppm timing
reference for 802.3 compatible operation. This may
be supplied either from the integrated oscillator or
from an external source. When the integrated oscillator
is used, a suitable crystal must be connected across
the XTAL1 & XTAL2 pins (see “External Components”)
and REFCLK must be tied low. When an external
source is used, it must be input to the REFCLK pin
and XTAL1 must be tied low. XTAL2 must be
unconnected.

48 MINT
47 DVDD3

46 MDC
45 MDIO

44 DGND3
43 RefCLK

42 OSCVDD

41 XTAL1

40 XTAL2
39 OSCGND

38 TXGND4

37 TXVDD4
36 TXREF100
35 TXREF10
34 TXVDD3
33 TXGND3

PA0 31

PA1 30

TXOP 23

TXVDD2 24

TXGND2 25

PA2 29

TXON 28

TXVDD1 27

TXGND1 26

TP64

SUBGND1 32

10Base-T Operation

10Mb/s Data Transfer on the MII

10Mb/s data is transferred across the MII with clock
speeds of 2.5MHz. The MAC outputs data to the
NWK933 via the MII interface, on the TXD[3:0] bus.
This data is synchronised to the rising edge of TX_CLK.
To indicate that there is valid data for transmission on
the MII, the MAC sets the TX_EN signal active. This
forces the NWK933 device to take in the data on the
TXD[3:0] bus. This is serialised and directly encoded
as Manchester data, before being output on the TXOP/
TXON differential output for transmission through 1:Ö2
magnetics and onto the twisted-pair.

The transmit current is governed by the current through
the TXREF10 pin, which must be grounded through a
resistor as described in “External Components”.

RX10 Clock Recovery

The NWK933 employs a digital delay line controlled
by the 100MHz Synthesizer DLL to derive a sampling
clock from the incoming signal. The recovered clock
runs at twice the data rate (nominally 20MHz). When
a signal is received from the Signal Detect block, it is
used to strobe Link Pulses and Manchester encoded
serial data.

2

NWK933

The Manchester data stream will be decoded into a 4­bit parallel data bus, RXD[3:0]. The RXD bus is clocked
out on RX_CLK rising. The NWK933 must detect the
first 4 bits of pre-amble before RX_DV is set high.
When RX_DV is high, any Manchester coding violation
will set RX_ER high. RX_DV is reset by a continuous
sequence of zeroes, or by the end-of-packet IDLE
terminator (11 11 00 00). Whilst RX_DV is low, the
data is invalid.

100MHz Synthesizer

This synthesizer employs a delay-locked loop (DLL)
to generate a 100MHz timing reference from the 25MHz
reference clock. This 100MHz reference is used by
the 10BASE-T transmit and receive functions and is
divided by 5 to provide a 20MHz data strobe. The
20MHz clock is used to derive the 2.5 MHz TX_CLK in
10BASE-T mode. The synthesizer is disabled when
not in 10BASE-T mode.

TX10 Pulse Shaper & Filter

The Pulse Shaper & Filter employs a digital Finite
Impulse Response filter (FIR) to pre-compensate for
line distortion and to remove high frequency
components in accordance with the 802.3 Standard.
The Pulse Shaper & Filter is disabled when not in
10BASE-T mode.

TX10 Latency

When connected to appropriate magnetics the latency
through the TX10 path is less than 2BT (200ns) for
data transmissions. This timing is measured from the
rising edge of TX_CLK to the output of the transmit
magnetics. The TX10 path will not transmit up to the
first two Manchester encoded bits of a data
transmission, as permitted by the 802.3 Standard.

RX10 Filter & RX10 Signal Detect

These blocks work in unison to remove noise and to
block signals that do not achieve the voltage levels
specified in 802.3. Signals that do not achieve the
required level are not sampled in the Clock Recovery
block and are not passed to the outputs.

RX10 Latency

When connected to appropriate magnetics the latency
through the RX10 path is less than 6BT (600ns). This
timing is measured from the input of the receive
magnetics to the rising edge of RX_CLK. The RX10
path may ignore up to three Manchester encoded bits
at the start of data reception (802.3 allows up to 5
bits).

100Base-TX Operation

100Mb/s Data Exchange on the MII Interface

100Mb/s data is transferred across the MII with clock
speeds of 25MHz. The MAC outputs data to the
NWK933 via the MII interface, on the TXD[3:0] bus.
This data is synchronised to the rising edge of TX_CLK.
To indicate that there is valid data for transmission on
the MII, the MAC sets the TX_EN signal active. This
forces the NWK933 device to take in the data on the
TXD[3:0] bus and replace the first octet of the MAC
preamble with Start-of-Stream Delimiter (SSD) symbols
to indicate the start of the Physical Layer Stream.

When the data transfer across the MII is complete, the
MAC deasserts the TX_EN signal and the NWK933
adds End-of-Stream Delimiters (ESD) symbols onto
the end of the data stream. The complete data stream
(the Physical Layer Stream) is encoded from 4 bits
into 5 bits, scrambled, converted to MLT3 and driven
to the TXOP and TXON pin differentially.

The TX100 path is disabled when not in 100BASE-TX
mode and, with the exception of the RX100 Signal
Detect, the RX100 Receive Path is disabled when not in
100BASE-TX mode.

125MHz Synthesizer

This synthesizer employs a phase-locked loop (PLL) to
generate a 125MHz timing reference from the 25MHz
reference clock. This 125MHz reference is used by the
100BASE-TX transmit function and is divided by 5 to
provide a 25MHz data strobe on TX_CLK. TX_CLK is
frequency and phase locked to the 25MHz reference
with a small phase offset. The synthesizer is disabled
when not in 100BASE-TX mode.

3

NWK933

TX100 PISO, Encoder and Scrambler

Data from the MII is loaded into the TX100 PISO,
Encoder and Scrambler on the rising edge of TX_CLK.
It is converted to serial MLT3 for outputting to the
TX100 Driver. The TXD[3] bit is output first. The
PISO & Encoder do not operate until the 125MHz
Synthesizer is locked to the 25MHz reference. This
avoids transmission of spurious signals onto the
twisted-pair.

TX100 Driver

The TX100 Driver outputs the differential signal onto
the TXOP and TXON pins. It operates with 1:root 2
magnetics to provide impedance matching and
amplification of the signal in accordance with the

802.3 specifications. The transmit current is governed
by the current through the TXREF100 pin, which
must be grounded through a resistor as described in
“External Components”. The TX100 driver is disabled
in 10BASE-T mode and in loop back mode.If no data
is being transmitted from the MAC, the NWK933
outputs idle symbols of 11111 (suitably scrambled).

TX100 Latency

The transmit latency from the first TX_CLK rising
when TX_EN is high to the first bit of the “J” symbol
on the cable is 8BT.

RX100 Equalizer & Base-line Wander
Correction

RX100 Clock Recovery

The RX100 Clock Recovery circuit uses a Phase­Locked Loop (PLL) to derive a sampling clock from
the incoming signal. The recovered clock runs at the
symbol bit rate rate (nominally 125MHz) and is used
to clock the MLT3 decoder and the Serial to Parallel
converter (SIPO).

The recovered clock is divided by 5 to generate the
receive clock (RX_CLK) which is used to strobe
received data across the MII interface. When no
signal is detected in 100BASE-TX mode, the PLL is
locked to the reference clock and runs at 125MHz.
This ensures that RX_CLK runs continuously at
25MHz in 100BASE-TX mode. When a signal is
present, the Clock Recovery PLL remains locked to
the reference until the equalizer has adjusted, then it
requires up to 1ms to phase lock to the incoming
signal. No data is passed to the MII interface until
lock is established.

RX100 SIPO, Decoder and Descrambler

The RX100 SIPO, Decoder and Descrambler convert
the received signal from serial MLT3 to 4-bit wide
parallel receive data on the MII. This appears on the
RXD[3:0] bus which is clocked out on the falling edge
of RX_CLK. When a frame starts the NWK933
decodes the SSD symbols and then asserts the
RX_DV signal, in order to inform the MAC that valid
data is available. When the NWK933 detects the
ESD, it deasserts the RX_DV signal.

The RX100 Equalizer compensates for the signal
attenuation and distortion resulting from transmission
down the cable and through the isolation transformers.
The Equalizer is self-adjusting and is designed to
restore signals received from up to 10dB cable
attenuation (at 16MHz). When the Equalizer is active
it adjusts to the incoming signal within 1ms. Thereafter,
the Equalizer will continuously adjust to small
variations in signal level without corrupting the
received data.

The 100BASE-TX MLT3 code contains significant
low frequency components which are not passed
through the isolation transformers and cannot be
restored by an adaptive equalizer. This leads to a
phenomenon known as Base-line Wander which will
cause an unacceptable increase in error rate if not
corrected. The NWK933 employs a quantized
feedback technique to restore the low frequency
components and thus maintain a very low error
rate even when receiving signals such as the
“killer packet” described in the TP_PMD spec.

4

RX100 Latency

The latency from the first bit of the “J” symbol on the
cable to CRS assertion is between 11 and 15BT. The
latency from the first bit of the “T” symbol on the
cable to CRS de-assertion is between 19 and 23BT.

100Mb/s Transmit Errors

If the NWK933 detects that the TX_ER signal has
gone active whilst the TX_EN signal is active, then it
will propagate the detected error onto the cable by
transmitting the symbol “00100” . Figure 3 shows the
meaning of the different states of TX_EN and TX_ER.
TX_ER is sampled inside the NWK933 on the rising
edge of TX_CLK.

NWK933

TX_EN TX_ER TXD [3:0] Indication

0 X ignored Normal inter frame data

1 0 0000 through 1111 Normal data transmission

1 1 0000 through 1111 Transmit error propagation

Figure 3. 100Mb/s Transmit Error States

100Mb/s Receive Errors

When there is no data on the cable, the receiver will
see only the idle code of scrambled 1’s. If a non idle
symbol is detected, the receiver looks for the SSD so
that it can align the incoming message for decoding.
If any 2 non consecutive zeros are detected within 10
bits, but are not the SSD symbols a false carrier
indication is signalled to the MII by asserting RX_ER
and setting RXD[3:0] to 1110 whilst keeping RX_DV
inactive. The remainder of the message is ignored
until 10 bits of 1’s are detected.

If any data is decoded after a SSD which is neither a
valid data code nor an ESD, then an error is flagged
by setting RX_ER active whilst the RX_DV signal is
active. This also happens if 2 idle codes are detected
before a valid ESD has been received or descramble
synchronisation is lost during packet reception. The
states of RX_DV and RX_ER are summarised in
Figure 4. RX_ER is clocked on the falling edge of
RX_CLK, and will remain active for at least 1 period
of RX_CLK.

RX_DV RX_ER RXD [3:0] Indication

0 0 0000 through 1111 Normal inter frame

Initialization (RESET_N)

The NWK933 incorporates a power-on-reset circuit
for self-initialization on power-up. During initialization
the open-drain RESET_N pin is driven low and all
data outputs are disabled to prevent spurious outputs
to the twisted-pair and to the MII interface. RESET_N
will remain low until the power supply has been stable
for at least 400ns. The NWK933 will then release
RESET_N allowing the external pull-up to pull the pin
high. Device initialisation will not commence until
RESET_N is high. This allows the user to extend the
inactive period by externally holding RESET_N low.
It will not normally be necessary for the user to reset
the NWK933 because it is designed to automatically
recover from fault conditions. However, if required,
the user may initialize the device by doing a hardware
or software reset.

Reset Mode

There are two types of reset in the NWK933 - hardware
and software. The hardware reset is activated by
setting the RESET_N pin to logic 0, and holding it low
for at least 100ns. This mode causes an over-all reset
in the NWK933 - both analog and digital circuitry are
reset. Whilst RESET_N is low, the SPDST and FDST
pins are inputs, and are used to determine the speed
and duplex capability which will be advertised during
auto-neg. A low on SPDST advertises 100M capability.
A high on FDST advertises full duplex capability.

The software reset is activated by setting bit 15 in
register 0 high. This bit is a self clear bit and causes
a partial reset of the device.

Figure 5 summarises the different blocks to be reset
and which reset will affect them:

0 1 1110 False carrier indication

1 0 0000 through 1111 Normal data reception

1 1 0101 or 0110 Data reception with errors

Figure 4. 100Mb/s receive error states

CONTROLS

Initialization, mode selection and other options are
governed by the control inputs and register as
described in the following paragraphs.

Block HW Reset SW reset

management register yes yes
PCS state machine (RCV, yes yes
XMT, ANEG)
XMT scrambler yes yes
RCV scramble yes yes
control state machine yes No
analog yes No

Figure 5. Effects of Reset

Note: Holding RESET_N low will hold the device in a static,

low power state.

5

NWK933

Low-Power Mode

This function is set via the management interface.
Using MDC and MDIO, Bit 11 of register 0 is written
high to put the NWK933 into Low-Power mode. The
type of low power mode is dependant on bits 14 and
15 in register 24.

For 24[15:14] = 0:0 the 10BASE-T and 100BASE-TX
transceivers are disabled. The oscillator continues
to run. Both RX_CLK and TX_CLK are stopped, the
RXD bus is held low and TXD, TXEN, and TXER are
ignored. MDC and MDIO are still active for new
commands. This mode is intended to conserve power
when the network connection is not required and the
TXOP/TXON output is undriven. Typical current
consumption is less than 10mA.

For 24[15:14] = 0:1, everything is turned off, including
the voltage references and the oscillator. This mode
must be exited via the management interface. Typical
current consumption is 0.5mA.

For 24[15:14] = 1:0, the only function available is the
signal detect. The NWK933 will detect a signal
amplitude on the cable and activate the interrupt.
MINT can be selected as either an active low or high
interrupt. Typical current consumption is less than
10mA.

consecutive false CRS events with no good frame in
between them or if a false CRS event is longer then
480 +/- 4BT. If the NWK933 receives a good carrier
event (480 +/- 4BT) or a good idle event (idle symbols
for a period of 25000 to 30000 bit time) it will resume
frame transfer to the MII.

A false CRS event happens if, at the beginning of a
carrier event, the JK symbols are not received
correctly.

When the NWK933 is in 100M mode it will count all
false CRS events in register 27 bits 7:0. This counter
is self cleared upon read. If a disconnect event
occurs between the consecutive reads of register 27,
bit 15 in the register will set high.

Auto-Negotiation Enable (ANEN)

Auto-negotiation may be hardware disabled by setting
the ANEN pin to logic zero. During operation, auto­negotiation can be disabled by setting the ANEN pin
low or by setting bit 12 of register 0 to zero. If auto­neg is disabled, the NWK933 will lose the link, and
link will be re-established only after the NWK933
control state machine has determined the speed
using bits 13 and 8 of register 0 to determine speed
and duplex respectively.

For 24[15:14] = 1:1, the NWK933 will automatically
power down into a sleep mode if no activity is seen
on the cable for approx 2 seconds. Power up is also
automatic if activity is seen. Typical current
consumption is less than 10mA.

Loopback Mode

Diagnostic loopback may be selected at any time by
asserting setting Bit 14 in register 0. In 10BASE-T
mode transmission to the TXOP/ TXON output will
be stopped and the RX10 Clock Recovery will receive
input from the TX10 transmit path rather than from
the RXIP/RXIN inputs. In 100BASE-TX mode
transmission to the TXOP/TXON output will be stopped
and the RX100 Clock Recovery will receive input
from the TX100 transmit path.

Repeater Mode

The NWK933 can be put into Repeater Mode by
setting register 24 bit 0 high. In this mode, the CRS
will be active on receive only. In 100Mbps repeater
mode, the NWK933 is able to perform a disconnect
function from the MII. This function is enabled by bit
1 in register 24. (Note that if the device is not in
repeater mode, this bit has no effect). The NWK933
will disconnect from the MII if it receives two

MII Management Interface, MDC and MDIO

The management interface is a 2 wire serial interface
connecting a PHY to a management entity. The
management unit controls the PHY and gathers
information on the status of the PHY. It does this via
the implemented registers using MDC to clock the
data on the MDIO pin.

Link Status Change Interrupt, MINT

MINT is, by default, an active low interrupt which is
activated whenever a change in the link status occurs.
It can be changed to be active high by setting bit 13
in register 24. The interrupt will remain active until
the controller acknowledges the interrupt by writing
to register 21 (any data). Should one or more link
status changes occur between the assertion of MINT
and an ackowledge, then MINT will be deasserted
and then reasserted (deassertion time between 100ns
and 150ns). Only a single interrupt event may be
queued at any one time. Multiple status changes
between an ackowledge will generate only a single
queued interrupt.

6