MITEL NJ88C50IG, NJ88C50NPAS, NJ88C50 Datasheet

The NJ88C50 is a low power integrated circuit, designed as the heart of a fast locking PLL subsystem in a mobile radio application. It is manufactured on Mitel Semiconductor 1.4 micron double polysilicon CMOS process, which ensures that low power and low noise performance is achieved. The device contains two synthesisers, one for the generation of VHF signals up to 125MHz and a second for UHF (when used with a mulitmodulus prescaler such as the SP8713/14/15). The main synthesiser has the capability of driving a dual speed loop filter and also can perform Fractional-N interpolation. Both synthesisers use current source outputs from their phase detectors to minimise external components. Various sections may be powered down for battery economy.

FEATURES

■ 30MHz main synthesiser

■ 125MHz auxiliary synthesiser

■ Programmable output current

from phase detector - up to 10mA

■ High input sensitivity

■ Fractional-N interpolator

■ Supports up to 4 modulus prescalers

■ SSOP package

APPLICATIONS

■ NMT, AMPS, ETACS cellular

■ GSM, IS-54, RCR-27 cellular

■ DCS1800 microcellular

■ DLMR, DSRR, TETRA

■ DECT, PHP cordless telephones

NJ88C50

Dual Low Power Frequency Synthesiser

DS3805 - 1.8 July 1995

NP20

Fig.1 Pin assignment

ABSOLUTE MAXIMUM RATINGS

Storage temperature -55°C to +150°C Operating temperature -40°C to +85°C Supply voltage -0.5 to 7.0V Voltage on any pin -0.3V to (VDD + 0.3V)

ORDERING INFORMATION

NJ88C50\IG\NPAS - (Industrial temp range in SSOP

package)

Fig.2 Simplified block diagram

NJ88C50

ARCHITECTURE

Fig.2 shows a simplified block diagram of the NJ88C50, a more detailed description of each block and its function is given later in this datasheet.

The synthesiser consists of the following blocks

- 35MHz reference frequency input buffer

- 35MHz programmable reference divider

- 125MHz Auxiliary synthesiser input buffer

PIN DESCRIPTION

1 2

3 4

5 6 7 8 9 10 11 12 13 14 15 16

17 18 19 20

Name

AVDD FIM

FIMB DATA

CKIN STROBE RI FIA RSA PDA PDI GND PDP VDD RSM RSC

SCREEN MOD1 MOD2 AGND

Function

Analog supply pin (nominally 5V). Main synthesiser balanced input buffer, may be used with single ended prescaler output if Fimb is biased. Main synthesiser balanced input buffer, may be used with balanced prescaler output, or biased for single ended operation. Serial input for programming data. Serial clock input for programming bus. Program enable pin, active low. Master reference frequency input, should be a.c coupled from an accurate source. Auxiliary synthesiser frequency input, should be a.c coupled. Current setting resistor connection defining auxiliary phase detector output current. Tristate current output from auxiliary phase detector. Tristate current output from the main synthesiser's phase detector giving integral control. Digital ground supply pin. Tristate current output from the main synthesiser's phase detector giving proportional control. Digital supply pin (nominally 5V). Current setting resistor connection defining main synthesiser's phase detector output currents. Current setting resistor connection defining the compensation current for fractional-N ripple elimination in the main synthesiser's current source outputs. To be connected to ground to provide isolation of the modulus control pins from RF interference. Modulus control pin (see truth table). Modulus control pin (see truth table). Analog ground supply pin.

- 125MHz Auxiliary synthesiser programmable divider

- Auxiliary synthesiser phase detector with current source outputs

- 30MHz main synthesiser input buffer (differential inputs)

- 30MHz main synthesiser programmable divider and control logic

- Main synthesiser Fractional-N interpolation system

- Main synthesiser phase detector with dual current source outputs

It is recommended that power supply pins are well decoupled to minimise power rail born interference.

NJ88C50

FUNCTIONAL DESCRIPTION

The NJ88C50 has been designed using a modular concept, and its operation can be best summarised as these component blocks.

Reference divider

The reference divider is used to provide the reference signals needed for both the main and auxiliary synthesiser phase detectors. The divider allows for a twelve bit number to be loaded, via the serial bus, to select the required division ratio. Division ratios of 3 to 4095 can be used.

The reference divider input stage will accept a low level, AC coupled, sinewave input. It is anticipated that in most systems this will be provided by a stable reference source up to 35MHz, and so encompasses all the common TCXO (temperature controlled crystal oscillator) frequencies, such as 9.6, 12.8, 13.0, 19.44 and 26MHz.

A standby mode is supported so that the reference divider can be powered down, this is achieved using two of the serial program control bits.

To reduce the possibility of unwanted interaction between the main and auxiliary synthesisers, the charge pumps do not take current at the same time. To achieve this the output of the reference divider has a duty factor of approximately 50:50, which then allows the Q and QBAR taps to be used for the auxiliary and main synthesisers respectively. By doing this the current pulses can be taken alternatively, minimising modulation of the power supply rails as current is drawn. The reference divider consists of a 12 bit programmable divider followed by a 4 bit binary counter. This 4 bit counter gives a choice of divide by M, 2M, 4M or 8M.

A pair of programmable control bits are used to determine which of the divide by M, 2M, 4M or 8M outputs is supplied to the auxiliary synthesiser’s phase detector and a further pair of control bits are used to determine which are supplied to the main synthesiser’s phase detector.

The charge pump output current level is set by an external resistor on the RSA pin (pin 9) up to a limit of 250µA +/-10%. A pull up current pulse will indicate that the VCO frequency must be increased, whilst a pull down pulse indicates that the frequency must be decreased.

Fig.3 Auxiliary phase detector

Main Synthesiser

The main synthesiser is capable of operating at frequencies up to 30MHz. The synthesiser uses the 12 bit reference divider, shared with the auxiliary synthesiser, a 12 bit up/down N divider and a digital phase comparator with current source outputs.

The device also has a number of features which increase the design flexibility and performance of the synthesiser. These include fractional-N operation, speed up mode and support of 2, 3 and 4 modulus prescalers. A description of the

operation and advantages of each of these features is given.

Auxiliary synthesiser

The auxiliary synthesiser operates over an input frequency range from 1 to 125MHz, without the use of an external prescaler. The synthesiser consists of a 12 bit N divider and a digital phase comparator with current source outputs. The reference frequency is supplied by the shared reference divider. Current source outputs allow a passive loop filter to be used.

When the auxiliary synthesiser is not in use, a standby mode is supported so that power consumption is reduced. This is achieved using one of the serial program control bits.

The divider is programmed with a 12 bit word allowing division ratios of 3 to 4095 to be used.

The auxiliary phase detector consists of the 2 D-type phase and frequency detector shown in Figure.3 below, the high and low outputs of which drive on-chip, opposing complementary charge pumps. This type of phase detector design eliminates non linearity or deadband around the zero phase error (locked) condition.

The main N divider input buffer will accept inputs from an external prescaler, either as balanced (2 wire) ECL levels at frequencies up to 30MHz, or DC coupled to a single ended prescaler output. Single ended operation requires the other buffer input (pin 3) to be externally biased to the correct slicing voltage for the prescaler and also externally decoupled.

If the inputs are in the form of balanced ECL levels, there must not be a skew of greater than 2ns between one input changing and the second input changing. The relationship of the signals is shown below in Fig.4.

Fig.4 Maximum input skew

NJ88C50

The main N divider is programmable so that it can determine how many cycles of each division ratio the external prescaler will perform.

The total division ratio of the output from the system VCO to the synthesiser's phase detector may be expressed as NTOT and R1, R2, R3 and R4 are the available prescaler ratios and N1, N2, N3 and N4 are the corresponding number of cycles for each ratio selected, within one complete division cycle.

The divider is programmed via the serial data bus and the values needed to be programmed for each of the possible prescaler ratios are as follows:-

In 2 modulus mode (division ratios R1, R2)

NTOT = N1.R1 + N2.R2

Programmed values needed: N1 - a 12 bit value giving the number of times R1 is to be used N2 - a 8 bit value giving the number of times R2 is to be used

In 3 modulus mode (division ratios R1, R2, R3)

NTOT = N1.R1 + N2.R2 + N3.R3

Programmed values needed: N1 - a 12 bit value giving the number of times R1 is to be used N2 - a 4 bit value giving the number of times R2 is to be used N2+N3 - a 4 bit value where N3 is the number of times R3 is to be used and (N2+N3) is modulo-16 addition

If N2, N3, or N4 are set to zero this will give a full count of 16 for the corresponding modulus.

The N divider block also has a special control line from the Fractional-N logic. When required this control will cause the total division ratio to be increased from N to N+1. This is achieved by forcing a cycle which would have normally used a prescaler ratio R1 to use ratio R2 instead. R1 and R2 are chosen so that R2 equals R1+1.

Further explanation of the operation of the synthesiser when using 2, 3 or 4 modulus prescaler is given in the section on multimodulus division (page 8).

The phase detector used on the main synthesiser is similar to the type used on the auxiliary synthesiser (Figure.3). In this case, however, the detector will drive two pairs of complimentary charge pumps, one of which is intended to drive the loop integrator capacitor to provide integral control, whilst the other provides proportional control for the VCO. This system is shown in Fig 5, and has applications where fast locking of the loop is required.

In 4 modulus mode (division ratios R1, R2, R3, R4)

NTOT = N1.R1 + N2.R2 + N3.R3 + N4.R4

To facilitate the use of multimodulus prescalers the N divider is based upon a twelve bit up/down counter which functions as follows

The first value, N1, is loaded into the counter which then counts down from N1 to zero. During this time, the modulus ratio R1 is selected.

When the counter reaches zero modulus R2 is selected and the counter then counts up to the N2 value. If 2 modulus operation is chosen, the counter is then reloaded with N1 and the count is repeated.

For operation with 3 or 4 modulus devices, the counter continues to count up once it has reached the N2 value. The count continues to the N2+N3 value and during this time the R3 ratio is selected. In the 3 modulus case, when the N2+N3 value is reached the counter is then reloaded with the N1 value and the modulus ratio R1 is selected.

For 4 modulus operation the counter will continue its count up to the N2+N3+N4 value before reloading the N1 value. During this time the R4 modulus is selected.

Fig.5 Loop filter using both charge pumps

MODES OF OPERATION

Normal Mode

The synthesiser will operate in normal mode while the strobe line of the serial data bus is low. In this mode the following current levels are produced. The charge pump providing the proportional feedback term will have a normal current level designated by Iprop(0), that is set by an external bias resistor, RSM. Iprop(0) will vary when different N-divider ratios are programmed, so that it is proportional to the total division ratio. To avoid the necessity of computing the total division ratio on chip, an eight bit number representing the most significant bits of Ntot will be loaded via the serial data bus. Iprop(0) is therefore given by

Iprop(0) = CN.Ibo

where CN is the loaded eight bit number and the value Ibo is scaled from the external current setting resistor RSM where Ibo = Irsm/32. Typically Ibo = 1µA ,and therefore Iprop(0) will have a maximum value equal to 255µA.

NJ88C50

The normal value of Iprop, Iprop(0), is obtained while the strobe line of the serial programming bus is held low. In this condition, the second charge pump providing the integral feedback term is inactive.

Speed up Mode

In speed up mode the loop bandwith during switching is increased to allow faster initial frequency acquisition. This is done by using the dual phase detector outputs (PDP and PDI) connected to a standard passive loop filter as shown in fig.5. The effect of this is to increase the loop gain and hence the bandwidth while maintaining a constant phase margin

when switching between speed up mode and normal mode.

The synthesiser operates in speed up mode when the strobe line goes high loading either word A or word A2 (see programming section Page 8-Page 9) and it will stay in this mode until the strobe line goes low. In this mode the following current levels are produced. The charge pump providing the proportional feedback will increase its current from Iprop(0) to a value Iprop(1), where

Iprop(1) = 2

L+1

.Iprop(0)

where L is a two bit number loaded as part of the serial programming data. Iprop(1) will therefore be 2, 4, 8 or 16 times Iprop(0). The charge pump supplying Iprop is specified up to a value of 1mA.

Also when the strobe line goes high loading word A or word A2, the charge pump providing the integral feedback term becomes active at a current level Iint given by

Iint = K.Iprop(1)

ratio. Using fractional-N the value of N is alternated between N and N+1 in order to simulate a fractional part. For example

9000.375 would be simulated by alternating between 9000 and 9001 in the pattern

9000, 9000, 9001, 9000, 9000, 9001, 9000, 9001 (mean value of 9000.375).

On the NJ88C50 the fractional-N circuit consists of an accumulator which can be set to overflow at a value of 5 or 8 (FMOD in programming word D, see page 9). The value in the accumulator, A, is incremented once every comparison cycle of the main phase detector and every time the accumulator overflows the total division ratio of the synthesiser and prescaler is increased from N to N+1. To obtain the pattern described above N=9000 and FMOD would be set to mod8 and the incremental value, NF(programmed in word A) would be set to 3. The accumulator would then behave as shown below.

Increment Accumulator Total Division

Value Value Ratio

3 3 9000 3 6 9000 3 1 9001 3 4 9000 3 7 9000 3 2 9001 3 5 9000 3 0 9001

Varying NF allows different fractions to be obtained. If NF=1 and FMOD=8 the accumulator would overflow once in every 8 cycles giving a value of 9000.125. Similarly if NF=4 the accumulator overflows every other cycle giving 9000.5.

where K is a four bit number loaded as part of the serial programming data. Although Iint can be programmed to be 240 times greater than Iprop(0), the charge pump supplying Iint is only specified up to a value of 10mA.

For all charge pumps, a pull-up current indicates the VCO frequency should be increased while a pull-down current indicates the VCO frequency should be decreased.

For the proportional and integral charge pumps, the selected pulse current levels will remain substantially constant over the charge pumps output voltage ranges tabulated in the electric characteristics. “Substantially constant” means that the current will not have changed by more than 10% of the value measured at 2.5 volts on the output .

FRACTIONAL-N OPERATION

Conventional, non fractional-N synthesisers have a frequency resolution or step size equal to the phase detector comparison frequency. Fractional-N refers to a technique which allows finer frequency steps to be obtained.

The synthesised frequency with a conventional synthesiser is equal to N times the phase detector comparison frequency, where N is the programmable integer loop divide

For a given step size this increase in resolution means a higher comparison frequency at the phase detector, and therefore a lower overall division ratio. For example,

with a step size = 200kHz and carrier frequency = 900MHz

Non fractional-N synthesiser Comparison frequency=200kHz Division ratio=900MHz=4500

200kHz Fractional-N synthesiser (using 5ths)

Comparison frequency=1MHz Division ratio=900MHz=900

1MHz In most applications the phase noise is proportional to the

overall division ratio. Therefore fractional-N gives lower phase noise. This higher comparison frequency and lower phase noise allows circuits to be built with wider loop bandwidths while keeping the same stability. This means that phase locked loops (PLLs) can be made to either switch faster for a given phase noise or be quieter for a given switching speed, compared to conventional designs.

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