MITEL MT93L16AQ Datasheet

CMOS MT93L16

Low-Voltage Acoustic Echo Canceller

Preliminary Information

Features

• Contains two echo cancellers: 112ms acoustic echo canceller + 16ms line echo canceller

• Works with low cost voice codec. ITU-T G.711 or signed mag µ/A-Law, or linear 2’s comp

• Each port may operate in different format

• Advanced NLP design - full duplex speech with no switched loss on audio paths

• Fast re-convergence time: tracks changing echo environment quickly

• Adaptation algorithm converges even during Double-Talk

• Designed for exceptional performance in high background noise environments

• Provides protection against narrow-band signal divergence

• Howling prevention stops uncontrolled oscillation in high loop gain conditions

• Offset nulling of all PCM channels

• Serial micro-controller interface

• ST-BUS, GCI, or variable-rate SSI PCM interfaces

• User gain control provided for speaker path (-24dB to +21dB in 3dB steps)

DS5068 ISSUE3 July 1999

Ordering Information

MT93L16AQ 36 Pin QSOP

-40 °C to + 85 °C

• AGC on speaker path

• Handles up to 0 dB acoustic echo return loss and 0dB line ERL

• Transparent data transfer and mute options

• 20 MHz master clock operation

• Low power mode during PCM Bypass

• Bootloadable for future factory software upgrades

• 2.7V to 3.6V supply voltage; 5V-tolerant inputs

Applications

• Full duplex speaker-phone for digital telephone

• Echo cancellation for video conferencing

• Handsfree in automobile environment

• Full duplex speaker-phone for PC

Sin

MD1

MD2

Rout

PORT 2

µ/A-Law/

Linear

ACOUSTIC ECHO PATH

Linear/

µ/A-Law

VDD

NBSD

VSS

Offset

Null

RESET

Limiter

Adaptive

Filter

AGC

FORMAT

-24 -> +21dB

User Gain

ENA2

ADV NLP

CONTROL

UNIT

Double

Talk

Detector

ADV NLP

Limiter

ENA1

Adaptive

Filter

LAW

Figure 1 - Functional Block Diagram

Program

RAM

Program

ROM

NBSD

F0i

Linear/

µ/A-Law

Micro

Interface

Howling

Controller

Offset

Null

BCLK/C4i

µ/A-Law/

Linear

MCLK

Sout

DATA1

DATA2

PORT 1

Line ECho Path

SCLK CS Rin

MT93L16 Preliminary Information

ENA1

MD1

ENA2

MD2

Rin

Sin

MCLK

IC IC

LAW

FORMAT

RESET

NC NC

SCLK

1 2

3 4 5 6 7 8 9 10 11 12 13 14 15 16

17 18

QSOP

36 35 34

33 32

31 30

29 28 27 26 25 24 23 22 21 20 19

IC IC IC MCLK2 NC

VSS VDD2 VSS2

IC IC BCLK/ F0i Rout

Sout

VDD

NC DATA1 DATA2

C4i

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1 ENA1 SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions

depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description).

2 MD1 ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in

conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode.

3 ENA2 SSI Enable Strobe / ST-BUS & GCI Mode for Sin/Rout (Input).This pin has dual functions

depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description).

4 MD2 ST-BUS & GCI Mode for Sin/Rout (Input).When in ST-BUS or GCI operation, this pin in

conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode.

5 Rin Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data

may be in either companded or 2’s complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or STBUS timing requirements.

6 Sin Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may

be in either companded or 2’s complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI,GCI or ST-BUS timing

requirements. 7ICInternal Connection (Input): Must be tied to Vss. 8 MCLK Master Clock (Input): Nominal 20 MHz Master Clock input (may be asynchronous relative

to 8KHz frame signal.) Tie together with MCLK2 (pin 33).

9,10,11 IC Internal Connection (Input): Must be tied to Vss.

12 LAW A/µ Law Select (Input). When low, selects µ−Law companded PCM. When high, selects A-

Law companded PCM. This control is for both serial pcm ports.

13 FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects

ITU-T (G.711) PCM code. This control is for both serial pcm ports.

Preliminary Information MT93L16

Pin Description (continued)

Pin # Name Description

14 RESET Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a

low-power stand-by mode.

15, 16 NC No Connect (Output). These pins should be left un-connected.

17 SCLK Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. 18 CS Serial Port Chip Select (Input). Enables serial microport interface data transfers. Activ e lo w. 19 DATA2 Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin

is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.

20 DATA1 Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1

pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for

transmitting and receiving data. 21 NC No Connect (Output). This pin should be left un-connected. 22 VDD Positive Power Supply (Input). Nominally 3.3 volts. 23 Sout Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’s complement linear PCM format. This is the Send

Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked

out following SSI, ST-BUS, or GCI timing requirements. 24 Rout Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.

Data may be in either companded or 2’ s complement linear PCM format. This is the Receive

out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits

are clocked out following SSI, ST-BUS, or GCI timing requirements. 25 F0i Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high)

frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss. 26 BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.

In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27, 28 IC Internal Connection (Input). Tie to Vss.

29 VSS2 Digital Ground (Input): Nominally 0 volts. 30 VDD2 Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22). 31 VSS Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29). 32 NC No Connect (Output). This pin should be left un-connected. 33 MCLK2 Master Clock (Input): Nominal 20MHz master clock (tie together with MCLK, pin 8).

34,35,36

Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.

2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers

IC Internal Connection (Input). Tie to Vss.

on a shared bus).

Glossary

Double-Talk Simultaneous signals present on Rin and Sin. Near-end Single-Talk Signals only present at Sin input. Far-end Single-Talk Signals only present at Rin input. ADV NLP Advanced Non-Linear-Processor Howling Oscillation caused by feedback from acoustic and line echo paths Narrowband Any mono or dual sinusoidal signals NBSD Narrow Band Signal Detector Noise-Gating Audible switching of background noise Offset Nulling Removal of DC component Reverberation time The time duration before an echo level decays to -60dBm ERL Echo Return Loss ERLE Echo Return Loss Enhancement AGC Automatic Gain Control

MT93L16 Preliminary Information

Functional Description

The MT93L16 device contains two echo cancellers, as well as the many control functions necessary to operate the echo cancellers. One canceller is for acoustic speaker to microphone echo, and one for line echo cancellation. The MT93L16 provides clear signal transmission in both audio path directions to ensure reliable voice communication, even with low level signals. The MT93L16 does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speaker-phones. Instead, the MT93L16 provides high performance full-duplex operation similar to network echo cancellers, so that users experience clear speech and un-interrupted background signals during the conversation. This prevents subjective sound quality problems associated with “noise gating” or “noise contrasting”.

The MT93L16 uses an advanced adaptive ﬁlter algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking1. This algorithm allows continual tracking of changes in the echo path, regardless of doubletalk, as long as a reference signal is available for the echo canceller.

(1. Patent Pending)

• PCM encoder/decoder compatible with µ/ALaw ITU-T G.711, µ/A-Law Sign-Mag or linear 2’s complement coding.

• Automatic gain control on the receive speaker path.

Adaptation Speed Control

The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. Adaptation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change, and noise levels to achieve fast convergence.

Advanced Non-Linear Processor (ADV-NLP)

(2. Patent Pending)

After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The MT93L16 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods.

The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112ms) to cancel echo in an average sized ofﬁce with a reverberation time of less than 112ms. The 16ms line echo canceller is sufﬁcient to ensure a high ERLE for most line circuits.

In addition to the echo cancellers, the following functions are supported:

• Control of adaptive ﬁlter convergence speed during periods of double-talk, far end singletalk, and near-end echo path changes.

• Control of Non-Linear Processor thresholds for suppression of residual non-linear echo.

• Howling detector to identify when instability is starting to occur, and to take action to prevent oscillation.

• Narrow-Band Detector for preventing adaptive ﬁlter divergence caused by narrow-band signals

• Offset Nulling ﬁlters for removal of DC components in PCM channels.

• Limiters that introduce controlled saturation levels.

• Serial controller interface compatible with Motorola, National and Intel microcontrollers.

The MT93L16 keeps the perceived noise level constant, without the need for any variable attenuators or gain switching that causes audible “noise gating”. The noise level is constant and identical to the original background noise even when the NLP is activated.

For each audio path, the NLP can be disabled by setting the NLP- bit to 1 in the LEC or AEC control registers.

Narrow Band Signal Detector (NBSD)

(3. Patent Pending)

Single or multi-frequency tones (e.g. DTMF, or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive ﬁlter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the ﬁlter adaptation process is stopped but the echo canceller continues to cancel echo.

The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers.

Preliminary Information MT93L16

Howling Detector (HWLD)

(4. Patent Pending)

The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths.

The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register.

Offset Null Filter

To ensure robust performance of the adaptive ﬁlters at all times, any DC offset that may be present on either the Rin signal or the Sin signal, is removed by highpass ﬁlters. These ﬁlters have a corner frequency placed at 40Hz.

The offset null ﬁlters can be disabled by setting the HPF- bit to 1 in the LEC or AEC control registers.

Limiters

The AGC can be disabled by setting the AGC- bit to 1 in MC control register.

Mute Function

A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively.

Quiet code is deﬁned according to the following table.

+Zero

(quiet code)

LINEAR

16 bits

2’s

complement

0000h 80h FFh D5h

SIGN/

MAGNITUDE

µ-Law

A-Law

CCITT (G.711)

µ-Law A-Law

Table 1 - Quiet PCM Code Assignment

Bypass Control

To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs.

The Rout limiter threshold is in Rout Limiter Register 1 and 2. The Sout limiter threshold is in Sout Limiter Register. Both output limiters are always enabled.

User Gain

The user gain function provides the ability for users to adjust the audio gain in the receive path (speaker path). This gain is adjustable from -24dB to +21dB in 3dB steps. It is important to use ONLY this user gain function to adjust the speaker volume. The user gain function in the MT93L16 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes.

The gain can be accessed through Receive Gain Control Register.

AGC

The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically reduced during the following conditions:

• When clipping of the receive signal occurs.

• When initial convergence of the acoustic echo canceller detects unusually large echo return.

• When howling is detected.

A PCM bypass function is provided to allow transparent transmission of pcm data through the MT93L16. When the bypass function is active, pcm data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise integrity preserved.

When the Bypass function is selected, most internal functions are powered down to provide low power consumption.

The BYPASS control bit is located in the main control MC register.

Adaptation Enable/Disable

Adaptation control bits are located in the AEC and LEC control registers. When the ADAPT- bit is set to 1, the adaptive ﬁlter is frozen at the current state. In this state, the device continues to cancel echo with the current echo model.

When the ADAPT- bit is set to 0, the adaptive ﬁlter is continually updated. This allows the echo canceller to adapt and track changes in the echo path. This is the normal operating state.

MT93L16 Throughput Delay

In all modes, voice channels always have 2 frames of delay. In ST-BUS/GCI operation, the D and C channels have a delay of one frame.

MT93L16 Preliminary Information

Power Down / Reset

Holding the RESET pin at logic low will keep the MT93L16 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated.

The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz frames prior to writing to the device registers. During this time, the initialization routines will execute and set the MT93L16 to default operation (program execution from ROM using default register values).

PCM Data I/O

The PCM data transfer for the MT93L16 is provided through two PCM ports. One port consists of Rin and Sout pins while the second port consists of Sin and Rout pins. The data are transferred through these ports according to either ST-BUS, GCI, or SSI conventions, and the device automatically detects the correct convention. The device determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the MT93L16 will assume ST-BUS operation. When a valid GCI (active

high) frame pulse is applied to the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device will assume SSI operation. Figures 11 to 13 show timing diagrams of these 3 PCM-interface operation conventions.

ST-BUS and GCI Operation

The ST-BUS PCM interface conforms to Mitel’s STBUS standard, with an active-low frame pulse. Input data is clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bitcell, and output data bit boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface corresponds to the GCI standard commonly used in Europe, with an activehigh frame pulse. Input data is clocked in by the falling edge of the bit clock (C4i) three-quarters of the way into the bitcell, and output data bit boundaries (Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.)

Either of these interfaces (STBUS or GCI) can be used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2’s complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 2. Figures 3 to 6 illustrate the timeslot allocation for each of these four modes.

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

01 2 34

F0i (GCI)

PORT1 Rin

Sout

PORT2 Sin

Rout

outputs = High impedance

inputs = don’t care

In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can conﬁgure PORT1 and PORT2 into different modes.

7654

Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)

Preliminary Information MT93L16

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

F0i (GCI)

PORT1 Rin

01 2 34

7654

Sout

PORT2

Sin

7654

Rout

outputs = High impedance

inputs = don’t care

In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can conﬁgure PORT1 and PORT2 into different modes.

7654

Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)

C4i

start of frame (stbus & GCI)

F0i (ST-BUS)

F0i (GCI)

01 2 34

PORT1

Rin

7654

Sout

PORT2

Sin

7654

Rout

ST-BUS/GCI Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller (EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be conﬁgured in Mode 3.

7654

outputs = High impedance

inputs = don’t care

indicates that an input channel is bypassed to an output channel

7654

Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)

MT93L16 Preliminary Information

C4i

start of frame (stbus & GCI)

F0i (stbus)

F0i (GCI)

Rin PORT1

Sout

Sin PORT2

Rout

ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4.

outputs = High impedance

inputs = don’t care

76543210

Figure 6 - ST-BUS and GCI 16-Bit 2’s complement linear PCM I/O (Mode 4)

In SSI operation, the frame boundary is determined

PORT1

Rin/Sout

Enable Pins Enable Pins

MD1 ENA1 MD2 ENA2

ST-BUS/GCI Mode

Selection

PORT2

Sin/Rout

by the rising edge of the ENA1 enable strobe (see Figure 7). The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ENA1.

00Mode 1. 8 bit companded PCM I/O on

timeslot 0

01Mode 2. 8 bit companded PCM I/O on

timeslot 2.

10Mode 3. 8 bit companded PCM I/O on

timeslot 2. Includes D & C channel bypass in timeslots 0 & 1.

11Mode 4. 16 bit 2’s complement linear

PCM I/O on timeslots 0 & 1.

Table 2 - ST-BUS & GCI Mode Select

SSI Operation

The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16 bit 2’s complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next.

In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the ﬂexibility to mix 2’s complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout).

Enable Strobe Pin Designated PCM I/O Port

ENA1 Line Side Echo Path (PORT 1) ENA2 Acoustic Side Echo Path (PORT 2)

Table 3 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the MT93L16 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for µ-Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and Sign-Magnitude are selected by the FORMAT pin. See Table 4.

Preliminary Information MT93L16

BCLK

PORT1

ENA1

Rin

Sout

PORT2

ENA2

Sin

Rout

outputs = High impedance

inputs = don’t care

Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate with 16-bit enable strobes.

start of frame (SSI)

8 or 16 bits

Figure 7 - SSI Operation

Sign-Magnitude

FORMAT=0

PCM Code

µ/A-LAW

LAW = 0 or 1

+ Full Scale 1111 1111 1000 0000 1010 1010

+ Zero 1000 0000 1111 1111 1101 0101

- Zero 0000 0000 0111 1111 0101 0101

- Full Scale 0111 1111 0000 0000 0010 1010

ITU-T (G.711)

FORMAT=1

µ-LAW

LAW = 0

A-LAW

LAW =1

Table 4 - Companded PCM

Linear PCM

The 16-bit 2’s complement PCM linear coding permits a dynamic range beyond that which is speciﬁed in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16 bits 2’s complement linear code which gives a maximum signal level of +15dBm0.

Bit Clock (BCLK/C4i )

The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI (BCLK) interface.

In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to

4.096 MHz and can be discontinuous outside of the enable strobe windows deﬁned by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 13.

In ST-BUS and GCI operation, connect the system C4 (4.096MHz) clock to the C4i pin.

Master Clock (MCLK)

A nominal 20MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the 8KHz frame.

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