MITEL MT9171AN, MT9171AE, MT9172AE, MT9172AN, MT9172AP Datasheet

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ISO

-CMOS ST-BUS FA MI LY

MT9171/72

Digital Subscriber Interface Circuit

Digital Network Interface Circuit

Features

• Full duple x transm iss ion o ver a si ngle twisted pair

• Selectable 80 or 160 kbit/s line rate

• Adaptive echo c anc ellation

• Up to 3km (917 1) and 4 km (9172)

• ISDN compatible (2B+D) data format

• Transparent modem capability

• Frame synchronization and clock extraction

• MITEL ST-BUS compatible

• Low power (typically 50 mW), single 5V supply

Applications

• Digital subscriber lines

• High speed data transm iss ion ov er twi sted wires

• Digital PABX line cards and tel eph one set s

• 80 or 160 kbi t/s si ngle chip m odem

Description

ISSUE 1 May 1995

Ordering In formati on

MT9171AE 22 Pin Plastic DIP MT9172AE 22 Pin Plastic DIP MT9172AC 22 Pin Ceramic DIP MT9171A N 24 Pin SS OP MT9172A N 24 Pin SS OP MT9171AP 28 Pin PLCC MT9172AP 28 Pin PLCC

-40°C to

+85°C

a twisted wire pair. They use adaptive echocancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted.

The MT9171/72 is fabricated in Mitel’s ISO2-CMOS process.

The MT9171 (DSIC) and MT9172 (DNIC) are multifunction devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over

DSTi/Di

CDSTi/

CDi

/CLD

F0 C4/TCK

F0o/RCK

MS0 MS1

MS2

RegC

DSTo/Do

CDSTo/

CDo

Transmit Interface

Control Register

Transmit/ Clock Receive Timing & Control

Status

Receive

Interfac e

Prescrambler Scrambler

Transmit

Timi ng

Master Clock

Phase Locked

Sync Detec t

Receive

DPLL

De-

Prescrambler

Error Signal

DDVSSVBiasVRef

Figure 1 - Functional Block Diagram

Address

Echo Canceller

Echo Estimate

Descrambler

Differentially

Encoded Biphase

Transmitter

—

∑

Differenti all y

Encoded Biphase

Receive

Filter

Receiver

Transmit

Filter &

Line Driver

Bias

-1

MUX

OUT

DIS

Precan

OSC2

OSC1

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MT9171/72 Advance Information

LOUT VBias

VRef

MS2 MS1 MS0

RegC

/CLD

CDSTi/CDi

CDSTo/CDo

VSS

1 2

3 4 5

6 7 8

9 10 11

22 PIN PDIP/CERDIP

22 21 20 19 18 17 16 15 14 13 12

VDD LIN TEST LOUT DIS Precan OSC1 OSC2

/TCK

C4 F0o/RCK DSTi/Di DSTo/Do

LOUT VBias

VRef

MS2 MS1 MS0

RegC

/CLD

CDSTi/CDi

CDSTo/CDo

VSS

1 2

3 4 5

6 7 8

9 10 11 12

24 PIN SSOP

24 23 22 21 20 19 18 17 16 15 14 13

MS2 MS1

MS0

RegC

/CLD

VDD LIN TEST LOUT DIS Precan OSC1 NC OSC2

/TCK

C4 F0o/RCK DSTi/Di DSTo/Do

VBias

VRef 432

5 6 7 8 9 10 11

1213141516

CDSTi/CDi

CDSTo/CDo

28 PIN PLCC

LOUT

•

VSS

NC 1

DSTo/Do

VDD 28

DSTi/Di

LIN

/RCK F0o

TEST 26

25 24 23 22 21 20 19

NC LOUT DIS Precan OSC1 OSC2

/TCK

Figure 2 - Pin Connections

Pin Description

Pin #

22 24 28

11 2 L 22 3 V 33 4 V

4,5,64,5,65,7,8MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the

77 9 RegCRegulator Control output (Digital). A 512 kHz clock used for switch mode power

89 10F0

9 10 12 CDS Ti/

10 11 13 CDSTo/

Name Description

OUT

Bias

Ref

Line Out. Transmit Signal output (Analog). Referenced to V Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD. Internal Reference V oltage output. Connect via 0.33 µF decoupling capacitor to

Bias

various operating modes for a particular appl icati on. See Table 1 for the operating modes.

supplies. Unused in MAS/MOD mode and should be left open circuit.

/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative

pulse input for the MASTER indicating the start of the active channel times of the device. Output for the SLAVE indicating the start of the active channel times of the device. Output in MOD mode providing a pulse indicating the sta rt of the Cchannel.

Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/ s serial cont rol

CDi

& signalling input in DN mode. In MOD m ode this is a contin uous bit strea m at the bit rate selected.

Control/Data ST-BUS Out/Control/Data Out (Digi tal). A 2.048 Mbit/s serial

CDo

control & signalling out put in DN mo de. In MO D mode this is a conti nuous bit stream at the bit rate selected.

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Advance Information MT9171/72

Pin Description (continued)

Pin #

Name Description

22 24 28

11 12 14 V

Negative Power Suppl y (0V ).

12 13 15 DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/da ta out put in

DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.

13 14 16 DS Ti/Di Data ST-BUS In/Data In (D i git al). A 2.048 Mbit /s serial PCM/ dat a input in DN

mode. In MOD mode this is a continuous bit stream at the bit rate selected.

14 15 17 F0o

/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns

wide negative pulse indicating the end of the active channel times of the device to allow daisy chaining. In MOD mode provides the rece ive bit rate clock to the system.

15 16 19 C4

/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 M Hz TTL compatible

clock input for the MASTER and out put for the SLAVE in DN mode. For MOD

mode this pin provides the transmit bit rate clock to the system. 16 17 21 OSC2 Oscillator Output. CMOS Out put. 17 19 22 OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C.

Electrical Characteristics for OSC1 input requirements. 18 20 23 Precan Precanceller Di sabl e. When held to Logic ’1

precanceller is forced to V

logic ’0’, the L

to the precanceller path is enabled and functions normally . An

OUT

thus bypassing the precanceller section. Wh en

Bias

’, the internal path from L

OUT

to the

internal pulldown (50 kΩ) is provided on this pin.

8,181,6,

NC No Connecti on . Leave ope n circuit 11, 18, 20,

19 21 24 L

OUT

DIS L

Disable. When held to logic “1”, L

OUT

logic “0”, L

functions normally. An internal pulldown (50 kΩ) is provided on this

OUT

is disabled (i.e., output = V

OUT

). When

Bias

pin. 20 22 26 TEST Test Pin. Connect to V 21 23 27 L 22 24 28 V

Receive Signal input (A nalog ).

Positi ve P ower Supply (+5V) input .

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MT9171/72 Advance Information

AAAA

AAA

AAAA

AAA

AAAA

AAA

DSTi

DSTo

F0o

AAA

AAAA

Channel Time 0

Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)

DSTi

DSTo

F0o

AAA

B17B16B15B14B13B12B11B1

AAA

7B16B15B14B13B12B11B10

AAA

Channel Time 0

Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)

B27B26B25B24B23B22B21B2

Channel Time 16

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Advance Information MT9171/72

Functional Description

The MT9171/72 is a device which has been designed primarily as an interface for the Integrated Services Digital Network (ISDN). However, it may be used in practically any application that requires high speed data transmission over two wires, including smart telephone sets, workstations, data terminals and com p uters.

). The data on the line is made up of information

OUT

from the DV and CD ports. The DNIC must combine information received from both the DV and CD ports and put it onto the line. At the same time, the data received from the line must be split into the various channels and directed to the proper ports. The usable data rates are 72 and

144 kbit/s as required

for the basic rate interface in ISDN. Full duplex transmission is made possible through on board adaptive echo cancellation.

In the ISDN, the DNIC is ideal for providing the interface at the U reference point. The device supports the 2B+D channel format (two 64 kbit/s Bchannels and one 16 kbit/s D-channel) over two wires as recommended by the CCITT. The line data is converted to and from the ST-BUS format on the system side of the network to allow for easy interfacing with other components such as the Sinterface device in an NT1 arrangement, or to digital PABX components.

Smart telephone sets with data and voice capability can be easily implemented using the MT9171/72 as a line interface. The device’s high bandwidth and long loop length capability allows its use in a wide variety of sets. This can be extended to provide full data and voice capability to the private subscriber by the installation of equipment in both the home and central office or remote concentration equipment. Within the subscriber equipment the MT9171/72 would terminate the line and encode/ decode the data and voice for transmission while additional electronics could provide interfaces for a standard telephone set and any number of data ports supporting standard data rates for such things as computer communications and telemetry for remote meter reading. Digital workstations with a high degree of networking capability can be designed using the DNIC for the line interface, offering up to 160 kbit/s data transmission over existing telephone lines. The MT9171/72 could also be valuable within existing computer networks for connecting a large number of terminals to a computer or for intercomputer links. The highest data rates existing for terminal to computer links is 19.2 kbit/s over conventional analog modems. With the DNIC, this can be increased up to 160 kbit/s at a very low cost per line for terminal to computer links and in many cases this bandwidth would be sufficient for computer to computer links.

Figure 1 shows the block diagram of the MT9171/72. The DNIC provides a bidirectional interface between the DV (data/voice) port and a full duplex line operating at 80 or 160 kbit/s over a single pair of twisted wires. The DNIC has three serial ports. The DV port (DSTi/Di, DSTo/Do), the CD (control/data) port (CDSTi/CDi, CDSTo/CDo) and a line port (L

The DNIC has various modes of operation which are selected through the mode select pins MS0-2. The two major modes of operation are the MODEM (MOD) and DIGITAL NETWORK (DN) modes. MOD mode is a transparent 80 or 160 kbit/s modem. In DN mode the line carries the B and D channels formatted for the ISDN at either 80 or 160 kbit/s. In the DN mode the DV and CD ports are standard STBUS and in MOD mode they are transparent serial data streams at 80 or 160 kbit/s. Other modes include: MASTER (MAS) or SLAVE (SLV) mode, where the timebase and frame synchronization are provided externally or are extracted from the line and DUAL or SINGLE (SINGL) port modes, where both the DV and CD ports are active or where the CD port is inactive and all information is passed through the DV port. For a detailed descript ion of the modes “Operating Modes” section.

In DIGITAL NETWORK (DN) mode there are three channels transferred by the DV and CD ports. They are the B, C and D channels. The B1 and B2 channels each have a bandwidth of 64 kbit/s and are used for carrying PCM encoded voice or data. These channels are always transmitted and received through the DV port (Figures 3, 4, 5, 6). The Cchannel, having a bandwidth of 64 kbit/s, provides a means for th e s y s te m to co n tro l th e D N IC and for the DNIC to pass status information back to the system. The C-channel has a Housekeeping (HK) bit which is the only bit of the C-channel transmitted and received on the line. The 2B+D channel bits and the HK bit are double-buffered. The D-channel can be transmitted or received on the line with either an 8, 16 or 64 kbit/s bandwidth depending on the DNIC’s mode of operation. Both the HK bit and the Dchannel can be used for end-to-end signalling or low speed data transfer. In DUAL port mode the C and D channels are accessed via the CD port (Figure 7) while in SINGL port mode they are transferred through the DV port (Figures 5, 6) along with the B1 and B2 channels.

see

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MT9171/72 Advance Information

AAA

DSTi

DSTo

15.6 µsec

F0o

B2-Channel

Channel Time 3

B1-Cha nnel

Channel Time 2

C-Channel

Figure 6 - DV Port - 16 0 k bit/s (Mo des 0 ,4)

Channe l Tim e 1

D-Channel

Channel Time 0

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AAA

DSTi

DSTo

11.7 µsec

F0o

B1-Cha nnel

Channel Time 2

C-Channel

Figure 5 - DV Port - 80 kbit/s (Modes 0,4)

Channel Time 1

D-Channel

Channel Time 0

Advance Information MT9171/72

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AAA

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AAA

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AAA

In DIGITAL NETWORK (DN) mode, upon entering the DNIC from the DV and CD ports, the B-channel data, D-channel D0 (and D1 for 160 kbit/s), the HK bit of the C-channel (160kbit/s only) and a SYNC bit are combined in a serial format to be sent out on the line by the Transmit Interface (Figures 11, 12). The SYNC bit produces an alternating 1-0 pattern each frame in order for the remote end to extract the frame alignment from the line. It is possible for the remote end to lock on to a data bit pattern which simulates this alternating 1-0 pattern that is not the true SYNC. To decrease the probability of this happening the DNIC may be programmed to put the data through a prescrambler that scrambles the data according to a predetermined polynomial with respect to the SYNC bit. This greatly decreases the probability that the SYNC pattern can be reproduced by any data on the line. In order for the echo canceller to function correctly, a dedicated scrambler is used with a scrambling algorithm which is different for the SLV and MAS modes. These algorithms are calculated in such a way as to provide orthogonality between the

near and far end data streams such that the correlation between the two signals is very low.

For any two DNICs on a link, one must be in SLV mode with the other in MAS mode. The scrambled data is differentially encoded which serves to make the data on the line polarity-independent. It is then biphase encoded as shown in Figure 10. See “Line Interface” section for more details on the encoding. Before leaving the DNIC the differentially encoded biphase data is passed through a pulse-shaping bandpass transmit filter that filters out the high and low frequency components and conditions the signal for transmission on the line.

The composite transmit and receive signal is received at L

. On entering the DNIC this signal

passes through a Precanceller which is a summing amplifier and lowpass filter that partially cancels the near-end signal and provides first order antialiasing for the rec eive d signa l. Inte rnal , part ial c ancell atio n

CDSTo

CDSTi

F0o

CLD

TCK

AAA

C0C1C2C3C4C5C6C

AAA

C0C1C2C3C4C5C6C

AAA

3.9 µsec

Channel Time 0 Channel Time 16

62.5 µsec

D0D1D2D3D4D5D6D

125 µsec

Figure 7 - CD Port (Modes 2,6)

CDi

CDo

Figure 8 - CD Port (Modes 1,5)

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