MITEL MT9161BE, MT9161BN, MT9160BN, MT9161BS Datasheet

ISO

2

-CMOS

MT9160B/61B

5 Volt Multi-Featured Codec (MFC)

Advance Information

Features

• Improved idle channel noise over MT9160

• MT9161 version features a delayed framing
pulse in SSI and ST-BUS modes to facilitate
cascaded devices

• Programmable µ-Law/A-Law Codec and Filters

• Programmable ITU-T G.711/sign-magnitude
coding

• Programmable transmit, receive and side-tone
gains

• Fully differential interface to handset
transducers - including 300 ohm receiver driver

• Flexible digital interface including ST-BUS/SSI

• Serial microport or default controllerless mode

• Single 5 volt supply

• Low power operation

• ITU-T G.714 compliant

Applications

• Digital telephone sets

• Cellular radio sets

• Local area communications stations

DS5145 ISSUE 3 March 1999

Ordering Information

MT9161BE 24 Pin Plastic DIP(600 mil)
MT9160BE 24 Pin Plastic DIP(600 mil)
MT9161BS 24 Pin SOIC
MT9160BS 20 Pin SOIC
MT9161BN 24 Pin SSOP
MT9160BN 20 Pin SSOP

-40°C to +85°C

Description

The MT9160B/61B 5V Multi-featured Codec
incorporates a built-in Filter/Codec, gain control and
programmable sidetone path as well as on-chip
anti-alias filters, reference voltage and bias source.
The device supports both ITU-T and sign-magnitude
A-Law and µ-Law requirements.

Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
compatible with various industry standard
micro-controllers. The device also supports
controllerless operation utilizing the default register
conditions.

The MT9160B/61B is fabricated in Mitel's
ISO2-CMOS technology ensuring low power
consumption and high reliability.

VSSD

VDD

VSSA

VBias

VRef

Din

Dout

STB/F0i

CLOCKin

STBd/FOod

(MT9161B only)

Flexible

Digital

Interface

FILTER/CODEC GAIN

ST-BUS

Channels

PWRST

ENCODER
DECODER

Timing

C & D

IC

7dB

-7dB

Serial Microport

CS DATA1 DATA2 SCLK

Figure 1 - Functional Block Diagram

Transducer

Interface

M ­M +

HSPKR +
HSPKR -

A/µ/IRQ

79

MT9160B/61B Advance Information

MT9160BE MT9161BE/BS/BN

VBias

VRef

NC

PWRST
A/µ/IRQ

VSSD

CS
NC

SCLK
DATA1
DATA2

1
2

3
4
5

IC

6
7
8

9
10
11
12

24 PIN PDIP/SOIC/SSOP

IC

CS

1
2

3
4
5

6
7
8

9
10
11
12

24 PIN PDIP

24
23
22
21
20
19
18
17
16
15
14
13

M +
M ­VSSA
NC
HSPKR +
HSPKR ­VDD
CLOCKin
NC

F0i

STB/
Din
Dout

24
23
22
21
20
19
18
17
16
15
14
13

M +
M ­VSSA
NC
HSPKR +
HSPKR ­VDD
CLOCKin
STBd/
STB/
Din
Dout

VBias

VRef

PWRST

IC

µ/IRQ

A/

VSSD

CS

SCLK
DATA1
DATA2

MT9160BS/BN

10

1
2

3
4
5

6
7
8
9

20
19
18
17
16
15
14
13
12
11

20 PIN SOIC/SSOP

M +
M ­VSSA

HSPKR +

HSPKR ­VDD
CLOCKin
STB/F0i
Din
Dout

VBias

VRef

NC

PWRST

A/µ/IRQ

VSSD

NC

SCLK
DATA1
DATA2

Figure 2 - Pin Connections

Pin Description

Pin #
20 Pin

Pin #
24 Pin

11V

22 V

Name Description

Bias

Ref

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1 µF capacitor to V

Connect 1 µF capacitor to Vref.

SSA,

Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.9] volts. Used
internally. Connect 0.1 µF capacitor to V

Connect 1 µF capacitor to VBias.

SSA,

34PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

Resets internal state of device.

FOod

F0i

45 ICInternal Connection. Tie externally to V

for normal operation.

SSD

56A/µ/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin

governs the companding law used by the filter/Codec;µ-Law when tied to V

SSD

and
A-Law when tied to VDD. Logically OR’ed with A/µ register bit.
IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.

67V

SSD

Digital Ground. Nominally 0 volts.

78 CS Chip Select (Input). This input signal is used to select the device for microport

data transfers. Active low. CMOS level compatible.

8 10 SCLK Serial Port Synchronous Clock (Input). Data clock for microport. CMOS level

compatible.

9 11 DATA 1 Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/

National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input CMOS level compatible.

10 12 DATA 2 Serial Data Receive. In Motorola/National mode of operation, this pin is used for

data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.

11 13 D

out

Data Output. A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiv er. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.

12 14 D

80

Data Input. A digital input for 8 bit wide channel data received from the Layer 1

in

transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.

Advance Information MT9160B/61B

Pin Description (continued)

Pin #
20 Pin

Pin #
24 Pin

13 15 STB/F0i Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit

16

(MT9161B

only)

14 17 CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device

15 18 V
16 19 HSPKR- Inverting Handset Speaker (Output). Output to the handset speaker (balanced).
17 20 HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker

18 22 V
19 23 M- Inverting Microphone (Input). Inverting input to microphone amplifier from the

Name Description

timeslot used by the device for both transmit and receive data. This active high
signal has a repetition rate of 8 kHz. Standard frame pulse definitions apply in
ST-BUS mode (refer to figure 11). CMOS level compatible input.

STBd/

FOod

DD

SSA

Delayed Frame Pulse Output. In SSI mode, an 8 bit wide strobe is output after the
first strobe goes low. In ST-BUS mode, a frame pulse is output 4 channel time slots
after /F0i.

functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or
greater. Connect a 4096 kHz clock to this input when the available bit clock is 128
kHz or 256 kHz. For ST-BUS mode connect C4i to this pin. CMOS level compatible.

Positive Power Supply (Input). Nominally 5 volts.

(balanced).
Analog Ground (Input). Nominally 0 volts.

handset microphone.

20 24 M+ Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier

from the handset microphone.

3,9,

16,21

Overview

The 5V Multi-featured Codec (MFC) features
complete Analog/Digital and Digital/Analog
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.

Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51®,
Motorola SPI® and National Semiconductor
Microwire® specifications. These parameters
include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.

NC No Connect. (24 Pin Packages only). Pin 16 is NC for MT9160B.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are ITU-T
G.711 A-law or µ-Law, with true-sign/Alternate Digit
Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign-magnitude coding may
also be selected for proprietary applications.

The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160B/61B.

81

MT9160B/61B Advance Information

In the event of PWRST, the MT9160B/61B defaults
such that the side-tone path is off, all programmable
gains are set to 0dB and ITU-T µ-Law is selected.
Further, the digital port is set to SSI mode operation
at 2048 kb/s and the FDI and driver sections are
powered up. (See Microport section)

The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply
design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.

A reference voltage (V

), for the conversion

Ref

requirements of the Codec section, and a bias
voltage (V
sections, are both generated on-chip. V

), for biasing the internal analog

Bias

Bias

is also
brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1µF
capacitor must be connected from V
ground at all times. Although V

may only be used

Ref

to analog

Bias

internally, a 0.1µF capacitor must be connected from
V

to ground. The analog ground reference point

Ref

for these two capacitors must be physically the same
point. Connect a 1µF capacitor between V
V

to ensure a quiet reference voltage. To facilitate

Ref

this the V

Ref

and V

pins are situated on adjacent

Bias

Bias

and

pins.

Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.

Side-tone filter gain is controlled by the STG0-STG
control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from

-9.96 dB to +9.96 dB in 3.32 dB increments.

Companding law selection for the Filter/Codec is
provided by the A/µ companding control bit while the
coding scheme is controlled by the Smag/ITU-T
control bit. The A/µ control bit is logically OR’ed with
the A/µ pin providing access in both controller and
controllerless modes. Both A/µ and Smag/ITU-T
reside in Control Register 2 (address 04h). Table 1
illustrates these choices.

Code

+ Full Scale 1111 1111 1000 0000 1010 1010

+ Zero 1000 0000 1111 1111 1101 0101

-Zero

(quiet code)

- Full Scale 0111 1111 0000 0000 0010 1010

Sign/

Magnitude

0000 0000 0111 1111 0101 0101

ITU-T (G.711)

µ-Law A-Law

Table 1 - PCM Coding

Transducer Interfaces

2

The transmit filter is designed to meet ITU-T G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.

The receive filter is designed to meet ITU-T G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.

Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).

Transmit and receive filter gains are controlled by the
TxFG0-TxFG2 and RxFG0-RxFG2 control bits,
respectively. These are located in Gain Control

Standard handset transducer interfaces are provided
by the MT9160B/61B. These are:

• The handset microphone inputs (transmitter),
pins M+/M-. The transmit path gain path may be
adjusted to either 6.0 dB or 15.3 dB. Control of
this gain is provided by the TxINC control bit
(Gain Control register 1, address 00h).

• The handset speaker outputs (receiver), pins
HSPKR+/HSPKR-.This internally compensated
fully differential output driver is capable of driving
the load shown in Figure 3. The nominal receive
path gain may be adjusted to either 0 dB, -6 dB or

-12 dB. Control of this gain is provided by the
RxINC control bit (Gain Control register 1,
address 00h). This gain adjustment is in addition
to the programmable gain provided by the receive
filter.

The serial microport, compatible with Intel MCS-51
(mode 0), Motorola SPI (CPOL=0,CPHA=0) and
National Semiconductor Microwire specifications
provides access to all MT9160B/61B internal read
and write registers. This microport consists of a
transmit/receive data pin (DATA1), a receive data pin

82

Advance Information MT9160B/61B

Serial

PCM

D

Port

in

PCM

D

out

Decoder

2.05dB

Encoder

-2.05dB

Filter/Codec and Transducer Interface

Default Bypass

Receive

Filter Gain

0 to -7 dB

(1 dB steps)

Transmit Filter

Transmit Filter

Gain

Gain

0 to +7 dB

0 to +7 dB

(1 dB steps)

(1 dB steps)

INTERNAL TO DEVICE

-0.37 dB or 8.93 dB

-6 dB

Side-tone

-9.96 to

+9. 96 dB

(3.32 dB steps)

-11 dB

Transmit Gain

-8.05 dB or

-2.05 dB
Receiver

Driver

Default Side-tone off

Transmit

Gain

8.42 dB

HSPKR +

75Ω

HSPKR -

75Ω

M+

Transmitter

Microphone

M-

EXTERNAL TO DEVICE

Handset

Receiver

(150Ω)

Figure 3 - Audio Gain Partitioning

(DATA2), a chip select pin (CS) and a synchronous
data clock pin (SCLK). For D-channel contention
control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).

The microport dynamically senses the state of the
serial clock (SCLK) each time chip select becomes
active. The device then automatically adjusts its
internal timing and pin configuration to conform to
Intel or Motorola/National requirements. If SCLK is
high during chip select activation then Intel mode 0
timing is assumed. The DATA1 pin is defined as a
bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during chip select activation then Motorola/National
timing is assumed. Motorola processor mode
CPOL=0, CPHA=0 must be used. DATA1 is defined
as the data transmit pin while DATA2 becomes the
data receive pin. Although the dual port Motorola
controller configuration usually supports full-duplex
communication, only half-duplex communication is
possible in the MT9160B/61B. The micro must
discard non-valid data which it clocks in during a
valid write transfer to the MT9160B/61B. During a
valid read transfer from the MT9160B/61B data
simultaneously clocked out by the micro is ignored
by the MT9160B/61B.

All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figures 5 and 6 the falling edge of CS
indicates to the MT9160B/61B that a microport
transfer is about to begin. The first 8 clock cycles of
SCLK after the falling edge of CS are always used to
receive the Command/Address byte from the
microcontroller. The Command/Address byte
contains information detailing whether the second
byte transfer will be a read or a write operation and
at what address. The next 8 clock cycles are used to
transfer the data byte between the MT9160B/61B
and the microcontroller. At the end of the two-byte
transfer CS is brought high again to terminate the
session. The rising edge of CS will tri-state the
output driver of DATA1 which will remain tr i-stated as
long as CS is high.

Intel processors utilize least significant bit first
transmission while Motorola/National processors
employ most significant bit first transmission. The
MT9160B/61B microport automatically
accommodates these two schemes for normal data
bytes. However, to ensure decoding of the R/W and
address information, the Command/Address byte is
defined differently for Intel operation than it is for

83

MT9160B/61B Advance Information

Motorola/National operation. Refer to the relative

Flexible Digital Interface

timing diagrams of Figures 5 and 6.

A serial link is required to transport data between the
Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.

COMMAND/ADDRESS DATA INPUT/OUTPUT COMMAND/ADDRESS:

DATA 1
RECEIVE

DATA 1
TRANSMIT

SCLK

CS

➀ Delays due to internal processor timing which are transparent.
② The MT9160:-latches received data on the rising edge of SCLK.

➂ The falling edge of

subsequent byte is always data until terminated via

➃ A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.
➄ The COMMAND/ADDRESS byte contains:

D0D1D2D3D4D5D6D

②

➂

-outputs transmit data on the falling edge of SCLK.
CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

➄

➀

D

7

0D1D2D3D4D5D6D7

D0D1D2D3D4D5D6D

CS returning high.

1 bit - Read/
3 bits - Addressing Data
4 bits - Unused

Write

MT9160B/61B and an external digital transmission
device. The MT9160B/61B utilizes the ST-BUS
architecture defined by Mitel Semiconductor but also

7

D

7

XX A2A1A

➀

➃

➂

➃

D0D1D2D3D4D5D6D

D0D1D2D3D4D5D6D

XX

7

7

D

0

R/W

0

Figure 4 - Serial Port Relative Timing for Intel Mode 0

COMMAND/ADDRESS DATA INPUT/OUTPUT COMMAND/ADDRESS:

DATA 2
RECEIVE

DATA 1
TRANSMIT

SCLK

CS

➀ Delays due to internal processor timing which are transparent.
② The MT9160:-latches received data on the rising edge of SCLK.

➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via

➃ A new COMMAND/ADDRESS byte may be loaded only by
➄ The COMMAND/ADDRESS byte contains:

D7D6D5D4D3D2D1D

②

➂

-outputs transmit data on the falling edge of SCLK.

➄

➀

D7D6D5D4D3D2D1D

0

D7D6D5D4D3D2D1D

CS returning high.

1 bit - Read/
3 bits - Addressing Data
4 bits - Unused

Write

0

0

➃

CS cycling high then low again.

D

7

R/WX A1A

➀

➃

D7D6D5D4D3D2D1D

D7D6D5D4D3D2D1D

➂

XX

A

2

0

0

D

0

X

0

84

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

Advance Information MT9160B/61B

125 µs

F0i

DSTi,
DSTo

F0od

CHANNEL 0
D-channel

LSB first

for D-

Channel

CHANNEL 1
C-channel

CHANNEL 2
B1-channel

MSB first for C, B1- & B2-

Channels

CHANNEL 3
B2-channel

Figure 6 - ST-BUS Channel Assignment

supports a strobed data interface found on many
standard Codec devices. This interface is commonly
referred to as Simple Serial Interface (SSI). The
combination of ST-BUS and SSI provides a Flexible
Digital Interface (FDI) capable of supporting all Mitel
basic rate transmission devices as well as many
other 2B+D transceivers.

The required mode of operation is selected via the
CSL2-0 control bits (Control Register 2, address
04h). Pin definitions alter dependent upon the
operational mode selected, as described in the
following subsections as well as in the Pin
Description tables.

Quiet Code
The FDI can be made to send quiet code to the

decoder and receive filter path by setting the RxMute
bit high. Likewise, the FDI will send quiet code in the
transmit path when the TxMute bit is high. Both of
these control bits reside in Control Register 1 at
address 03h. When either of these bits are low their
respective paths function normally. The -Zero entry
of Table 1 is used for the quiet code definition.

ST-BUS Mode
The ST-BUS consists of output (DSTo) and input

(DSTi) serial data streams, in FDI these are named
Dout and Din respectively, a synchronous clock input
signal CLOCKin (C4i), and a framing pulse input
(F0i). These signals are direct connections to the
corresponding pins of Mitel basic rate devices. The
CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS
operation.

The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to separate the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i is

CHANNELS 4-31

Not Used

logic low coincident with a falling edge of C4i. R efer
to figure 11 for detailed ST-BUS timing. C4i has a
frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i is also used to
clock the MT9160B/61B internal functions (i.e.,
Filter/Codec, Digital gain and tone generation) and to
provide the channel timing requirements.

The MT9160B/61B uses only the first four channels
of the 32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 6 (ST-BUS channel
assignments). The MT9161B provides a delayed
frame pulse (F0od), 4 channels after the input frame
pulse.

The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT9160B/61B supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT9160B/61B supports microport access to this
C-Channel.

DEN - D-Channel

In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.

85

MT9160B/61B Advance Information

DEN:

When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.

When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).

D8:

When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).

When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).

16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the reference frame, during which the
microprocessor D-Channel read and write operations
are performed, then:

(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 7a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.

An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame at
the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following fr amesF0i
input, whichever occurs first. To ensure D-Channel
data integrity, microport read/write access to
Address 04 hex must occur before the following
frame pulse. See Figure 7b for timing.

8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 7c.

Cen - C-Channel

Channel 1 conveys the control/status information for
the Layer 1 transceiver. C-Channel data is
transferred MSB first on the ST-BUS by the
MT9160B/61B. The full 64 kb/s bandwidth is
available and is assigned according to which
transceiver is being used. Consult the data sheet for
the selected transceiver for its C-Channel bit
definitions and order of bit transfer.

When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high. Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.

The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).

(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 7a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.

If no new data is written to address 04 hex, the
current D-channel register contents will be
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).

86

When low, data transmission is halted and this
timeslot is tri-stated on DSTo.

B1-Channel and B2-Channel

Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.

If no valid transmit path has been selected then the
timeslot output on DSTo is tr i-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).

Advance Information MT9160B/61B

IRQ

Microport Read/Write Access

FP

DSTo/
DSTi

n-3 n-2 n-1 n n+1 n+2 n+3 n+4*

Di-bit Group
Receive
D-Channel

D0

I

D2

II

D1

No preset value

D3

D4

III

D5

* note that frame n+4 is equivalent to frame n of the next cycle.

Figure 7a - D-Channel 16 kb/s Operation

FP

C4i

C2

DSTo/
DSTi

IRQ

D0

8 kb/s operation

D1

16 kb/s operation

IV

D6

D7

Di-bit Group

Transmit

D-Channel

tif=500 nsec max

Microport Read/Write Access

D0

I

D1

D2

II

D3

D4

III

D5

D6

IV

D7

Power-up reset to 1111 1111

tir=500 nsec max

= 10 k

R

pullup

Reset coincident with

Read/Write of Address 04 Hex

or next

FP, whichever occurs first

IRQ

FP

Di-bit Group
Receive
D-Channel

Figure 7b - IRQ Timing Diagram

n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1

IID1IIID2IV

I

D0

No preset value

D3

V

D4

VID5VIID6VIII

D7

Di-bit Group

Transmit

D-Channel

Figure 7c - D-Channel 8 kb/s Operation

Microport Read/Write Access

I

D0

n+2

IID1IIID2IV

n+3

n+4

D3

Power-up reset to 1111 1111

n+5

VID5VIID6VIII

V

D4

n+6

n+7

n+8

D-Channel

D7

87