MITEL MT9160AE, MT9160AS Datasheet

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ISO

-CMOS

MT9160



5 Volt Multi-Featured Codec (MFC)

Preliminary Information

Features

• Programmable µ-Law/A-Law C ode c and Fi lters

• Program mable CCITT (G .711)/sign-magni tude coding

• Program mab le trans mit , receiv e and si de-t one gains

• Fully di fferential in terfac e to han dse t transduce rs - inc luding 3 00 o hm rece iver dri ver

• Flexibl e digit al inter face i ncluding ST-BUS/SSI

• Serial mi croport or def ault co ntrol lerle ss mode

• Singl e 5 volt s upply

• Low pow er opera tio n

• CCITT G.714 com p li an t

Applications

• Digita l telep hone s ets

• Cel lu lar rad io set s

• Local area com m unications stations

•Pair Gain Systems

• Line ca rds

ISSUE 3 May 1995

Ordering Information

MT9160AE 24 Pin Plastic D IP MT9160AS 20 Pin SOIC

-40°C to +85°C

Descript io n

The MT9160 5V Multi-featured Codec incorporates a built-in Filter/Codec, gain control and programmable sidetone path as well as on-chip anti-alias filters, reference voltage and bias source. The device supports both A-Law and µ-Law requirements.

Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible with various industry standard micro-controllers. The device also supports controllerless operation utilizing the default register conditions.

The MT9160 is fabricated in Mitel's ISO technology ensuring low power consumption and high reliability.

-CMOS

STB/F0i

CLOCKin

VSSD

VDD

VSSA

VBias

VRef

Dout

Din

Flexible

Digital

Interface

FILTER/CODEC GAIN

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ENCODER

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DECODER

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7dB

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-7dB

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Timing

ST-BUS

C & D

Channels

Serial Microport

PWRST

CS DA T A1 DATA2 SCLK

Figure 1 - Functional Block Diagram

Transducer

Interface

M M +

HSPKR + HSPKR -

A/µ/IRQ

7-77

MT9160 Preliminary Information

20 PIN SOIC

24 PIN PDIP

Pin Description

1 2

3 4 5 6 7 8 9

10 11

1 2 3 4 5

6 7 8

9 10 11 12

20 19 18 17 16 15 14 13 12

24 23 22 21 20 19 18 17 16 15 14 13

VBias

VRef

PWRST A/µ/IRQ

VSSD

SCLK DATA1 DATA2

VBias

VRef

PWRST

A/µ/IRQ

VSSD

SCLK DATA1 DATA2

Figure 2 - Pin Connections

M + M VSSA HSPKR + HSPKR VDD CLOCKin STB/F0i Din Dout

M + M VSSA NC HSPKR + HSPKR VDD CLOCKin NC STB/F0i Din Dout

Pin #

SOIC DIP

11V

22 V

3 4 PWRST 45 ICInternal Conne ction. Tie externally to V 56A/µ

Name Description

Bias

Ref

Bias Voltage (Output). (VDD/2) volts is available at this pin for biasing external amplifiers. Connect 0.1 µF capacitor to V

SSA

Reference Voltage for Codec (Output). Nominally [(VDD/2)-1.5] volts. Used internally. Connect 0.1 µF capacitor to V

SSA

Power-up Reset (Input). CMOS comp atib le input with Schmitt Trigger (active low).

for normal operation.

/IRQ A/µ - When internal control bit DEn = 0 this CMOS level compatible input pin governs

the companding law used by the filter/Code c; µ -Law when tie d to V when tied to V IRQ

- When internal control bit DEn = 1 this pin becomes an open-drain inter rupt

. Logically OR’ed with A/µ register bit .

and A-Law

output signalling valid access to the D-Channel registers in ST-BUS mode.

67V

SSD

78 CS

Digital Groun d. Nomi nally 0 volts. Chip Select (Input). This input signal is used to select the device for microport data

transfers. Active low. TTL level compatible.

810SCLKSerial Port Synch ro nou s Clo ck (In put). Data clock for microport. TTL level

compatible.

911DATA 1Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/

National mode of operation, this pin becomes the dat a transmit pin only and data receive is performed on the DATA 2 pin. Input TTL level compatible.

10 12 DATA 2 Serial Data Receive. In Motorola/Nat ional mode of operati on, this pin is used for

data receive. In Intel mode, serial data transmit and receive are performed on the DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.

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Preliminary Information MT9160

Pin Description (continued)

Pin #

SOIC DIP

11 13 D

Name Description

out

Data Output. A high impedance three-state digital output for 8 bit wide channel data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with the rising edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing.

12 14 D

Data Input. A digital input for 8 bit wide channel data received from the Layer 1

transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatibl e.

13 15 STB/F0i

Data Strobe/Frame Pulse (Input). For SSI mode this input determine s the 8 bit timeslot used by the device for both transmit and receive data. This active high signal has a repetition rate of 8 kHz. Standard frame pulse defini tions ap ply in ST-BUS mode (refer to Figure 11). CMOS level compatible input.

14 17 CLOCKin Clock (Input). (CM OS level compatib le). Th e clock provided to this input pin is used

for the internal device functions. For SSI mode connect the bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit

15 18 V

clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i Positive Po wer Supply (Inp ut). Nominally 5 volt s .

to this pin.

16 19 HSPKR- Invertin g Hand set Speaker (Outpu t). Output to the handset speaker (balanced). 17 20 HSPKR+ N on-I nver tin g Hand set Speaker (Output). Output to the handse t speaker

(balanced).

18 22 V

SSA

Analog Gr ou nd (In pu t). Nominally 0 volts.

19 23 M- Invertin g Micro ph on e (Inp ut). Inverting input to microp hone am plif ier from the

handset microphone.

20 24 M+ Non-Inverting Micro ph one (Input). Non-invert ing input to microphone am plif ier

from the handset microphone.

3,9,

NC No Connect. (DIP Package only).

16,21

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MT9160 Preliminary Information

Overview

The 5V Multi-featured Codec (MFC) features complete Analog/Digital and Digital/Analog conversion of audio signals (Filter/Codec) and an analog interface to a standard handset transmitter and receiver (Transducer Interface). The receiver amplifier is capable of driving a 300 ohm load.

Each of the programmable parameters within the functional blocks is accessed through a serial microcontroller port compatible with Intel MCS-51 Motorola SPI Microwire

and National Semiconductor

specifications. These parameters

include: gain control, power down, mute, B-Channel select (ST-BUS mode), C&D channel control/access, law control, digital interface programming and loopback. Optionally the device may be used in a controllerless mode utilizing the power-on default settings.

Functional Description

Filter/Codec

design. This fully differential architecture is continued into the Transducer Interface section to provide full chip realization of these capabilities for the handset functions.

A reference voltage (V

), for the conversion

Ref

requirements of the Codec section, and a bias voltage (V

), for biasing the internal analog

Bias

sections, are both generated on-chip. V brought to an external pin so that it may be used for biasing external gain setting amplifiers. A 0.1µF capacitor must be connected from V

ground at all times. Likewise, although V

Bias

be used internally, a 0.1µF capacitor from the V pin to ground is required at all times. The analog ground reference point for these two capacitors must be physically the same point. To facilitate this the V

Ref

and V

pins are situated on adjacent pins.

Bias

The transmit filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0 dB). Gain control allows the output signal to be increased up to 7 dB. An anti-aliasing filter is included. This is a second order lowpass implementation with a corner frequency at 25 kHz.

is also

Bias

to analog

may only

Ref

The Filter/Codec block implements conversion of the analog 0-3.3 kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are programmable. These are CCITT G.711 A-law or µ-Law, with true-sign/ Alte rnate Digit Inversion or true-sign/Inverted Magnitude coding, respectively. Optionally, sign- magnitude coding may also be selected for proprietary applications.

The Filter/Codec block also implements transmit and receive audio path gains in the analog domain. A programmable gain, voice side-tone path is also included to provide proportional transmit speech feedback to the handset receiver. This side tone path feature is disabled by default. Figure 3 depicts the nominal half-channel and side-tone gains for the MT9160.

In the event of PWRST

, the MT9160 defaults such that the side-tone path is off, all programmable gains are set to 0dB and CCITT µ-Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up. (See Microport section.)

The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 5 volt supply

The receive filter is designed to meet CCITT G.714 specifications. The nominal gain for this filter is 0 dB (gain control = 0dB). Gain control allows t he output signal to be attenuated up to 7 dB. Filter response is peaked to compensate for the sinx/x attenuation caused by the 8 kHz sampling rate.

Side-tone is derived from the input of the Tx filter and is not subject to the gain control of the Tx filter section. Side-tone is summed into the receive handset transducer driver path after the Rx filter gain control section so that Rx gain adjustment will not affect side-tone levels. The side-tone path may be enabled/disabled with the gain control bits located in Gain Control Register 2 (address 01h).

Transmit and receive filter gains are controlled by the TxFG

-TxFG2 and RxFG0-RxFG2 control bits,

respectively. These are located in Gain Control Register 1 (address 00h). Transmit filter gain is adjustable from 0 dB to +7 dB and receive filter gain from 0dB to -7 dB, both in 1 dB increments.

Side-tone filter gain is controlled by the STG

-STG

control bits located in Gain Control Register 2 (address 01h). Side-tone gain is adjustable from

-9.96 dB to +9.96 dB i n 3 .3 2 dB in c r em en ts .

Intel® and MCS-51® are registered trademarks of Intel Corporation Motorola® and SPI® are registered trademarks of Motorola Corporation National® and Microwire® are trademarks of National Semiconductor Corporation

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Preliminary Information MT9160

Companding law selection for the Filter/Codec is provided by the A/µ

companding control bit while the coding scheme is controlled by the Smag/CCITT control bit. The A/µ control bit is logically OR’ed with the A/µ controllerless modes. Both A/µ

pin providing access in both controller and

and Smag/CCITT reside in Control Register 2 (address 04h). Table 1 illustrates th es e ch o ice s.

Code

+ Full Scale 1111 1111 1000 0000 1010 1010

+ Zero 1000 0000 1111 1111 1101 0101

-Zero

(quiet code)

- Full Scale 0111 1111 0000 0000 0010 1010

Sign/

Magnitude

0000 0000 0111 1111 0101 0101

CCITT (G.7 11)

µ-Law A-Law

Ta ble 1

Transducer Interfaces

Standard handset transducer interfaces are provided by the MT9160. These are:

Control of this gain is provided by the TxINC control bit (G ain Co ntrol reg iste r 1, add ress 0 0h).

• The handset speaker outputs (receiver), pins HSPKR+/HSPKR-.This internally compensated fully differ ential outp ut driver is ca pab le of d rivi ng the load sh own in Figu re 4. Th e nominal handse t receive path gain may be adjusted to either 0 dB,

-6 dB or -12 d B. Control of this gai n is provided by the Rx INC contro l bit (Gain C ontrol re gister 1, address 00h ). This gain adj ustment is in addition to the programmable gain provided by the receive filter.

HSPKR +

75 Ω

150 ohm

MT9160

75 Ω

load

(speaker)

• The handset microphone inputs (transmitter), pins M+/M-. The nominal transmit amplifier gain may be adjusted to either 6.0 dB or 15.3 dB.

Serial Port

PCM

Filter/Codec and Transducer Interface

Receive

Filter Gain

0 to -7 dB

(1 dB steps)

-6 dB

Side-tone

-9.96 to

+9. 96 dB

(3.32 dB steps)

-11 dB

Default Bypass

HSPKR -

Figure 4 - Handset Speaker Driver

HSPKR +

75Ω

HSPKR -

75Ω

Default Side-tone off

-6.0 dB or 0 dB

Receiver

Driver

Handset

Receiver

(150Ω)

PCM

out

Transmit Filter

Transmit Fil te r

Gain

0 to +7 dB

(1 dB steps)

Transmit Gain

-0.37 dB or 8.93 dB

INTERNAL TO DEVICE

Transmit

Gain

6.37 dB

Figure 3 - Audio Gain Partitioning

M+

Transmitter

Micropho ne

M-

EXTERNAL TO DEVICE

7-81

MT9160 Preliminary Information

Microport

The serial microport, compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0,CPHA=0) and National Semiconductor Microwire specifications provides access to all MT9160 internal read and write registers. This microport consists of a transmit/ receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS data clock pin (SCLK). For D-channel contention control, in ST-BUS mode, this interface provides an open-drain interrupt output (IRQ

The microport dynamically senses the state of the serial clock (SCLK) each time chip select becomes active. The device then automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. If SCLK is high during chip select activation then Intel mode 0 timing is assumed. The DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during chip select activation then Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual port Motorola controller configuration usually supports full-duplex communication, only half-duplex communication is possible in the MT9160. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT9160. During a valid read transfer from the MT9160 data simultaneously clocked out by the micro is ignored by the MT9160.

All data transfers through the microport are two-byte transfers requiring the transmission of a Command/ Address byte followed by the data byte written or read from the addressed register. CS asserted fo r th e duration of this t wo - by te t ra n sfer. As shown in Figures 5 and 6 the falling edge of CS indicates to the MT9160 tha t a microport tran sfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the MT9160 and the microcontroller. At the end of the two-byte transfer CS to terminate the session. The rising edge of CS tri-state the output driver of DATA1 which will remain tri-stated as long as CS

Intel processors utilize least significant bit first transmission while Motorola/National processors employ most significant bit first transmission. The MT9160 microport automatically accommodates

are always used to receive the

is high.

) and a synchronous

must remain

is brought high again

will

these two schemes for normal data bytes. However, to ensure decoding of the R/W information, the Command/Address byte is defined differently for Intel operation than it is for Motorola/ National operation. Refer to the relative timing diagrams of Figures 5 and 6.

Receive data is sampled on the rising edge of SCLK while transmit data is made available concurrent with the falling edge of SCLK.

Flexible Di gital Interf ace

A serial link is required to transport data between the MT9160 and an external digital transmission device. The MT9160 utilizes the ST-BUS architecture defined by Mitel Semiconductor but also supports a strobed data interface found on many standard Codec devices. This interface is commonly referred to as Synchronous Serial Interface (SSI). The combination of ST-BUS and SSI provides a Flexible Digital Interface (FDI) capable of supporting all Mitel basic rate transmission devices as well as many other 2B+D transceivers.

The required mode of operation is selected via the CSL2-0 control bits (Control Register 2, address 04h). Pin definitions alter dependent upon the operational mode selected, as described in the following subsections as well as in the Pin Description tables.

Quiet Code

The FDI can be made to send quiet code to the decoder and receive filter path by setting the RxMute bit high. Likewise, the FDI will send quiet code in the transmit path when the TxMute bit is high. Both of these control bits reside in Control Register 1 at address 03h. When either of these bits are low their respective paths function normally. The -Zero entry of Table 1 is used for the quiet code definition.

ST-BUS Mode

The ST-BUS consists of output (DSTo) and input (DSTi) serial data streams, in FDI these are named Dout and Din respectively, a synchronous clock input signal CLOCKin (C4i (F0i

). These signals are direct connections to the corresponding pins of Mitel basic rate devices. The CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS operation.

), and a framing pulse input

and address

7-82

Preliminary Information MT9160

The data streams operate at 2048 kb/s and are Time Division Multiplexed into 32 identical channels of 64 kb/s bandwidth. A frame pulse (a 244 nSec low going pulse) is used to parse the continuous serial data streams into the 32 channel TDM frames. Each frame has a 125 µSecond period translating into an 8 kHz frame rate. A valid frame begins when F0i

COMMAND/ADDRESS DATA INPUT/OUTPUT COMMAND/ADDRESS:

DATA 1 RECEIVE

DATA 1 TRANSMIT

SCLK

➀ Delays due to internal processor timing which are transparent. ② Th e MT9160:-latches received data on the rising edge of SCLK.

➂ The falling edge of CS

subsequent byte is always data until terminated via CS

➃ A new COMMAND/ADDRESS byte may be loaded only by CS ➄ The COMMAND/ADDRESS b yte contains:

D0D1D2D3D4D5D6D

②

➂

-outputs transmit data on the falling edge of SCLK. indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

➄

➀

D0D1D2D3D4D5D6D

1 bit - Read/Write 3 bits - Addressing Data 4 bits - Unused

returning high.

logic low coincident with a falling edge of C4i to Figure 11 for detailed ST-BUS timing. C4i frequency (4096 kHz) which is twice the data rate. This clock is used to sample the data at the 3/4 bit-cell position on DSTi and to make data available on DSTo at the start of the bit-cell. C4i

is also used to

clock the MT9160 internal functions (i.e., Filter/

➃

D0D1D2D3D4D5D6D

➃

➂

cycling high then low again.

XX A2A1A0R/W

➀

. Refer

has a

Figure 5 - Serial Port Relative Timing for Intel Mode 0

COMMAND/ADDRESS DATA INPUT/OUTPUT COMMAND/ADDRESS:

DATA 2 RECEIVE

DATA 1 TRANSMIT

SCLK

➀Delays due to internal processor timing which are transparent .

② The MT9160:-latches received data on the rising edge of SCLK.

➂ The falling edge of CS

subsequent byte is always data until terminated via CS

➃ A new COMMAND/ADDRESS byte may be loaded only by CS ➄ The COMMAND/ADDRESS byte contains:

D7D6D5D4D3D2D1D

②

➂

-outputs transmit data on the falling edge of SCLK. indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

➄

➀

D7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D

returning high.

1 bit - Read/Write 3 bits - Addressing Data 4 bits - Unused

➃

cycling high then low again.

R/W XA

➀

➂

➃

Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

7-83

MT9160 Preliminary Information

125 µ s

F0i

DSTi, DST o

CHANNEL 0 D-channel

LSB first

for D-

Channel

CHANNEL 1 C-channel

CHANNEL 2 B1-channel

MSB first for C, B1- & B2-

Channels

CHANNEL 3 B2-channel

Figure 7 - ST-BUS Channel Assignment

Codec, Digital gain and tone generation) and to provide the channel timing requirements.

The MT9160 uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 7 (ST-BUS channel assignments).

The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (Control Register 2, address 04h). ISDN basic rate service (2B+D) defines a 16 kb/s signalling (D) Channel. The MT9160 supports transparent access to this signalling channel. ST-BUS basic rate transmission devices, which may not employ a microport, provide access to their internal control/status registers through the ST-BUS Control (C) Channel. The MT9160 supports microport access to this C-Channel.

DEN - D-Channe l

In ST-BUS mode ac cess to the D -Channel ( transmit and receive) data is provided through an 8-bit read/ write register (address 06h). D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame for 16 kb/s operation (1 bit/ frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the microport, valid access to this register is controlled through the use of an interrupt (IRQ

) output. D-Channel access is

enabled via the (DEn) bit.

DEn:

When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/ out of the D-channel (READ/WRITE) register.

CHANNELS 4-31

Not Used

D8:

When 1, D-Channel data is shifted at the rate of 1 bit/ frame (8 kb/s).

When 0, D-Channel data is shifted at the rate of 2 bits/frame ( 1 6 kb/s default).

16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of D-Channel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame, during which the microprocessor D-Channel read and write operations are performed, then:

(a) A microport read of address 04 hex will result in a byte of data being extracted which is composed of four di-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 8a: di-bit I is mapped from frame n-3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from frame n.

The D-Channel read register is not preset to any particular value on power-up (PWRST

) or software

reset (RST).

(b) A microport write to Address 04 he x will result in a byte of data being loaded which is composed of four di-bits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig. 8a: di-bit I is mapped to frame n+1, di-bit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame n+4.

When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel timeslot and IRQ

outputs are tri-stated

(default).

7-84

If no new data is written to address 04 hex , the current D-channel register contents will be continuously re-transmitted. The D-Channel write register is preset to all ones on power-up (PWRST or softwa re r es e t ( RS T).

)

Preliminary Information MT9160

IRQ

Micropo rt Rea d/Wri te A c cess

DSTo/ DSTi

n-3 n-2 n-1 n n+1 n+2 n+3 n+4*

Di-bit Group Receive D-Channel

D0 D1

No preset value

D2 D3

III

* note that fram e n+4 is equ ival en t to frame n of the next cycle.

Figure 8a - D-Channel 16 kb/s Operation

C4i

DSTo/ DSTi

IRQ

8 kb/s operation

16 kb/s operation

Di-bit Group

Transmit

D-Channel

D0 D1ID2

Power-up reset to 1111 1111

=500 nsec max

Microport Read/Write Access

III

D6 D7

=500 nsec max

pullup

Reset coincident with

Read/Write of Address 04 Hex

or next FP

, whichever occurs first

= 10 k

IRQ

Di-bit Group Receive D-Channel

Figure 8b - IRQ

n-7 n-6 n-5 n-4 n-3 n-2 n-1 n n+1

IID1IIID2IVD3VD4VID5VIID6VIII

No preset value

Di-bit Group

Transmit

D-Channel

Timing Diagram

Figure 8c - D-Channel 8 kb/s Operation

Microport Read/Write Access

n+2

IID1IIID2IV

n+3

n+4

Power-up reset to 1111 1111

n+5

VID5VIID6VIII

n+6

n+7 n+8

D-Channel

7-85

+ 19 hidden pages